eccd1f0a14
Mechanically replace "SOC" with "ATOM" to match Linux. No functional change. Original Linux commit log follows: Instead of using the platform code names, use the correct platform names to identify the respective Intel NTB hardware. Authored by: Dave Jiang Obtained from: Linux (Dual BSD/GPL driver) Sponsored by: EMC / Isilon Storage Division
172 lines
6.1 KiB
C
172 lines
6.1 KiB
C
/*-
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* Copyright (C) 2013 Intel Corporation
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* Copyright (C) 2015 EMC Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _NTB_REGS_H_
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#define _NTB_REGS_H_
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#define NTB_LINK_STATUS_ACTIVE 0x2000
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#define NTB_LINK_SPEED_MASK 0x000f
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#define NTB_LINK_WIDTH_MASK 0x03f0
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#define NTB_LNK_STA_WIDTH(sta) (((sta) & NTB_LINK_WIDTH_MASK) >> 4)
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#define XEON_SNB_MW_COUNT 2
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#define XEON_HSX_SPLIT_MW_COUNT 3
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/* Reserve the uppermost bit for link interrupt */
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#define XEON_DB_COUNT 15
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#define XEON_DB_LINK 15
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#define XEON_DB_MSIX_VECTOR_COUNT 4
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#define XEON_DB_MSIX_VECTOR_SHIFT 5
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#define XEON_DB_LINK_BIT (1 << XEON_DB_LINK)
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#define XEON_SPAD_COUNT 16
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#define XEON_PCICMD_OFFSET 0x0504
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#define XEON_DEVCTRL_OFFSET 0x0598
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#define XEON_LINK_STATUS_OFFSET 0x01a2
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#define XEON_SLINK_STATUS_OFFSET 0x05a2
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#define XEON_PBAR2LMT_OFFSET 0x0000
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#define XEON_PBAR4LMT_OFFSET 0x0008
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#define XEON_PBAR5LMT_OFFSET 0x000c
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#define XEON_PBAR2XLAT_OFFSET 0x0010
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#define XEON_PBAR4XLAT_OFFSET 0x0018
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#define XEON_PBAR5XLAT_OFFSET 0x001c
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#define XEON_SBAR2LMT_OFFSET 0x0020
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#define XEON_SBAR4LMT_OFFSET 0x0028
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#define XEON_SBAR5LMT_OFFSET 0x002c
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#define XEON_SBAR2XLAT_OFFSET 0x0030
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#define XEON_SBAR4XLAT_OFFSET 0x0038
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#define XEON_SBAR5XLAT_OFFSET 0x003c
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#define XEON_SBAR0BASE_OFFSET 0x0040
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#define XEON_SBAR2BASE_OFFSET 0x0048
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#define XEON_SBAR4BASE_OFFSET 0x0050
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#define XEON_SBAR5BASE_OFFSET 0x0054
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#define XEON_NTBCNTL_OFFSET 0x0058
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#define XEON_SBDF_OFFSET 0x005c
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#define XEON_PDOORBELL_OFFSET 0x0060
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#define XEON_PDBMSK_OFFSET 0x0062
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#define XEON_SDOORBELL_OFFSET 0x0064
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#define XEON_SDBMSK_OFFSET 0x0066
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#define XEON_USMEMMISS 0x0070
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#define XEON_SPAD_OFFSET 0x0080
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#define XEON_SPADSEMA4_OFFSET 0x00c0
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#define XEON_WCCNTRL_OFFSET 0x00e0
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#define XEON_B2B_SPAD_OFFSET 0x0100
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#define XEON_B2B_DOORBELL_OFFSET 0x0140
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#define XEON_B2B_XLAT_OFFSETL 0x0144
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#define XEON_B2B_XLAT_OFFSETU 0x0148
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#define ATOM_MW_COUNT 2
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#define ATOM_DB_COUNT 34
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#define ATOM_DB_MSIX_VECTOR_COUNT 34
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#define ATOM_DB_MSIX_VECTOR_SHIFT 1
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#define ATOM_SPAD_COUNT 16
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#define ATOM_PCICMD_OFFSET 0xb004
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#define ATOM_MBAR23_OFFSET 0xb018
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#define ATOM_MBAR45_OFFSET 0xb020
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#define ATOM_DEVCTRL_OFFSET 0xb048
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#define ATOM_LINK_STATUS_OFFSET 0xb052
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#define ATOM_ERRCORSTS_OFFSET 0xb110
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#define ATOM_SBAR2XLAT_OFFSET 0x0008
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#define ATOM_SBAR4XLAT_OFFSET 0x0010
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#define ATOM_PDOORBELL_OFFSET 0x0020
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#define ATOM_PDBMSK_OFFSET 0x0028
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#define ATOM_NTBCNTL_OFFSET 0x0060
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#define ATOM_EBDF_OFFSET 0x0064
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#define ATOM_SPAD_OFFSET 0x0080
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#define ATOM_SPADSEMA_OFFSET 0x00c0
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#define ATOM_STKYSPAD_OFFSET 0x00c4
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#define ATOM_PBAR2XLAT_OFFSET 0x8008
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#define ATOM_PBAR4XLAT_OFFSET 0x8010
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#define ATOM_B2B_DOORBELL_OFFSET 0x8020
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#define ATOM_B2B_SPAD_OFFSET 0x8080
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#define ATOM_B2B_SPADSEMA_OFFSET 0x80c0
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#define ATOM_B2B_STKYSPAD_OFFSET 0x80c4
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#define ATOM_MODPHY_PCSREG4 0x1c004
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#define ATOM_MODPHY_PCSREG6 0x1c006
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#define ATOM_IP_BASE 0xc000
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#define ATOM_DESKEWSTS_OFFSET (ATOM_IP_BASE + 0x3024)
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#define ATOM_LTSSMERRSTS0_OFFSET (ATOM_IP_BASE + 0x3180)
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#define ATOM_LTSSMSTATEJMP_OFFSET (ATOM_IP_BASE + 0x3040)
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#define ATOM_IBSTERRRCRVSTS0_OFFSET (ATOM_IP_BASE + 0x3324)
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#define ATOM_DESKEWSTS_DBERR (1 << 15)
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#define ATOM_LTSSMERRSTS0_UNEXPECTEDEI (1 << 20)
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#define ATOM_LTSSMSTATEJMP_FORCEDETECT (1 << 2)
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#define ATOM_IBIST_ERR_OFLOW 0x7fff7fff
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#define NTB_CNTL_CFG_LOCK (1 << 0)
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#define NTB_CNTL_LINK_DISABLE (1 << 1)
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#define NTB_CNTL_S2P_BAR23_SNOOP (1 << 2)
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#define NTB_CNTL_P2S_BAR23_SNOOP (1 << 4)
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#define NTB_CNTL_S2P_BAR4_SNOOP (1 << 6)
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#define NTB_CNTL_P2S_BAR4_SNOOP (1 << 8)
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#define NTB_CNTL_S2P_BAR5_SNOOP (1 << 12)
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#define NTB_CNTL_P2S_BAR5_SNOOP (1 << 14)
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#define ATOM_CNTL_LINK_DOWN (1 << 16)
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#define XEON_PBAR23SZ_OFFSET 0x00d0
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#define XEON_PBAR45SZ_OFFSET 0x00d1
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#define XEON_PBAR4SZ_OFFSET 0x00d1
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#define XEON_PBAR5SZ_OFFSET 0x00d5
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#define XEON_SBAR23SZ_OFFSET 0x00d2
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#define XEON_SBAR4SZ_OFFSET 0x00d3
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#define XEON_SBAR5SZ_OFFSET 0x00d6
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#define NTB_PPD_OFFSET 0x00d4
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#define XEON_PPD_CONN_TYPE 0x0003
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#define XEON_PPD_DEV_TYPE 0x0010
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#define XEON_PPD_SPLIT_BAR 0x0040
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#define ATOM_PPD_INIT_LINK 0x0008
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#define ATOM_PPD_CONN_TYPE 0x0300
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#define ATOM_PPD_DEV_TYPE 0x1000
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/* All addresses are in low 32-bit space so 32-bit BARs can function */
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#define XEON_B2B_BAR0_USD_ADDR 0x1000000000000000ull
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#define XEON_B2B_BAR2_USD_ADDR64 0x2000000000000000ull
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#define XEON_B2B_BAR4_USD_ADDR64 0x4000000000000000ull
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#define XEON_B2B_BAR4_USD_ADDR32 0x20000000ull
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#define XEON_B2B_BAR5_USD_ADDR32 0x40000000ull
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#define XEON_B2B_BAR0_DSD_ADDR 0x9000000000000000ull
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#define XEON_B2B_BAR2_DSD_ADDR64 0xa000000000000000ull
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#define XEON_B2B_BAR4_DSD_ADDR64 0xc000000000000000ull
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#define XEON_B2B_BAR4_DSD_ADDR32 0xa0000000ull
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#define XEON_B2B_BAR5_DSD_ADDR32 0xc0000000ull
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/* The peer ntb secondary config space is 32KB fixed size */
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#define XEON_B2B_MIN_SIZE 0x8000
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/* XEON Shadowed MMIO Space */
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#define XEON_SHADOW_PDOORBELL_OFFSET 0x60
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#define XEON_SHADOW_SPAD_OFFSET 0x80
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#endif /* _NTB_REGS_H_ */
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