d5a51e03e7
the AMI PCI controllers using the 8LD firmware interface (40LD firmware will be supported as soon as I have hardware to test with). These controllers are rebadged by Dell as the PERC, as well as by HP and possibly other vendors.
217 lines
7.2 KiB
C
217 lines
7.2 KiB
C
/*-
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* Copyright (c) 1999 Michael Smith
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* We could actually use all 17 segments, but using only 16 means that
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* each scatter/gather map is 128 bytes in size, and thus we don't have to worry about
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* maps crossing page boundaries.
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*/
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#define AMR_NSEG 16
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#define AMR_CFG_BASE 0x10
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#define AMR_CFG_SIG 0xa0
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#define AMR_SIGNATURE 0x3344
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#define AMR_MAXCMD 255 /* ident = 0 not allowed */
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#define AMR_MAXLD 40
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#define AMR_BLKSIZE 512
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struct amr_softc;
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/*
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* Per-logical-drive datastructure
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*/
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struct amr_logdrive
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{
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u_int32_t al_size;
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int al_state;
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int al_properties;
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/* synthetic geometry */
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int al_cylinders;
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int al_heads;
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int al_sectors;
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/* driver */
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device_t al_disk;
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};
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/*
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* Per-command control structure.
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*/
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struct amr_command
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{
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TAILQ_ENTRY(amr_command) ac_link;
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struct amr_softc *ac_sc;
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u_int8_t ac_slot;
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int ac_status;
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#define AMR_STATUS_BUSY 0xffff
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#define AMR_STATUS_WEDGED 0xdead
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struct amr_mailbox ac_mailbox;
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u_int32_t ac_sgphys;
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int ac_nsgent;
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int ac_flags;
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#define AMR_CMD_DATAIN (1<<0)
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#define AMR_CMD_DATAOUT (1<<1)
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#define AMR_CMD_PRIORITY (1<<2)
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time_t ac_stamp;
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void *ac_data;
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size_t ac_length;
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bus_dmamap_t ac_dmamap;
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u_int32_t ac_dataphys;
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void (* ac_complete)(struct amr_command *ac);
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void *ac_private;
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};
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struct amr_softc
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{
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/* bus attachments */
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device_t amr_dev;
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struct resource *amr_reg; /* control registers */
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bus_space_handle_t amr_bhandle;
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bus_space_tag_t amr_btag;
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bus_dma_tag_t amr_parent_dmat; /* parent DMA tag */
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bus_dma_tag_t amr_buffer_dmat; /* data buffer DMA tag */
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struct resource *amr_irq; /* interrupt */
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void *amr_intr;
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/* mailbox */
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struct amr_mailbox *amr_mailbox;
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struct amr_mailbox64 *amr_mailbox64;
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u_int32_t amr_mailboxphys;
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bus_dma_tag_t amr_mailbox_dmat;
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bus_dmamap_t amr_mailbox_dmamap;
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/* scatter/gather lists and their controller-visible mappings */
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struct amr_sgentry *amr_sgtable; /* s/g lists */
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u_int32_t amr_sgbusaddr; /* s/g table base address in bus space */
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bus_dma_tag_t amr_sg_dmat; /* s/g buffer DMA tag */
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bus_dmamap_t amr_sg_dmamap; /* map for s/g buffers */
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/* controller limits and features */
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int amr_maxio; /* maximum number of I/O transactions */
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int amr_maxdrives; /* max number of logical drives */
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/* connected logical drives */
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struct amr_logdrive amr_drive[AMR_MAXLD];
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/* controller status */
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int amr_state;
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#define AMR_STATE_OPEN (1<<0)
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#define AMR_STATE_SUSPEND (1<<1)
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#define AMR_STATE_INTEN (1<<2)
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#define AMR_STATE_SHUTDOWN (1<<3)
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/* per-controller queues */
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struct buf_queue_head amr_bufq; /* pending I/O */
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int amr_waitbufs;
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struct amr_command *amr_busycmd[AMR_MAXCMD];
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int amr_busycmdcount;
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TAILQ_HEAD(,amr_command) amr_donecmds;
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int amr_donecmdcount;
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TAILQ_HEAD(,amr_command) amr_freecmds;
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/* controller type-specific support */
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int amr_type;
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#define AMR_TYPE_STD 0
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#define AMR_TYPE_QUARTZ 1
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void (* amr_submit_command)(struct amr_softc *sc);
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int (* amr_get_work)(struct amr_softc *sc, struct amr_mailbox *mbsave);
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void (* amr_attach_mailbox)(struct amr_softc *sc);
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};
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/*
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* I/O primitives
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*/
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/* Quartz */
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#define AMR_QPUT_IDB(sc, val) bus_space_write_4(sc->amr_btag, sc->amr_bhandle, AMR_QIDB, val)
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#define AMR_QGET_IDB(sc) bus_space_read_4 (sc->amr_btag, sc->amr_bhandle, AMR_QIDB)
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#define AMR_QPUT_ODB(sc, val) bus_space_write_4(sc->amr_btag, sc->amr_bhandle, AMR_QODB, val)
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#define AMR_QGET_ODB(sc) bus_space_read_4 (sc->amr_btag, sc->amr_bhandle, AMR_QODB)
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/* Standard */
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#define AMR_SPUT_ISTAT(sc, val) bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_SINTR, val)
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#define AMR_SGET_ISTAT(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SINTR)
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#define AMR_SACK_INTERRUPT(sc) bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_SCMD, AMR_SCMD_ACKINTR)
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#define AMR_SPOST_COMMAND(sc) bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_SCMD, AMR_SCMD_POST)
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#define AMR_SGET_MBSTAT(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_BUSY)
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#define AMR_SENABLE_INTR(sc) \
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bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_STOGGLE, \
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bus_space_read_1(sc->amr_btag, sc->amr_bhandle, AMR_STOGGLE) | AMR_STOGL_IENABLE)
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#define AMR_SDISABLE_INTR(sc) \
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bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_STOGGLE, \
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bus_space_read_1(sc->amr_btag, sc->amr_bhandle, AMR_STOGGLE) & ~AMR_STOGL_IENABLE)
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#define AMR_SBYTE_SET(sc, reg, val) bus_space_write_1(sc->amr_btag, sc->amr_bhandle, reg, val)
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/*
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* Interface between bus connections and driver core.
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*/
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extern void amr_free(struct amr_softc *sc);
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extern int amr_attach(struct amr_softc *sc);
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extern void amr_startup(struct amr_softc *sc);
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extern void amr_intr(void *data);
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extern int amr_detach(device_t dev);
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extern int amr_shutdown(device_t dev);
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extern int amr_suspend(device_t dev);
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extern int amr_resume(device_t dev);
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extern d_open_t amr_open;
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extern d_close_t amr_close;
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extern d_ioctl_t amr_ioctl;
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extern devclass_t amr_devclass;
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/*
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* MegaRAID logical disk driver
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*/
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struct amrd_softc
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{
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device_t amrd_dev;
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struct amr_softc *amrd_controller;
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struct amr_logdrive *amrd_drive;
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struct disk amrd_disk;
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struct devstat amrd_stats;
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struct disklabel amrd_label;
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int amrd_unit;
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int amrd_flags;
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#define AMRD_OPEN (1<<0) /* drive is open (can't shut down) */
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};
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/*
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* Interface between driver core and disk driver (should be using a bus?)
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*/
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extern int amr_submit_buf(struct amr_softc *sc, struct buf *bp);
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extern int amr_submit_ioctl(struct amr_softc *sc, struct amr_logdrive *drive, u_long cmd,
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caddr_t addr, int32_t flag, struct proc *p);
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extern void amrd_intr(void *data);
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