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LLVM 5.0.0 Release Notes
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========================
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.. contents::
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:local:
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Introduction
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============
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This document contains the release notes for the LLVM Compiler Infrastructure,
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release 5.0.0. Here we describe the status of LLVM, including major improvements
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from the previous release, improvements in various subprojects of LLVM, and
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some of the current users of the code. All LLVM releases may be downloaded
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from the `LLVM releases web site <http://llvm.org/releases/>`_.
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For more information about LLVM, including information about the latest
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release, please check out the `main LLVM web site <http://llvm.org/>`_. If you
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have questions or comments, the `LLVM Developer's Mailing List
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<http://lists.llvm.org/mailman/listinfo/llvm-dev>`_ is a good place to send
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them.
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Non-comprehensive list of changes in this release
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=================================================
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* LLVM's ``WeakVH`` has been renamed to ``WeakTrackingVH`` and a new ``WeakVH``
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has been introduced. The new ``WeakVH`` nulls itself out on deletion, but
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does not track values across RAUW.
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* A new library named ``BinaryFormat`` has been created which holds a collection
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of code which previously lived in ``Support``. This includes the
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``file_magic`` structure and ``identify_magic`` functions, as well as all the
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structure and type definitions for DWARF, ELF, COFF, WASM, and MachO file
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formats.
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* The tool ``llvm-pdbdump`` has been renamed ``llvm-pdbutil`` to better reflect
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its nature as a general purpose PDB manipulation / diagnostics tool that does
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more than just dumping contents.
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* The ``BBVectorize`` pass has been removed. It was fully replaced and no
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longer used back in 2014 but we didn't get around to removing it. Now it is
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gone. The SLP vectorizer is the suggested non-loop vectorization pass.
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* A new tool opt-viewer.py has been added to visualize optimization remarks in
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HTML. The tool processes the YAML files produced by clang with the
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-fsave-optimization-record option.
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* A new CMake macro ``LLVM_REVERSE_ITERATION`` has been added. If enabled, all
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supported unordered LLVM containers would be iterated in reverse order. This
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is useful for uncovering non-determinism caused by iteration of unordered
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containers. Currently, it supports reverse iteration of SmallPtrSet and
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DenseMap.
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* A new tool ``llvm-dlltool`` has been added to create short import libraries
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from GNU style definition files. The tool utilizes the PE COFF SPEC Import
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Library Format and PE COFF Auxiliary Weak Externals Format to achieve
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compatibility with LLD and MSVC LINK.
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Changes to the LLVM IR
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----------------------
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* The datalayout string may now indicate an address space to use for
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the pointer type of ``alloca`` rather than the default of 0.
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* Added ``speculatable`` attribute indicating a function which has no
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side-effects which could inhibit hoisting of calls.
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Changes to the Arm Targets
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--------------------------
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During this release the AArch64 target has:
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* A much improved Global ISel at O0.
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* Support for ARMv8.1 8.2 and 8.3 instructions.
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* New scheduler information for ThunderX2.
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* Some SVE type changes but not much more than that.
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* Made instruction fusion more aggressive, resulting in speedups
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for code making use of AArch64 AES instructions. AES fusion has been
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enabled for most Cortex-A cores and the AArch64MacroFusion pass was moved
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to the generic MacroFusion pass.
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* Added preferred function alignments for most Cortex-A cores.
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* OpenMP "offload-to-self" base support.
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During this release the ARM target has:
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* Improved, but still mostly broken, Global ISel.
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* Scheduling models update, new schedule for Cortex-A57.
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* Hardware breakpoint support in LLDB.
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* New assembler error handling, with spelling corrections and multiple
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suggestions on how to fix problems.
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* Improved mixed ARM/Thumb code generation. Some cases in which wrong
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relocations were emitted have been fixed.
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* Added initial support for mixed ARM/Thumb link-time optimization, using the
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thumb-mode target feature.
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Changes to the MIPS Target
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--------------------------
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* The microMIPS64R6 backend is deprecated and will be removed in the next
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release.
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* The MIPS backend now directly supports vector types for arguments and return
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values (previously this required ABI specific LLVM IR).
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* Added documentation for how the MIPS backend handles address lowering.
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* Added a GCC compatible option -m(no-)madd4 to control the generation of four
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operand multiply addition/subtraction instructions.
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* Added basic support for the XRay instrumentation system.
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* Added support for more assembly aliases and macros.
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* Added support for the ``micromips`` and ``nomicromips`` function attributes
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which control micromips code generation on a per function basis.
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* Added the ``long-calls`` feature for non-pic environments. This feature is
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used where the callee is out of range of the caller using a standard call
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sequence. It must be enabled specifically.
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* Added support for performing microMIPS code generation via function
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attributes.
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* Added experimental support for the static relocation model for the N64 ABI.
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* Added partial support for the MT ASE.
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* Added basic support for code size reduction for microMIPS.
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* Fixed numerous bugs including: multi-precision arithmetic support, various
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vectorization bugs, debug information for thread local variables, debug
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sections lacking the correct flags, crashing when disassembling sections
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whose size is not a multiple of two or four.
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Changes to the PowerPC Target
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-----------------------------
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* Additional support and exploitation of POWER ISA 3.0: vabsdub, vabsduh,
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vabsduw, modsw, moduw, modsd, modud, lxv, stxv, vextublx, vextubrx, vextuhlx,
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vextuhrx, vextuwlx, vextuwrx, vextsb2w, vextsb2d, vextsh2w, vextsh2d, and
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vextsw2d
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* Implemented Optimal Code Sequences from The PowerPC Compiler Writer's Guide.
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* Enable -fomit-frame-pointer by default.
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* Improved handling of bit reverse intrinsic.
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* Improved handling of memcpy and memcmp functions.
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* Improved handling of branches with static branch hints.
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* Improved codegen for atomic load_acquire.
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* Improved block placement during code layout
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* Many improvements to instruction selection and code generation
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Changes to the X86 Target
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-------------------------
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* Added initial AMD Ryzen (znver1) scheduler support.
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* Added support for Intel Goldmont CPUs.
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* Add support for avx512vpopcntdq instructions.
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* Added heuristics to convert CMOV into branches when it may be profitable.
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* More aggressive inlining of memcmp calls.
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* Improve vXi64 shuffles on 32-bit targets.
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* Improved use of PMOVMSKB for any_of/all_of comparision reductions.
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* Improved Silvermont, Sandybridge, and Jaguar (btver2) schedulers.
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* Improved support for AVX512 vector rotations.
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* Added support for AMD Lightweight Profiling (LWP) instructions.
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* Avoid using slow LEA instructions.
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* Use alternative sequences for multiply by constant.
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* Improved lowering of strided shuffles.
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* Improved the AVX512 cost model used by the vectorizer.
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* Fix scalar code performance when AVX512 is enabled by making i1's illegal.
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* Fixed many inline assembly bugs.
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* Preliminary support for tracing NetBSD processes and core files with a single
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thread in LLDB.
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Changes to the AMDGPU Target
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-----------------------------
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* Initial gfx9 support
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Changes to the AVR Target
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-----------------------------
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This release consists mainly of bugfixes and implementations of features
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required for compiling basic Rust programs.
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* Enable the branch relaxation pass so that we don't crash on large
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stack load/stores
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* Add support for lowering bit-rotations to the native ``ror`` and ``rol``
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instructions
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* Fix bug where function pointers were treated as pointers to RAM and not
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pointers to program memory
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* Fix broken code generation for shift-by-variable expressions
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* Support zero-sized types in argument lists; this is impossible in C,
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but possible in Rust
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Changes to the C API
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--------------------
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* Deprecated the ``LLVMAddBBVectorizePass`` interface since the ``BBVectorize``
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pass has been removed. It is now a no-op and will be removed in the next
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release. Use ``LLVMAddSLPVectorizePass`` instead to get the supported SLP
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vectorizer.
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External Open Source Projects Using LLVM 5
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==========================================
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Zig Programming Language
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------------------------
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`Zig <http://ziglang.org>`_ is an open-source programming language designed
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for robustness, optimality, and clarity. It integrates closely with C and is
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intended to eventually take the place of C. It uses LLVM to produce highly
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optimized native code and to cross-compile for any target out of the box. Zig
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is in alpha; with a beta release expected in September.
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LDC - the LLVM-based D compiler
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-------------------------------
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`D <http://dlang.org>`_ is a language with C-like syntax and static typing. It
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pragmatically combines efficiency, control, and modeling power, with safety and
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programmer productivity. D supports powerful concepts like Compile-Time Function
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Execution (CTFE) and Template Meta-Programming, provides an innovative approach
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to concurrency and offers many classical paradigms.
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`LDC <http://wiki.dlang.org/LDC>`_ uses the frontend from the reference compiler
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combined with LLVM as backend to produce efficient native code. LDC targets
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x86/x86_64 systems like Linux, OS X, FreeBSD and Windows and also Linux on ARM
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and PowerPC (32/64 bit). Ports to other architectures like AArch64 and MIPS64
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are underway.
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Additional Information
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======================
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A wide variety of additional information is available on the `LLVM web page
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<http://llvm.org/>`_, in particular in the `documentation
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<http://llvm.org/docs/>`_ section. The web page also contains versions of the
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API documentation which is up-to-date with the Subversion version of the source
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code. You can access versions of these documents specific to this release by
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going into the ``llvm/docs/`` directory in the LLVM tree.
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If you have any questions or comments about LLVM, please feel free to contact
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us via the `mailing lists <http://llvm.org/docs/#maillist>`_.
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