af3dc4a7ca
Mainly focus on files that use BSD 2-Clause license, however the tool I was using misidentified many licenses so this was mostly a manual - error prone - task. The Software Package Data Exchange (SPDX) group provides a specification to make it easier for automated tools to detect and summarize well known opensource licenses. We are gradually adopting the specification, noting that the tags are considered only advisory and do not, in any way, superceed or replace the license texts.
611 lines
19 KiB
C
611 lines
19 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2005-2008 Olivier Houchard. All rights reserved.
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* Copyright (c) 2005-2012 Warner Losh. All rights reserved.
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* Copyright (c) 2007-2014 Ian Lepore. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Board init code for the TSC4370, and all other current TSC mainboards.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <arm/at91/at91_pioreg.h>
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#include <arm/at91/at91_piovar.h>
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#include <arm/at91/at91_pmcreg.h>
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#include <arm/at91/at91_pmcvar.h>
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#include <arm/at91/at91_twireg.h>
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#include <arm/at91/at91_usartreg.h>
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#include <arm/at91/at91board.h>
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#include <arm/at91/at91var.h>
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#include <arm/at91/at91rm9200var.h>
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#include <arm/at91/at91rm92reg.h>
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#include <arm/at91/if_atereg.h>
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#include <machine/board.h>
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#include <machine/cpu.h>
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#include <machine/machdep.h>
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#include <net/ethernet.h>
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#include <sys/reboot.h>
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/*
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* RD4HW()/WR4HW() read and write at91rm9200 hardware register space directly.
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* They serve the same purpose as the RD4()/WR4() idiom you see in many drivers,
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* except that those translate to bus_space calls, but in this code we need to
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* access the registers directly before the at91 bus_space stuff is set up.
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*/
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static inline uint32_t
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RD4HW(uint32_t devbase, uint32_t regoff)
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{
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return *(volatile uint32_t *)(AT91_BASE + devbase + regoff);
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}
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static inline void
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WR4HW(uint32_t devbase, uint32_t regoff, uint32_t val)
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{
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*(volatile uint32_t *)(AT91_BASE + devbase + regoff) = val;
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}
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/*
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* This is the same calculation the at91 uart driver does, we use it to update
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* the console uart baud rate after changing the MCK rate.
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*/
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#ifndef BAUD2DIVISOR
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#define BAUD2DIVISOR(b) \
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((((at91_master_clock * 10) / ((b) * 16)) + 5) / 10)
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#endif
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/*
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* If doing an in-house build, use tsc_bootinfo.h which is shared with our
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* custom boot2. Otherwise define some crucial bits of it here, enough to allow
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* this code to compile.
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*/
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#ifdef TSC_BUILD
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#include <machine/tsc_bootinfo.h>
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#else
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struct tsc_bootinfo {
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uint32_t bi_size;
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uint32_t bi_version;
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uint32_t bi_flags; /* RB_xxxxx flags from sys/reboot.h */
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char bi_rootdevname[64];
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};
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#define TSC_BOOTINFO_MAGIC 0x06C30000
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#endif
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static struct arm_boot_params boot_params;
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static struct tsc_bootinfo inkernel_bootinfo;
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/*
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* Change the master clock config and wait for it to stabilize.
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*/
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static void
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change_mckr(uint32_t mckr)
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{
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int i;
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WR4HW(AT91RM92_PMC_BASE, PMC_MCKR, mckr);
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for (i = 0; i < 1000; ++i)
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if ((RD4HW(AT91RM92_PMC_BASE, PMC_SR) & PMC_IER_MCKRDY))
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return;
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}
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/*
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* Allow the master clock frequency to be changed from whatever the bootloader
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* set up, because sometimes it's harder to change/update a bootloader than it
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* is to change/update the kernel once a product is in the field.
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*/
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static void
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master_clock_init(void)
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{
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uint32_t mckr = RD4HW(AT91RM92_PMC_BASE, PMC_MCKR);
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int hintvalue = 0;
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int newmckr = 0;
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/*
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* If there's a hint that specifies the contents of MCKR, use it
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* without question (it had better be right).
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*
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* If there's a "mckfreq" hint it might be in hertz or mhz (convert the
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* latter to hz). Calculate the new MCK divider. If the CPU frequency
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* is not a sane multiple of the hinted MCK frequency this is likely to
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* behave badly. The moral is: don't hint at impossibilities.
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*/
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if (resource_int_value("at91", 0, "mckr", &hintvalue) == 0) {
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newmckr = hintvalue;
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} else {
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hintvalue = 90; /* Default to 90mhz if not specified. */
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resource_int_value("at91", 0, "mckfreq", &hintvalue);
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if (hintvalue != 0) {
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if (hintvalue < 1000)
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hintvalue *= 1000000;
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if (hintvalue != at91_master_clock) {
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uint32_t divider;
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struct at91_pmc_clock * cpuclk;
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cpuclk = at91_pmc_clock_ref("cpu");
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divider = (cpuclk->hz / hintvalue) - 1;
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newmckr = (mckr & 0xFFFFFCFF) | ((divider & 0x03) << 8);
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at91_pmc_clock_deref(cpuclk);
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}
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}
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}
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/* If the new mckr value is different than what's in the register now,
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* make the change and wait for the clocks to settle (MCKRDY status).
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*
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* MCKRDY will never be asserted unless either the selected clock or the
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* prescaler value changes (but not both at once) [this is detailed in
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* the rm9200 errata]. This code assumes the prescaler value is always
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* zero and that by time we get to here we're running on something other
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* than the slow clock, so to change the mckr divider we first change
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* back to the slow clock (keeping prescaler and divider unchanged),
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* then go back to the original selected clock with the new divider.
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*
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* After changing MCK, go re-init everything clock-related, and reset
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* the baud rate generator for the console (doing this here is kind of a
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* rude hack, but hey, you do what you have to to run MCK faster).
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*/
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if (newmckr != 0 && newmckr != mckr) {
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if (mckr & 0x03)
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change_mckr(mckr & ~0x03);
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change_mckr(newmckr);
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at91_pmc_init_clock();
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WR4HW(AT91RM92_DBGU_BASE, USART_BRGR, BAUD2DIVISOR(115200));
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}
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}
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/*
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* TSC-specific code to read the ID eeprom on the mainboard and extract the
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* unit's EUI-64 which gets translated into a MAC-48 for ethernet.
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*/
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static void
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eeprom_init(void)
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{
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const uint32_t twiHz = 400000;
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const uint32_t twiCkDiv = 1 << 16;
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const uint32_t twiChDiv = ((at91_master_clock / twiHz) - 2) << 8;
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const uint32_t twiClDiv = ((at91_master_clock / twiHz) - 2);
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/*
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* Set the TWCK and TWD lines for Periph A, no pullup, open-drain.
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*/
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at91_pio_use_periph_a(AT91RM92_PIOA_BASE,
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AT91C_PIO_PA25 | AT91C_PIO_PA26, 0);
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at91_pio_gpio_high_z(AT91RM92_PIOA_BASE, AT91C_PIO_PA25, 1);
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/*
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* Enable TWI power (irq numbers are also device IDs for power)
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*/
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WR4HW(AT91RM92_PMC_BASE, PMC_PCER, 1u << AT91RM92_IRQ_TWI);
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/*
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* Disable TWI interrupts, reset device, enable Master mode,
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* disable Slave mode, set the clock.
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*/
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WR4HW(AT91RM92_TWI_BASE, TWI_IDR, 0xffffffff);
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WR4HW(AT91RM92_TWI_BASE, TWI_CR, TWI_CR_SWRST);
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WR4HW(AT91RM92_TWI_BASE, TWI_CR, TWI_CR_MSEN | TWI_CR_SVDIS);
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WR4HW(AT91RM92_TWI_BASE, TWI_CWGR, twiCkDiv | twiChDiv | twiClDiv);
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}
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static int
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eeprom_read(uint32_t EE_DEV_ADDR, uint32_t ee_off, void * buf, uint32_t size)
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{
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uint8_t *bufptr = (uint8_t *)buf;
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uint32_t status;
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uint32_t count;
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/* Clean out any old status and received byte. */
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status = RD4HW(AT91RM92_TWI_BASE, TWI_SR);
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status = RD4HW(AT91RM92_TWI_BASE, TWI_RHR);
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/* Set the TWI Master Mode Register */
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WR4HW(AT91RM92_TWI_BASE, TWI_MMR,
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TWI_MMR_DADR(EE_DEV_ADDR) | TWI_MMR_IADRSZ(2) | TWI_MMR_MREAD);
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/* Set TWI Internal Address Register */
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WR4HW(AT91RM92_TWI_BASE, TWI_IADR, ee_off);
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/* Start transfer */
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WR4HW(AT91RM92_TWI_BASE, TWI_CR, TWI_CR_START);
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status = RD4HW(AT91RM92_TWI_BASE, TWI_SR);
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while (size-- > 1){
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/* Wait until Receive Holding Register is full */
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count = 1000000;
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while (!(RD4HW(AT91RM92_TWI_BASE, TWI_SR) & TWI_SR_RXRDY) &&
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--count != 0)
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continue;
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if (count <= 0)
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return -1;
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/* Read and store byte */
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*bufptr++ = (uint8_t)RD4HW(AT91RM92_TWI_BASE, TWI_RHR);
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}
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WR4HW(AT91RM92_TWI_BASE, TWI_CR, TWI_CR_STOP);
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status = RD4HW(AT91RM92_TWI_BASE, TWI_SR);
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/* Wait until transfer is finished */
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while (!(RD4HW(AT91RM92_TWI_BASE, TWI_SR) & TWI_SR_TXCOMP))
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continue;
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/* Read last byte */
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*bufptr = (uint8_t)RD4HW(AT91RM92_TWI_BASE, TWI_RHR);
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return 0;
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}
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static int
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set_mac_from_idprom(void)
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{
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#define SIGNATURE_SIZE 4
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#define EETYPE_SIZE 2
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#define BSLENGTH_SIZE 2
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#define RAW_SIZE 52
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#define EUI64_SIZE 8
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#define BS_SIGNATURE 0x21706d69
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#define BSO_SIGNATURE 0x216f7362
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#define DEVOFFSET_BSO_SIGNATURE 0x20
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#define OFFSET_BS_SIGNATURE 0
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#define SIZE_BS_SIGNATURE SIGNATURE_SIZE
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#define OFFSET_EETYPE (OFFSET_BS_SIGNATURE + SIZE_BS_SIGNATURE)
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#define SIZE_EETYPE EETYPE_SIZE
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#define OFFSET_BOOTSECTSIZE (OFFSET_EETYPE + SIZE_EETYPE)
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#define SIZE_BOOTSECTSIZE BSLENGTH_SIZE
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#define OFFSET_RAW (OFFSET_BOOTSECTSIZE + SIZE_BOOTSECTSIZE)
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#define OFFSET_EUI64 (OFFSET_RAW + RAW_SIZE)
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#define EE_DEV_ADDR 0xA0 /* eeprom is AT24C256 at address 0xA0 */
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int status;
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uint32_t dev_offset = 0;
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uint32_t sig;
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uint8_t eui64[EUI64_SIZE];
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uint8_t eaddr[ETHER_ADDR_LEN];
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eeprom_init();
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/* Check for the boot section signature at offset 0. */
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status = eeprom_read(EE_DEV_ADDR, OFFSET_BS_SIGNATURE, &sig, sizeof(sig));
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if (status == -1)
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return -1;
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if (sig != BS_SIGNATURE) {
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/* Check for the boot section offset signature. */
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status = eeprom_read(EE_DEV_ADDR,
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DEVOFFSET_BSO_SIGNATURE, &sig, sizeof(sig));
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if ((status == -1) || (sig != BSO_SIGNATURE))
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return -1;
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/* Read the device offset of the boot section structure. */
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status = eeprom_read(EE_DEV_ADDR,
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DEVOFFSET_BSO_SIGNATURE + sizeof(sig),
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&dev_offset, sizeof(dev_offset));
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if (status == -1)
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return -1;
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/* Check for the boot section signature. */
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status = eeprom_read(EE_DEV_ADDR,
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dev_offset + OFFSET_BS_SIGNATURE, &sig, sizeof(sig));
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if ((status == -1) || (sig != BS_SIGNATURE))
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return -1;
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}
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dev_offset += OFFSET_EUI64;
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/* Read the EUI64 from the device. */
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if (eeprom_read(EE_DEV_ADDR, dev_offset, eui64, sizeof(eui64)) == -1)
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return -1;
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/* Transcribe the EUI-64 to a MAC-48.
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*
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* Given an EUI-64 of aa:bb:cc:dd:ee:ff:gg:hh
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*
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* if (ff is zero and ee is non-zero)
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* mac is aa:bb:cc:ee:gg:hh
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* else
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* mac is aa:bb:cc:ff:gg:hh
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*
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* This logic fixes a glitch in our mfg process in which the ff byte was
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* always zero and the ee byte contained a non-zero value. This
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* resulted in duplicate MAC addresses because we discarded the ee byte.
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* Now they've fixed the process so that the ff byte is non-zero and
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* unique addresses are formed from the ff:gg:hh bytes. If the ff byte
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* is zero, then we have a unit manufactured during the glitch era, and
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* we fix the problem by grabbing the ee byte rather than the ff byte.
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*/
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eaddr[0] = eui64[0];
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eaddr[1] = eui64[1];
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eaddr[2] = eui64[2];
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eaddr[3] = eui64[5];
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eaddr[4] = eui64[6];
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eaddr[5] = eui64[7];
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if (eui64[5] == 0 && eui64[4] != 0) {
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eaddr[3] = eui64[4];
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}
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/*
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* Set the address in the hardware regs where the ate driver
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* looks for it.
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*/
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WR4HW(AT91RM92_EMAC_BASE, ETH_SA1L,
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(eaddr[3] << 24) | (eaddr[2] << 16) | (eaddr[1] << 8) | eaddr[0]);
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WR4HW(AT91RM92_EMAC_BASE, ETH_SA1H,
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(eaddr[5] << 8) | (eaddr[4]));
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printf(
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"ID: EUI-64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n"
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" MAC-48 %02x:%02x:%02x:%02x:%02x:%02x\n"
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" read from i2c device 0x%02X offset 0x%x\n",
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eui64[0], eui64[1], eui64[2], eui64[3],
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eui64[4], eui64[5], eui64[6], eui64[7],
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eaddr[0], eaddr[1], eaddr[2],
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eaddr[3], eaddr[4], eaddr[5],
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EE_DEV_ADDR, dev_offset);
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return (0);
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}
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/*
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* Assign SPI chip select pins based on which chip selects are found in hints.
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*/
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static void
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assign_spi_pins(void)
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{
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struct {
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uint32_t num;
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const char * name;
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} chipsel_pins[] = {
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{ AT91C_PIO_PA3, "PA3", },
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{ AT91C_PIO_PA4, "PA4", },
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{ AT91C_PIO_PA5, "PA5", },
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{ AT91C_PIO_PA6, "PA6", },
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};
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int anchor = 0;
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uint32_t chipsel_inuse = 0;
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/*
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* Search through all device hints looking for any that have
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* ".at=spibus0". For each one found, ensure that there is also a
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* chip select hint ".cs=<num>" and that <num> is 0-3, and assign the
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* corresponding pin to the SPI peripheral. Whine if we find a SPI
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* device with a missing or invalid chipsel hint.
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*/
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for (;;) {
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const char * rName = "";
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int unit = 0;
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int cs = 0;
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int ret;
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ret = resource_find_match(&anchor, &rName, &unit, "at", "spibus0");
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if (ret != 0)
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break;
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ret = resource_int_value(rName, unit, "cs", &cs);
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if (ret != 0) {
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printf( "Error: hint for SPI device %s%d "
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"without a chip select hint; "
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"device will not function.\n",
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rName, unit);
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continue;
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}
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if (cs < 0 || cs > 3) {
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printf( "Error: hint for SPI device %s%d "
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"contains an invalid chip select "
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"value: %d\n",
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rName, unit, cs);
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continue;
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}
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if (chipsel_inuse & (1 << cs)) {
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printf( "Error: hint for SPI device %s%d "
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"specifies chip select %d, which "
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"is already used by another device\n",
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rName, unit, cs);
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continue;
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}
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chipsel_inuse |= 1 << cs;
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at91_pio_use_periph_a(AT91RM92_PIOA_BASE,
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chipsel_pins[cs].num, 1);
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printf( "Configured pin %s as SPI chip "
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"select %d for %s%d\n",
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chipsel_pins[cs].name, cs, rName, unit);
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}
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/*
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* If there were hints for any SPI devices, assign the basic SPI IO pins
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* and enable SPI power (irq numbers are also device IDs for power).
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*/
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if (chipsel_inuse != 0) {
|
|
at91_pio_use_periph_a(AT91RM92_PIOA_BASE,
|
|
AT91C_PIO_PA1 | AT91C_PIO_PA0 | AT91C_PIO_PA2, 0);
|
|
WR4HW(AT91RM92_PMC_BASE, PMC_PCER, 1u << AT91RM92_IRQ_SPI);
|
|
}
|
|
}
|
|
|
|
BOARD_INIT long
|
|
board_init(void)
|
|
{
|
|
int is_bga, rev_mii;
|
|
|
|
/*
|
|
* Deal with bootinfo (if any) passed in from the boot2 bootloader and
|
|
* copied to the static inkernel_bootinfo earlier in the init. Do this
|
|
* early so that bootverbose is set from this point on.
|
|
*/
|
|
if (inkernel_bootinfo.bi_size > 0 &&
|
|
(inkernel_bootinfo.bi_flags & RB_BOOTINFO)) {
|
|
struct tsc_bootinfo *bip = &inkernel_bootinfo;
|
|
printf("TSC_BOOTINFO: size %u howtoflags=0x%08x rootdev='%s'\n",
|
|
bip->bi_size, bip->bi_flags, bip->bi_rootdevname);
|
|
boothowto = bip->bi_flags;
|
|
bootverbose = (boothowto & RB_VERBOSE);
|
|
if (bip->bi_rootdevname[0] != 0)
|
|
rootdevnames[0] = bip->bi_rootdevname;
|
|
}
|
|
|
|
/*
|
|
* The only way to know if we're in a BGA package (and thus have PIOD)
|
|
* is to be told via a hint; there's nothing detectable in the silicon.
|
|
* This is esentially an rm92-specific extension to getting the chip ID
|
|
* (which was done by at91_machdep just before calling this routine).
|
|
* If it is the BGA package, enable the clock for PIOD.
|
|
*/
|
|
is_bga = 0;
|
|
resource_int_value("at91", 0, "is_bga_package", &is_bga);
|
|
|
|
if (is_bga)
|
|
WR4HW(AT91RM92_PMC_BASE, PMC_PCER, 1u << AT91RM92_IRQ_PIOD);
|
|
|
|
#if __FreeBSD_version >= 1000000
|
|
at91rm9200_set_subtype(is_bga ? AT91_ST_RM9200_BGA :
|
|
AT91_ST_RM9200_PQFP);
|
|
#endif
|
|
|
|
/*
|
|
* Go reprogram the MCK frequency based on hints.
|
|
*/
|
|
master_clock_init();
|
|
|
|
/* From this point on you can use printf. */
|
|
|
|
/*
|
|
* Configure UARTs.
|
|
*/
|
|
at91rm9200_config_uart(AT91_ID_DBGU, 0, 0); /* DBGU just Tx and Rx */
|
|
at91rm9200_config_uart(AT91RM9200_ID_USART0, 1, 0); /* Tx and Rx */
|
|
at91rm9200_config_uart(AT91RM9200_ID_USART1, 2, 0); /* Tx and Rx */
|
|
at91rm9200_config_uart(AT91RM9200_ID_USART2, 3, 0); /* Tx and Rx */
|
|
at91rm9200_config_uart(AT91RM9200_ID_USART3, 4, 0); /* Tx and Rx */
|
|
|
|
/*
|
|
* Configure MCI (sdcard)
|
|
*/
|
|
at91rm9200_config_mci(0);
|
|
|
|
/*
|
|
* Assign the pins needed by the emac device, and power it up. Also,
|
|
* configure it for RMII operation unless the 'revmii_mode' hint is set,
|
|
* in which case configure the full set of MII pins. The revmii_mode
|
|
* hint is for so-called reverse-MII, used for connections to a Broadcom
|
|
* 5325E switch on some boards. Note that order is important here:
|
|
* configure pins, then power on the device, then access the device's
|
|
* config registers.
|
|
*/
|
|
rev_mii = 0;
|
|
resource_int_value("ate", 0, "phy_revmii_mode", &rev_mii);
|
|
|
|
at91_pio_use_periph_a(AT91RM92_PIOA_BASE,
|
|
AT91C_PIO_PA7 | AT91C_PIO_PA8 | AT91C_PIO_PA9 |
|
|
AT91C_PIO_PA10 | AT91C_PIO_PA11 | AT91C_PIO_PA12 |
|
|
AT91C_PIO_PA13 | AT91C_PIO_PA14 | AT91C_PIO_PA15 |
|
|
AT91C_PIO_PA16, 0);
|
|
if (rev_mii) {
|
|
at91_pio_use_periph_b(AT91RM92_PIOB_BASE,
|
|
AT91C_PIO_PB12 | AT91C_PIO_PB13 | AT91C_PIO_PB14 |
|
|
AT91C_PIO_PB15 | AT91C_PIO_PB16 | AT91C_PIO_PB17 |
|
|
AT91C_PIO_PB18 | AT91C_PIO_PB19, 0);
|
|
}
|
|
WR4HW(AT91RM92_PMC_BASE, PMC_PCER, 1u << AT91RM92_IRQ_EMAC);
|
|
if (!rev_mii) {
|
|
WR4HW(AT91RM92_EMAC_BASE, ETH_CFG,
|
|
RD4HW(AT91RM92_EMAC_BASE, ETH_CFG) | ETH_CFG_RMII);
|
|
}
|
|
|
|
/*
|
|
* Get our ethernet MAC address from the ID eeprom.
|
|
* Configures TWI as a side effect.
|
|
*/
|
|
set_mac_from_idprom();
|
|
|
|
/*
|
|
* Configure SPI
|
|
*/
|
|
assign_spi_pins();
|
|
|
|
/*
|
|
* Configure SSC
|
|
*/
|
|
at91_pio_use_periph_a(
|
|
AT91RM92_PIOB_BASE,
|
|
AT91C_PIO_PB6 | AT91C_PIO_PB7 | AT91C_PIO_PB8 | /* transmit */
|
|
AT91C_PIO_PB9 | AT91C_PIO_PB10 | AT91C_PIO_PB11, /* receive */
|
|
0); /* no pullup */
|
|
|
|
/*
|
|
* We're using TC1's A1 input for PPS measurements that drive the
|
|
* kernel PLL and our NTP refclock. On some old boards we route a 5mhz
|
|
* signal to TC1's A2 input (pin PA21), but we have never used that
|
|
* clock (it rolls over too fast for hz=100), and now newer boards are
|
|
* using pin PA21 as a CTS0 for USART1, so we no longer assign it to
|
|
* the timer block like we used to here.
|
|
*/
|
|
at91_pio_use_periph_b(AT91RM92_PIOA_BASE, AT91C_PIO_PA19, 0);
|
|
|
|
/*
|
|
* Configure pins used to bitbang-upload the firmware to the main FPGA.
|
|
*/
|
|
at91_pio_use_gpio(AT91RM92_PIOB_BASE,
|
|
AT91C_PIO_PB16 | AT91C_PIO_PB17 | AT91C_PIO_PB18 | AT91C_PIO_PB19);
|
|
|
|
return (at91_ramsize());
|
|
}
|
|
|
|
/*
|
|
* Override the default boot param parser (supplied via weak linkage) with one
|
|
* that knows how to handle our custom tsc_bootinfo passed in from boot2.
|
|
*/
|
|
vm_offset_t
|
|
parse_boot_param(struct arm_boot_params *abp)
|
|
{
|
|
|
|
boot_params = *abp;
|
|
|
|
/*
|
|
* If the right magic is in r0 and a non-NULL pointer is in r1, then
|
|
* it's our bootinfo, copy it. The pointer in r1 is a physical address
|
|
* passed from boot2. This routine is called immediately upon entry to
|
|
* initarm() and is in very nearly the same environment as boot2. In
|
|
* particular, va=pa and we can safely copy the args before we lose easy
|
|
* access to the memory they're stashed in right now.
|
|
*
|
|
* Note that all versions of boot2 that we've ever shipped have put
|
|
* zeroes into r2 and r3. Maybe that'll be useful some day.
|
|
*/
|
|
if (abp->abp_r0 == TSC_BOOTINFO_MAGIC && abp->abp_r1 != 0) {
|
|
inkernel_bootinfo = *(struct tsc_bootinfo *)(abp->abp_r1);
|
|
}
|
|
|
|
return fake_preload_metadata(abp, NULL, 0);
|
|
}
|
|
|
|
ARM_BOARD(NONE, "TSC4370 Controller Board");
|
|
|