ce110ea12f
MANA is the new network adapter from Microsoft which will be available in Azure public cloud. It provides SRIOV NIC as virtual function to guest OS running on Hyper-V. The code can be divided into two major parts. Gdma_main.c is the one to bring up the hardware board and drives all underlying hardware queue infrastructure. Mana_en.c contains all main ethernet driver code. It has only tested and supported on amd64 architecture. PR: 256336 Reviewed by: decui@microsoft.com Tested by: whu MFC after: 2 week Relnotes: yes Sponsored by: Microsoft Differential Revision: https://reviews.freebsd.org/D31150
338 lines
10 KiB
C
338 lines
10 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2021 Microsoft Corp.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/types.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include "mana.h"
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#include "shm_channel.h"
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#include "gdma_util.h"
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#define PAGE_FRAME_L48_WIDTH_BYTES 6
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#define PAGE_FRAME_L48_WIDTH_BITS (PAGE_FRAME_L48_WIDTH_BYTES * 8)
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#define PAGE_FRAME_L48_MASK 0x0000FFFFFFFFFFFF
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#define PAGE_FRAME_H4_WIDTH_BITS 4
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#define VECTOR_MASK 0xFFFF
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#define SHMEM_VF_RESET_STATE ((uint32_t)-1)
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#define SMC_MSG_TYPE_ESTABLISH_HWC 1
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#define SMC_MSG_TYPE_ESTABLISH_HWC_VERSION 0
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#define SMC_MSG_TYPE_DESTROY_HWC 2
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#define SMC_MSG_TYPE_DESTROY_HWC_VERSION 0
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#define SMC_MSG_DIRECTION_REQUEST 0
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#define SMC_MSG_DIRECTION_RESPONSE 1
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/* Structures labeled with "HW DATA" are exchanged with the hardware. All of
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* them are naturally aligned and hence don't need __packed.
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*/
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/* Shared memory channel protocol header
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*
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* msg_type: set on request and response; response matches request.
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* msg_version: newer PF writes back older response (matching request)
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* older PF acts on latest version known and sets that version in result
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* (less than request).
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* direction: 0 for request, VF->PF; 1 for response, PF->VF.
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* status: 0 on request,
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* operation result on response (success = 0, failure = 1 or greater).
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* reset_vf: If set on either establish or destroy request, indicates perform
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* FLR before/after the operation.
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* owner_is_pf: 1 indicates PF owned, 0 indicates VF owned.
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*/
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union smc_proto_hdr {
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uint32_t as_uint32;
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struct {
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uint8_t msg_type : 3;
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uint8_t msg_version : 3;
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uint8_t reserved_1 : 1;
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uint8_t direction : 1;
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uint8_t status;
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uint8_t reserved_2;
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uint8_t reset_vf : 1;
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uint8_t reserved_3 : 6;
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uint8_t owner_is_pf : 1;
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};
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}; /* HW DATA */
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#define SMC_APERTURE_BITS 256
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#define SMC_BASIC_UNIT (sizeof(uint32_t))
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#define SMC_APERTURE_DWORDS (SMC_APERTURE_BITS / (SMC_BASIC_UNIT * 8))
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#define SMC_LAST_DWORD (SMC_APERTURE_DWORDS - 1)
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static int
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mana_smc_poll_register(void __iomem *base, bool reset)
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{
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void __iomem *ptr = (uint8_t *)base + SMC_LAST_DWORD * SMC_BASIC_UNIT;
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volatile uint32_t last_dword;
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int i;
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/* Poll the hardware for the ownership bit. This should be pretty fast,
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* but let's do it in a loop just in case the hardware or the PF
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* driver are temporarily busy.
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*/
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for (i = 0; i < 20 * 1000; i++) {
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last_dword = readl(ptr);
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/* shmem reads as 0xFFFFFFFF in the reset case */
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if (reset && last_dword == SHMEM_VF_RESET_STATE)
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return 0;
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/* If bit_31 is set, the PF currently owns the SMC. */
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if (!(last_dword & BIT(31)))
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return 0;
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DELAY(1000);
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}
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return ETIMEDOUT;
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}
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static int
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mana_smc_read_response(struct shm_channel *sc, uint32_t msg_type,
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uint32_t msg_version, bool reset_vf)
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{
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void __iomem *base = sc->base;
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union smc_proto_hdr hdr;
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int err;
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/* Wait for PF to respond. */
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err = mana_smc_poll_register(base, reset_vf);
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if (err)
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return err;
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hdr.as_uint32 =
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readl((uint8_t *)base + SMC_LAST_DWORD * SMC_BASIC_UNIT);
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mana_dbg(NULL, "shm response 0x%x\n", hdr.as_uint32);
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if (reset_vf && hdr.as_uint32 == SHMEM_VF_RESET_STATE)
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return 0;
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/* Validate protocol fields from the PF driver */
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if (hdr.msg_type != msg_type || hdr.msg_version > msg_version ||
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hdr.direction != SMC_MSG_DIRECTION_RESPONSE) {
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device_printf(sc->dev,
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"Wrong SMC response 0x%x, type=%d, ver=%d\n",
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hdr.as_uint32, msg_type, msg_version);
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return EPROTO;
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}
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/* Validate the operation result */
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if (hdr.status != 0) {
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device_printf(sc->dev,
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"SMC operation failed: 0x%x\n", hdr.status);
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return EPROTO;
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}
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return 0;
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}
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void
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mana_smc_init(struct shm_channel *sc, device_t dev, void __iomem *base)
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{
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sc->dev = dev;
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sc->base = base;
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}
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int
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mana_smc_setup_hwc(struct shm_channel *sc, bool reset_vf, uint64_t eq_addr,
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uint64_t cq_addr, uint64_t rq_addr, uint64_t sq_addr,
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uint32_t eq_msix_index)
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{
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union smc_proto_hdr *hdr;
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uint16_t all_addr_h4bits = 0;
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uint16_t frame_addr_seq = 0;
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uint64_t frame_addr = 0;
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uint8_t shm_buf[32];
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uint64_t *shmem;
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uint32_t *dword;
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uint8_t *ptr;
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int err;
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int i;
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/* Ensure VF already has possession of shared memory */
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err = mana_smc_poll_register(sc->base, false);
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if (err) {
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device_printf(sc->dev,
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"Timeout when setting up HWC: %d\n", err);
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return err;
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}
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if (!IS_ALIGNED(eq_addr, PAGE_SIZE) ||
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!IS_ALIGNED(cq_addr, PAGE_SIZE) ||
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!IS_ALIGNED(rq_addr, PAGE_SIZE) ||
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!IS_ALIGNED(sq_addr, PAGE_SIZE))
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return EINVAL;
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if ((eq_msix_index & VECTOR_MASK) != eq_msix_index)
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return EINVAL;
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/* Scheme for packing four addresses and extra info into 256 bits.
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*
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* Addresses must be page frame aligned, so only frame address bits
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* are transferred.
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*
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* 52-bit frame addresses are split into the lower 48 bits and upper
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* 4 bits. Lower 48 bits of 4 address are written sequentially from
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* the start of the 256-bit shared memory region followed by 16 bits
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* containing the upper 4 bits of the 4 addresses in sequence.
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*
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* A 16 bit EQ vector number fills out the next-to-last 32-bit dword.
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*
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* The final 32-bit dword is used for protocol control information as
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* defined in smc_proto_hdr.
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*/
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memset(shm_buf, 0, sizeof(shm_buf));
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ptr = shm_buf;
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/* EQ addr: low 48 bits of frame address */
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shmem = (uint64_t *)ptr;
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frame_addr = PHYS_PFN(eq_addr);
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*shmem = frame_addr & PAGE_FRAME_L48_MASK;
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all_addr_h4bits |= (frame_addr >> PAGE_FRAME_L48_WIDTH_BITS) <<
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(frame_addr_seq++ * PAGE_FRAME_H4_WIDTH_BITS);
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ptr += PAGE_FRAME_L48_WIDTH_BYTES;
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/* CQ addr: low 48 bits of frame address */
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shmem = (uint64_t *)ptr;
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frame_addr = PHYS_PFN(cq_addr);
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*shmem = frame_addr & PAGE_FRAME_L48_MASK;
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all_addr_h4bits |= (frame_addr >> PAGE_FRAME_L48_WIDTH_BITS) <<
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(frame_addr_seq++ * PAGE_FRAME_H4_WIDTH_BITS);
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ptr += PAGE_FRAME_L48_WIDTH_BYTES;
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/* RQ addr: low 48 bits of frame address */
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shmem = (uint64_t *)ptr;
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frame_addr = PHYS_PFN(rq_addr);
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*shmem = frame_addr & PAGE_FRAME_L48_MASK;
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all_addr_h4bits |= (frame_addr >> PAGE_FRAME_L48_WIDTH_BITS) <<
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(frame_addr_seq++ * PAGE_FRAME_H4_WIDTH_BITS);
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ptr += PAGE_FRAME_L48_WIDTH_BYTES;
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/* SQ addr: low 48 bits of frame address */
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shmem = (uint64_t *)ptr;
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frame_addr = PHYS_PFN(sq_addr);
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*shmem = frame_addr & PAGE_FRAME_L48_MASK;
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all_addr_h4bits |= (frame_addr >> PAGE_FRAME_L48_WIDTH_BITS) <<
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(frame_addr_seq++ * PAGE_FRAME_H4_WIDTH_BITS);
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ptr += PAGE_FRAME_L48_WIDTH_BYTES;
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/* High 4 bits of the four frame addresses */
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*((uint16_t *)ptr) = all_addr_h4bits;
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ptr += sizeof(uint16_t);
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/* EQ MSIX vector number */
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*((uint16_t *)ptr) = (uint16_t)eq_msix_index;
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ptr += sizeof(uint16_t);
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/* 32-bit protocol header in final dword */
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*((uint32_t *)ptr) = 0;
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hdr = (union smc_proto_hdr *)ptr;
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hdr->msg_type = SMC_MSG_TYPE_ESTABLISH_HWC;
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hdr->msg_version = SMC_MSG_TYPE_ESTABLISH_HWC_VERSION;
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hdr->direction = SMC_MSG_DIRECTION_REQUEST;
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hdr->reset_vf = reset_vf;
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/* Write 256-message buffer to shared memory (final 32-bit write
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* triggers HW to set possession bit to PF).
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*/
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dword = (uint32_t *)shm_buf;
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for (i = 0; i < SMC_APERTURE_DWORDS; i++) {
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mana_dbg(NULL, "write shm_buf %d, val: 0x%x\n",
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i, *dword);
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writel((char *)sc->base + i * SMC_BASIC_UNIT, *dword++);
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}
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/* Read shmem response (polling for VF possession) and validate.
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* For setup, waiting for response on shared memory is not strictly
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* necessary, since wait occurs later for results to appear in EQE's.
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*/
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err = mana_smc_read_response(sc, SMC_MSG_TYPE_ESTABLISH_HWC,
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SMC_MSG_TYPE_ESTABLISH_HWC_VERSION, reset_vf);
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if (err) {
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device_printf(sc->dev,
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"Error when setting up HWC: %d\n", err);
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return err;
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}
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return 0;
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}
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int
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mana_smc_teardown_hwc(struct shm_channel *sc, bool reset_vf)
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{
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union smc_proto_hdr hdr = {};
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int err;
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/* Ensure already has possession of shared memory */
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err = mana_smc_poll_register(sc->base, false);
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if (err) {
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device_printf(sc->dev, "Timeout when tearing down HWC\n");
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return err;
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}
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/* Set up protocol header for HWC destroy message */
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hdr.msg_type = SMC_MSG_TYPE_DESTROY_HWC;
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hdr.msg_version = SMC_MSG_TYPE_DESTROY_HWC_VERSION;
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hdr.direction = SMC_MSG_DIRECTION_REQUEST;
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hdr.reset_vf = reset_vf;
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/* Write message in high 32 bits of 256-bit shared memory, causing HW
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* to set possession bit to PF.
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*/
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writel((char *)sc->base + SMC_LAST_DWORD * SMC_BASIC_UNIT,
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hdr.as_uint32);
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/* Read shmem response (polling for VF possession) and validate.
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* For teardown, waiting for response is required to ensure hardware
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* invalidates MST entries before software frees memory.
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*/
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err = mana_smc_read_response(sc, SMC_MSG_TYPE_DESTROY_HWC,
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SMC_MSG_TYPE_DESTROY_HWC_VERSION, reset_vf);
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if (err) {
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device_printf(sc->dev,
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"Error when tearing down HWC: %d\n", err);
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return err;
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}
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return 0;
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}
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