295 lines
9.2 KiB
C
295 lines
9.2 KiB
C
/*-
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* Copyright (c) 2017 Kevin Lo <kevlo@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_wlan.h"
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#include <sys/param.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/mbuf.h>
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#include <sys/kernel.h>
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#include <sys/socket.h>
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#include <sys/systm.h>
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#include <sys/malloc.h>
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#include <sys/queue.h>
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#include <sys/taskqueue.h>
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#include <sys/bus.h>
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#include <sys/endian.h>
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#include <sys/linker.h>
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#include <net/if.h>
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#include <net/ethernet.h>
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#include <net/if_media.h>
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#include <net80211/ieee80211_var.h>
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#include <net80211/ieee80211_radiotap.h>
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#include <dev/rtwn/if_rtwnreg.h>
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#include <dev/rtwn/if_rtwnvar.h>
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#include <dev/rtwn/if_rtwn_debug.h>
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#include <dev/rtwn/if_rtwn_ridx.h>
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#include <dev/rtwn/if_rtwn_rx.h>
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#include <dev/rtwn/rtl8192e/r92e.h>
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#include <dev/rtwn/rtl8192e/r92e_reg.h>
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#include <dev/rtwn/rtl8192e/r92e_var.h>
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static int
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r92e_get_power_group(struct rtwn_softc *sc, struct ieee80211_channel *c)
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{
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uint8_t chan;
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int group;
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chan = rtwn_chan2centieee(c);
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if (IEEE80211_IS_CHAN_2GHZ(c)) {
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if (chan <= 2) group = 0;
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else if (chan <= 5) group = 1;
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else if (chan <= 8) group = 2;
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else if (chan <= 11) group = 3;
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else if (chan <= 14) group = 4;
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else {
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KASSERT(0, ("wrong 2GHz channel %d!\n", chan));
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return (-1);
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}
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} else {
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KASSERT(0, ("wrong channel band (flags %08X)\n", c->ic_flags));
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return (-1);
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}
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return (group);
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}
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static void
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r92e_get_txpower(struct rtwn_softc *sc, int chain, struct ieee80211_channel *c,
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uint8_t power[RTWN_RIDX_COUNT])
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{
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struct r92e_softc *rs = sc->sc_priv;
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int i, ridx, group, max_mcs;
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/* Determine channel group. */
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group = r92e_get_power_group(sc, c);
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if (group == -1) { /* shouldn't happen */
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device_printf(sc->sc_dev, "%s: incorrect channel\n", __func__);
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return;
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}
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max_mcs = RTWN_RIDX_MCS(sc->ntxchains * 8 - 1);
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/* XXX regulatory */
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/* XXX net80211 regulatory */
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for (ridx = RTWN_RIDX_CCK1; ridx <= RTWN_RIDX_CCK11; ridx++)
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power[ridx] = rs->cck_tx_pwr[chain][group];
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for (ridx = RTWN_RIDX_OFDM6; ridx <= max_mcs; ridx++)
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power[ridx] = rs->ht40_tx_pwr_2g[chain][group];
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for (ridx = RTWN_RIDX_OFDM6; ridx <= RTWN_RIDX_OFDM54; ridx++)
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power[ridx] += rs->ofdm_tx_pwr_diff_2g[chain][0];
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for (i = 0; i < sc->ntxchains; i++) {
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uint8_t min_mcs;
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uint8_t pwr_diff;
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if (IEEE80211_IS_CHAN_HT40(c))
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pwr_diff = rs->bw40_tx_pwr_diff_2g[chain][i];
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else
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pwr_diff = rs->bw20_tx_pwr_diff_2g[chain][i];
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min_mcs = RTWN_RIDX_MCS(i * 8);
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for (ridx = min_mcs; ridx <= max_mcs; ridx++)
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power[ridx] += pwr_diff;
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}
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/* Apply max limit. */
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for (ridx = RTWN_RIDX_CCK1; ridx <= max_mcs; ridx++) {
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if (power[ridx] > R92C_MAX_TX_PWR)
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power[ridx] = R92C_MAX_TX_PWR;
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}
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#ifdef RTWN_DEBUG
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if (sc->sc_debug & RTWN_DEBUG_TXPWR) {
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/* Dump per-rate Tx power values. */
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printf("Tx power for chain %d:\n", chain);
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for (ridx = RTWN_RIDX_CCK1; ridx < RTWN_RIDX_COUNT; ridx++)
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printf("Rate %d = %u\n", ridx, power[ridx]);
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}
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#endif
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}
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static void
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r92e_write_txpower(struct rtwn_softc *sc, int chain,
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uint8_t power[RTWN_RIDX_COUNT])
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{
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uint32_t reg;
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/* Write per-CCK rate Tx power. */
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if (chain == 0) {
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reg = rtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32);
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reg = RW(reg, R92C_TXAGC_A_CCK1, power[RTWN_RIDX_CCK1]);
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rtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg);
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reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);
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reg = RW(reg, R92C_TXAGC_A_CCK2, power[RTWN_RIDX_CCK2]);
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reg = RW(reg, R92C_TXAGC_A_CCK55, power[RTWN_RIDX_CCK55]);
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reg = RW(reg, R92C_TXAGC_A_CCK11, power[RTWN_RIDX_CCK11]);
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rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg);
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} else {
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reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32);
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reg = RW(reg, R92C_TXAGC_B_CCK1, power[RTWN_RIDX_CCK1]);
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reg = RW(reg, R92C_TXAGC_B_CCK2, power[RTWN_RIDX_CCK2]);
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reg = RW(reg, R92C_TXAGC_B_CCK55, power[RTWN_RIDX_CCK55]);
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rtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg);
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reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);
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reg = RW(reg, R92C_TXAGC_B_CCK11, power[RTWN_RIDX_CCK11]);
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rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg);
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}
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/* Write per-OFDM rate Tx power. */
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rtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain),
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SM(R92C_TXAGC_RATE06, power[RTWN_RIDX_OFDM6]) |
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SM(R92C_TXAGC_RATE09, power[RTWN_RIDX_OFDM9]) |
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SM(R92C_TXAGC_RATE12, power[RTWN_RIDX_OFDM12]) |
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SM(R92C_TXAGC_RATE18, power[RTWN_RIDX_OFDM18]));
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rtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain),
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SM(R92C_TXAGC_RATE24, power[RTWN_RIDX_OFDM24]) |
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SM(R92C_TXAGC_RATE36, power[RTWN_RIDX_OFDM36]) |
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SM(R92C_TXAGC_RATE48, power[RTWN_RIDX_OFDM48]) |
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SM(R92C_TXAGC_RATE54, power[RTWN_RIDX_OFDM54]));
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/* Write per-MCS Tx power. */
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rtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain),
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SM(R92C_TXAGC_MCS00, power[RTWN_RIDX_MCS(0)]) |
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SM(R92C_TXAGC_MCS01, power[RTWN_RIDX_MCS(1)]) |
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SM(R92C_TXAGC_MCS02, power[RTWN_RIDX_MCS(2)]) |
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SM(R92C_TXAGC_MCS03, power[RTWN_RIDX_MCS(3)]));
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rtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain),
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SM(R92C_TXAGC_MCS04, power[RTWN_RIDX_MCS(4)]) |
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SM(R92C_TXAGC_MCS05, power[RTWN_RIDX_MCS(5)]) |
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SM(R92C_TXAGC_MCS06, power[RTWN_RIDX_MCS(6)]) |
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SM(R92C_TXAGC_MCS07, power[RTWN_RIDX_MCS(7)]));
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if (sc->ntxchains >= 2) {
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rtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain),
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SM(R92C_TXAGC_MCS08, power[RTWN_RIDX_MCS(8)]) |
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SM(R92C_TXAGC_MCS09, power[RTWN_RIDX_MCS(9)]) |
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SM(R92C_TXAGC_MCS10, power[RTWN_RIDX_MCS(10)]) |
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SM(R92C_TXAGC_MCS11, power[RTWN_RIDX_MCS(11)]));
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rtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain),
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SM(R92C_TXAGC_MCS12, power[RTWN_RIDX_MCS(12)]) |
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SM(R92C_TXAGC_MCS13, power[RTWN_RIDX_MCS(13)]) |
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SM(R92C_TXAGC_MCS14, power[RTWN_RIDX_MCS(14)]) |
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SM(R92C_TXAGC_MCS15, power[RTWN_RIDX_MCS(15)]));
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}
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}
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static void
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r92e_set_txpower(struct rtwn_softc *sc, struct ieee80211_channel *c)
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{
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uint8_t power[RTWN_RIDX_COUNT];
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int i;
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for (i = 0; i < sc->ntxchains; i++) {
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memset(power, 0, sizeof(power));
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/* Compute per-rate Tx power values. */
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r92e_get_txpower(sc, i, c, power);
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/* Write per-rate Tx power values to hardware. */
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r92e_write_txpower(sc, i, power);
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}
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}
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static void
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r92e_set_bw40(struct rtwn_softc *sc, uint8_t chan, int prichlo)
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{
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int i;
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rtwn_setbits_2(sc, R92C_WMAC_TRXPTCL_CTL, 0x100, 0x80);
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rtwn_write_1(sc, R12A_DATA_SEC,
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prichlo ? R12A_DATA_SEC_PRIM_DOWN_20 : R12A_DATA_SEC_PRIM_UP_20);
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rtwn_bb_setbits(sc, R92C_FPGA0_RFMOD, 0, R92C_RFMOD_40MHZ);
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rtwn_bb_setbits(sc, R92C_FPGA1_RFMOD, 0, R92C_RFMOD_40MHZ);
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/* Select 40MHz bandwidth. */
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for (i = 0; i < sc->nrxchains; i++)
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rtwn_rf_setbits(sc, i, R92C_RF_CHNLBW,
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R88E_RF_CHNLBW_BW20, 0x400);
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/* Set CCK side band. */
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rtwn_bb_setbits(sc, R92C_CCK0_SYSTEM,
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R92C_CCK0_SYSTEM_CCK_SIDEBAND, (prichlo ? 0 : 1) << 4);
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rtwn_bb_setbits(sc, R92C_OFDM1_LSTF, 0x0c00, (prichlo ? 1 : 2) << 10);
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rtwn_bb_setbits(sc, R92C_FPGA0_ANAPARAM2,
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R92C_FPGA0_ANAPARAM2_CBW20, 0);
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rtwn_bb_setbits(sc, 0x818, 0x0c000000, (prichlo ? 2 : 1) << 26);
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}
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static void
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r92e_set_bw20(struct rtwn_softc *sc, uint8_t chan)
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{
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int i;
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rtwn_setbits_2(sc, R92C_WMAC_TRXPTCL_CTL, 0x180, 0);
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rtwn_write_1(sc, R12A_DATA_SEC, R12A_DATA_SEC_NO_EXT);
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rtwn_bb_setbits(sc, R92C_FPGA0_RFMOD, R92C_RFMOD_40MHZ, 0);
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rtwn_bb_setbits(sc, R92C_FPGA1_RFMOD, R92C_RFMOD_40MHZ, 0);
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/* Select 20MHz bandwidth. */
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for (i = 0; i < sc->nrxchains; i++)
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rtwn_rf_setbits(sc, i, R92C_RF_CHNLBW,
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R88E_RF_CHNLBW_BW20, 0xc00);
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rtwn_bb_setbits(sc, R92C_OFDM0_TXPSEUDONOISEWGT, 0xc0000000, 0);
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}
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void
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r92e_set_chan(struct rtwn_softc *sc, struct ieee80211_channel *c)
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{
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struct r92e_softc *rs = sc->sc_priv;
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u_int chan;
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int i;
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chan = rtwn_chan2centieee(c);
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for (i = 0; i < sc->nrxchains; i++) {
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rtwn_rf_write(sc, i, R92C_RF_CHNLBW,
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RW(rs->rf_chnlbw[0], R92C_RF_CHNLBW_CHNL, chan));
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}
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if (IEEE80211_IS_CHAN_HT40(c))
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r92e_set_bw40(sc, chan, IEEE80211_IS_CHAN_HT40U(c));
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else
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r92e_set_bw20(sc, chan);
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/* Set Tx power for this new channel. */
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r92e_set_txpower(sc, c);
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}
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