ef2ee5d07a
The following pheripherals are supported: UART, MMC, AHCI, EHCI, PCIe, I2C, PMIC, GPIO, CPU temperature and clock. Note: The PCIe driver is pure mash at this moment. It will be reworked immediately when both D5237 and D2579 enter the current tree.
567 lines
14 KiB
C
567 lines
14 KiB
C
/*-
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* Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <sys/rman.h>
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#include <machine/bus.h>
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#include <dev/extres/clk/clk.h>
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#include <dev/extres/hwreset/hwreset.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <arm/nvidia/tegra_pmc.h>
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#define PMC_CNTRL 0x000
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#define PMC_CNTRL_CPUPWRGOOD_SEL_MASK (0x3 << 20)
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#define PMC_CNTRL_CPUPWRGOOD_SEL_SHIFT 20
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#define PMC_CNTRL_CPUPWRGOOD_EN (1 << 19)
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#define PMC_CNTRL_FUSE_OVERRIDE (1 << 18)
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#define PMC_CNTRL_INTR_POLARITY (1 << 17)
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#define PMC_CNTRL_CPU_PWRREQ_OE (1 << 16)
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#define PMC_CNTRL_CPU_PWRREQ_POLARITY (1 << 15)
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#define PMC_CNTRL_SIDE_EFFECT_LP0 (1 << 14)
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#define PMC_CNTRL_AOINIT (1 << 13)
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#define PMC_CNTRL_PWRGATE_DIS (1 << 12)
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#define PMC_CNTRL_SYSCLK_OE (1 << 11)
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#define PMC_CNTRL_SYSCLK_POLARITY (1 << 10)
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#define PMC_CNTRL_PWRREQ_OE (1 << 9)
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#define PMC_CNTRL_PWRREQ_POLARITY (1 << 8)
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#define PMC_CNTRL_BLINK_EN (1 << 7)
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#define PMC_CNTRL_GLITCHDET_DIS (1 << 6)
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#define PMC_CNTRL_LATCHWAKE_EN (1 << 5)
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#define PMC_CNTRL_MAIN_RST (1 << 4)
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#define PMC_CNTRL_KBC_RST (1 << 3)
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#define PMC_CNTRL_RTC_RST (1 << 2)
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#define PMC_CNTRL_RTC_CLK_DIS (1 << 1)
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#define PMC_CNTRL_KBC_CLK_DIS (1 << 0)
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#define PMC_DPD_SAMPLE 0x020
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#define PMC_CLAMP_STATUS 0x02C
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#define PMC_CLAMP_STATUS_PARTID(x) (1 << ((x) & 0x1F))
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#define PMC_PWRGATE_TOGGLE 0x030
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#define PMC_PWRGATE_TOGGLE_START (1 << 8)
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#define PMC_PWRGATE_TOGGLE_PARTID(x) (((x) & 0x1F) << 0)
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#define PMC_REMOVE_CLAMPING_CMD 0x034
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#define PMC_REMOVE_CLAMPING_CMD_PARTID(x) (1 << ((x) & 0x1F))
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#define PMC_PWRGATE_STATUS 0x038
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#define PMC_PWRGATE_STATUS_PARTID(x) (1 << ((x) & 0x1F))
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#define PMC_SCRATCH0 0x050
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#define PMC_SCRATCH0_MODE_RECOVERY (1 << 31)
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#define PMC_SCRATCH0_MODE_BOOTLOADER (1 << 30)
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#define PMC_SCRATCH0_MODE_RCM (1 << 1)
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#define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \
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PMC_SCRATCH0_MODE_BOOTLOADER | \
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PMC_SCRATCH0_MODE_RCM)
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#define PMC_CPUPWRGOOD_TIMER 0x0c8
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#define PMC_CPUPWROFF_TIMER 0x0cc
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#define PMC_SCRATCH41 0x140
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#define PMC_SENSOR_CTRL 0x1b0
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#define PMC_SENSOR_CTRL_BLOCK_SCRATCH_WRITE (1 << 2)
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#define PMC_SENSOR_CTRL_ENABLE_RST (1 << 1)
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#define PMC_SENSOR_CTRL_ENABLE_PG (1 << 0)
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#define PMC_IO_DPD_REQ 0x1b8
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#define PMC_IO_DPD_REQ_CODE_IDLE (0 << 30)
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#define PMC_IO_DPD_REQ_CODE_OFF (1 << 30)
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#define PMC_IO_DPD_REQ_CODE_ON (2 << 30)
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#define PMC_IO_DPD_REQ_CODE_MASK (3 << 30)
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#define PMC_IO_DPD_STATUS 0x1bc
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#define PMC_IO_DPD_STATUS_HDMI (1 << 28)
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#define PMC_IO_DPD2_REQ 0x1c0
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#define PMC_IO_DPD2_STATUS 0x1c4
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#define PMC_IO_DPD2_STATUS_HV (1 << 6)
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#define PMC_SEL_DPD_TIM 0x1c8
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#define PMC_SCRATCH54 0x258
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#define PMC_SCRATCH54_DATA_SHIFT 8
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#define PMC_SCRATCH54_ADDR_SHIFT 0
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#define PMC_SCRATCH55 0x25c
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#define PMC_SCRATCH55_RST_ENABLE (1 << 31)
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#define PMC_SCRATCH55_CNTRL_TYPE (1 << 30)
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#define PMC_SCRATCH55_CNTRL_ID_SHIFT 27
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#define PMC_SCRATCH55_CNTRL_ID_MASK 0x07
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#define PMC_SCRATCH55_PINMUX_SHIFT 24
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#define PMC_SCRATCH55_PINMUX_MASK 0x07
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#define PMC_SCRATCH55_CHECKSUM_SHIFT 16
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#define PMC_SCRATCH55_CHECKSUM_MASK 0xFF
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#define PMC_SCRATCH55_16BITOP (1 << 15)
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#define PMC_SCRATCH55_I2CSLV1_SHIFT 0
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#define PMC_SCRATCH55_I2CSLV1_MASK 0x7F
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#define PMC_GPU_RG_CNTRL 0x2d4
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#define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v))
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#define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r))
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#define PMC_LOCK(_sc) mtx_lock(&(_sc)->mtx)
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#define PMC_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx)
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#define PMC_LOCK_INIT(_sc) mtx_init(&(_sc)->mtx, \
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device_get_nameunit(_sc->dev), "tegra124_pmc", MTX_DEF)
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#define PMC_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx);
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#define PMC_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED);
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#define PMC_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->mtx, MA_NOTOWNED);
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struct tegra124_pmc_softc {
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device_t dev;
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struct resource *mem_res;
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clk_t clk;
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struct mtx mtx;
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uint32_t rate;
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enum tegra_suspend_mode suspend_mode;
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uint32_t cpu_good_time;
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uint32_t cpu_off_time;
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uint32_t core_osc_time;
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uint32_t core_pmu_time;
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uint32_t core_off_time;
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int corereq_high;
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int sysclkreq_high;
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int combined_req;
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int cpu_pwr_good_en;
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uint32_t lp0_vec_phys;
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uint32_t lp0_vec_size;
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};
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static struct ofw_compat_data compat_data[] = {
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{"nvidia,tegra124-pmc", 1},
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{NULL, 0},
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};
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static struct tegra124_pmc_softc *pmc_sc;
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static inline struct tegra124_pmc_softc *
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tegra124_pmc_get_sc(void)
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{
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if (pmc_sc == NULL)
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panic("To early call to Tegra PMC driver.\n");
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return (pmc_sc);
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}
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static int
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tegra124_pmc_set_powergate(struct tegra124_pmc_softc *sc,
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enum tegra_powergate_id id, int ena)
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{
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uint32_t reg;
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int i;
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PMC_LOCK(sc);
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reg = RD4(sc, PMC_PWRGATE_STATUS) & PMC_PWRGATE_STATUS_PARTID(id);
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if (((reg != 0) && ena) || ((reg == 0) && !ena)) {
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PMC_UNLOCK(sc);
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return (0);
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}
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for (i = 100; i > 0; i--) {
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reg = RD4(sc, PMC_PWRGATE_TOGGLE);
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if ((reg & PMC_PWRGATE_TOGGLE_START) == 0)
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break;
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DELAY(1);
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}
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if (i <= 0)
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device_printf(sc->dev,
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"Timeout when waiting for TOGGLE_START\n");
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WR4(sc, PMC_PWRGATE_TOGGLE,
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PMC_PWRGATE_TOGGLE_START | PMC_PWRGATE_TOGGLE_PARTID(id));
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for (i = 100; i > 0; i--) {
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reg = RD4(sc, PMC_PWRGATE_TOGGLE);
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if ((reg & PMC_PWRGATE_TOGGLE_START) == 0)
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break;
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DELAY(1);
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}
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if (i <= 0)
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device_printf(sc->dev,
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"Timeout when waiting for TOGGLE_START\n");
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PMC_UNLOCK(sc);
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return (0);
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}
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int
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tegra_powergate_remove_clamping(enum tegra_powergate_id id)
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{
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struct tegra124_pmc_softc *sc;
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uint32_t reg;
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enum tegra_powergate_id swid;
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int i;
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sc = tegra124_pmc_get_sc();
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if (id == TEGRA_POWERGATE_3D) {
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WR4(sc, PMC_GPU_RG_CNTRL, 0);
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return (0);
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}
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reg = RD4(sc, PMC_PWRGATE_STATUS);
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if ((reg & PMC_PWRGATE_STATUS_PARTID(id)) == 0)
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panic("Attempt to remove clamping for unpowered partition.\n");
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if (id == TEGRA_POWERGATE_PCX)
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swid = TEGRA_POWERGATE_VDE;
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else if (id == TEGRA_POWERGATE_VDE)
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swid = TEGRA_POWERGATE_PCX;
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else
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swid = id;
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WR4(sc, PMC_REMOVE_CLAMPING_CMD, PMC_REMOVE_CLAMPING_CMD_PARTID(swid));
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for (i = 100; i > 0; i--) {
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reg = RD4(sc, PMC_REMOVE_CLAMPING_CMD);
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if ((reg & PMC_REMOVE_CLAMPING_CMD_PARTID(swid)) == 0)
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break;
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DELAY(1);
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}
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if (i <= 0)
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device_printf(sc->dev, "Timeout when remove clamping\n");
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reg = RD4(sc, PMC_CLAMP_STATUS);
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if ((reg & PMC_CLAMP_STATUS_PARTID(id)) != 0)
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panic("Cannot remove clamping\n");
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return (0);
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}
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int
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tegra_powergate_is_powered(enum tegra_powergate_id id)
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{
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struct tegra124_pmc_softc *sc;
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uint32_t reg;
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sc = tegra124_pmc_get_sc();
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reg = RD4(sc, PMC_PWRGATE_STATUS);
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return ((reg & PMC_PWRGATE_STATUS_PARTID(id)) ? 1 : 0);
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}
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int
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tegra_powergate_power_on(enum tegra_powergate_id id)
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{
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struct tegra124_pmc_softc *sc;
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int rv, i;
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sc = tegra124_pmc_get_sc();
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rv = tegra124_pmc_set_powergate(sc, id, 1);
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if (rv != 0) {
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device_printf(sc->dev, "Cannot set powergate: %d\n", id);
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return (rv);
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}
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for (i = 100; i > 0; i--) {
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if (tegra_powergate_is_powered(id))
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break;
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DELAY(1);
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}
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if (i <= 0)
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device_printf(sc->dev, "Timeout when waiting on power up\n");
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return (rv);
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}
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int
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tegra_powergate_power_off(enum tegra_powergate_id id)
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{
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struct tegra124_pmc_softc *sc;
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int rv, i;
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sc = tegra124_pmc_get_sc();
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rv = tegra124_pmc_set_powergate(sc, id, 0);
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if (rv != 0) {
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device_printf(sc->dev, "Cannot set powergate: %d\n", id);
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return (rv);
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}
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for (i = 100; i > 0; i--) {
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if (!tegra_powergate_is_powered(id))
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break;
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DELAY(1);
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}
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if (i <= 0)
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device_printf(sc->dev, "Timeout when waiting on power off\n");
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return (rv);
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}
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int
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tegra_powergate_sequence_power_up(enum tegra_powergate_id id, clk_t clk,
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hwreset_t rst)
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{
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struct tegra124_pmc_softc *sc;
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int rv;
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sc = tegra124_pmc_get_sc();
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rv = hwreset_assert(rst);
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if (rv != 0) {
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device_printf(sc->dev, "Cannot assert reset\n");
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return (rv);
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}
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rv = clk_stop(clk);
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if (rv != 0) {
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device_printf(sc->dev, "Cannot stop clock\n");
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goto clk_fail;
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}
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rv = tegra_powergate_power_on(id);
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if (rv != 0) {
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device_printf(sc->dev, "Cannot power on powergate\n");
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goto clk_fail;
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}
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rv = clk_enable(clk);
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if (rv != 0) {
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device_printf(sc->dev, "Cannot enable clock\n");
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goto clk_fail;
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}
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DELAY(20);
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rv = tegra_powergate_remove_clamping(id);
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if (rv != 0) {
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device_printf(sc->dev, "Cannot remove clamping\n");
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goto fail;
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}
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rv = hwreset_deassert(rst);
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if (rv != 0) {
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device_printf(sc->dev, "Cannot unreset reset\n");
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goto fail;
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}
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return 0;
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fail:
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clk_disable(clk);
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clk_fail:
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hwreset_assert(rst);
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tegra_powergate_power_off(id);
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return (rv);
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}
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static int
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tegra124_pmc_parse_fdt(struct tegra124_pmc_softc *sc, phandle_t node)
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{
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int rv;
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uint32_t tmp;
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uint32_t tmparr[2];
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rv = OF_getencprop(node, "nvidia,suspend-mode", &tmp, sizeof(tmp));
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if (rv > 0) {
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switch (tmp) {
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case 0:
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sc->suspend_mode = TEGRA_SUSPEND_LP0;
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break;
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case 1:
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sc->suspend_mode = TEGRA_SUSPEND_LP1;
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break;
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case 2:
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sc->suspend_mode = TEGRA_SUSPEND_LP2;
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break;
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default:
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sc->suspend_mode = TEGRA_SUSPEND_NONE;
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break;
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}
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}
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rv = OF_getencprop(node, "nvidia,cpu-pwr-good-time", &tmp, sizeof(tmp));
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if (rv > 0) {
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sc->cpu_good_time = tmp;
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sc->suspend_mode = TEGRA_SUSPEND_NONE;
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}
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rv = OF_getencprop(node, "nvidia,cpu-pwr-off-time", &tmp, sizeof(tmp));
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if (rv > 0) {
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sc->cpu_off_time = tmp;
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sc->suspend_mode = TEGRA_SUSPEND_NONE;
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}
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rv = OF_getencprop(node, "nvidia,core-pwr-good-time", tmparr,
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sizeof(tmparr));
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if (rv == sizeof(tmparr)) {
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sc->core_osc_time = tmparr[0];
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sc->core_pmu_time = tmparr[1];
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sc->suspend_mode = TEGRA_SUSPEND_NONE;
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}
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rv = OF_getencprop(node, "nvidia,core-pwr-off-time", &tmp, sizeof(tmp));
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if (rv > 0) {
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sc->core_off_time = tmp;
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sc->suspend_mode = TEGRA_SUSPEND_NONE;
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}
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sc->corereq_high =
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OF_hasprop(node, "nvidia,core-power-req-active-high");
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sc->sysclkreq_high =
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OF_hasprop(node, "nvidia,sys-clock-req-active-high");
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sc->combined_req =
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OF_hasprop(node, "nvidia,combined-power-req");
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sc->cpu_pwr_good_en =
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OF_hasprop(node, "nvidia,cpu-pwr-good-en");
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rv = OF_getencprop(node, "nvidia,lp0-vec", tmparr, sizeof(tmparr));
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if (rv == sizeof(tmparr)) {
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sc->lp0_vec_phys = tmparr[0];
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sc->core_pmu_time = tmparr[1];
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sc->lp0_vec_size = TEGRA_SUSPEND_NONE;
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if (sc->suspend_mode == TEGRA_SUSPEND_LP0)
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sc->suspend_mode = TEGRA_SUSPEND_LP1;
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}
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return 0;
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}
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|
|
|
static int
|
|
tegra124_pmc_probe(device_t dev)
|
|
{
|
|
|
|
if (!ofw_bus_status_okay(dev))
|
|
return (ENXIO);
|
|
|
|
if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
|
|
return (ENXIO);
|
|
|
|
device_set_desc(dev, "Tegra PMC");
|
|
return (BUS_PROBE_DEFAULT);
|
|
}
|
|
|
|
static int
|
|
tegra124_pmc_detach(device_t dev)
|
|
{
|
|
|
|
/* This device is always present. */
|
|
return (EBUSY);
|
|
}
|
|
|
|
static int
|
|
tegra124_pmc_attach(device_t dev)
|
|
{
|
|
struct tegra124_pmc_softc *sc;
|
|
int rid, rv;
|
|
uint32_t reg;
|
|
phandle_t node;
|
|
|
|
sc = device_get_softc(dev);
|
|
sc->dev = dev;
|
|
node = ofw_bus_get_node(dev);
|
|
|
|
rv = tegra124_pmc_parse_fdt(sc, node);
|
|
if (rv != 0) {
|
|
device_printf(sc->dev, "Cannot parse FDT data\n");
|
|
return (rv);
|
|
}
|
|
|
|
rv = clk_get_by_ofw_name(sc->dev, "pclk", &sc->clk);
|
|
if (rv != 0) {
|
|
device_printf(sc->dev, "Cannot get \"pclk\" clock\n");
|
|
return (ENXIO);
|
|
}
|
|
|
|
rid = 0;
|
|
sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
|
|
RF_ACTIVE);
|
|
if (sc->mem_res == NULL) {
|
|
device_printf(dev, "Cannot allocate memory resources\n");
|
|
return (ENXIO);
|
|
}
|
|
|
|
PMC_LOCK_INIT(sc);
|
|
|
|
/* Enable CPU power request. */
|
|
reg = RD4(sc, PMC_CNTRL);
|
|
reg |= PMC_CNTRL_CPU_PWRREQ_OE;
|
|
WR4(sc, PMC_CNTRL, reg);
|
|
|
|
/* Set sysclk output polarity */
|
|
reg = RD4(sc, PMC_CNTRL);
|
|
if (sc->sysclkreq_high)
|
|
reg &= ~PMC_CNTRL_SYSCLK_POLARITY;
|
|
else
|
|
reg |= PMC_CNTRL_SYSCLK_POLARITY;
|
|
WR4(sc, PMC_CNTRL, reg);
|
|
|
|
/* Enable sysclk request. */
|
|
reg = RD4(sc, PMC_CNTRL);
|
|
reg |= PMC_CNTRL_SYSCLK_OE;
|
|
WR4(sc, PMC_CNTRL, reg);
|
|
|
|
/*
|
|
* Remove HDMI from deep power down mode.
|
|
* XXX mote this to HDMI driver
|
|
*/
|
|
reg = RD4(sc, PMC_IO_DPD_STATUS);
|
|
reg &= ~ PMC_IO_DPD_STATUS_HDMI;
|
|
WR4(sc, PMC_IO_DPD_STATUS, reg);
|
|
|
|
reg = RD4(sc, PMC_IO_DPD2_STATUS);
|
|
reg &= ~ PMC_IO_DPD2_STATUS_HV;
|
|
WR4(sc, PMC_IO_DPD2_STATUS, reg);
|
|
|
|
if (pmc_sc != NULL)
|
|
panic("tegra124_pmc: double driver attach");
|
|
pmc_sc = sc;
|
|
return (0);
|
|
}
|
|
|
|
static device_method_t tegra124_pmc_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_probe, tegra124_pmc_probe),
|
|
DEVMETHOD(device_attach, tegra124_pmc_attach),
|
|
DEVMETHOD(device_detach, tegra124_pmc_detach),
|
|
|
|
DEVMETHOD_END
|
|
};
|
|
|
|
static driver_t tegra124_pmc_driver = {
|
|
"tegra124_pmc",
|
|
tegra124_pmc_methods,
|
|
sizeof(struct tegra124_pmc_softc),
|
|
};
|
|
|
|
static devclass_t tegra124_pmc_devclass;
|
|
EARLY_DRIVER_MODULE(tegra124_pmc, simplebus, tegra124_pmc_driver,
|
|
tegra124_pmc_devclass, 0, 0, 70);
|