4192788cb2
Let drivers for Alpine CCU, NB and Serdes take care of internal SoC configuration. Obtained from: Semihalf Submitted by: Michal Stanek <mst@semihalf.com> Sponsored by: Annapurna Labs Reviewed by: imp,wma Differential Revision: https://reviews.freebsd.org/D7566
249 lines
6.8 KiB
C
249 lines
6.8 KiB
C
/*-
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* Copyright (c) 2013 Ruslan Bukin <br@bsdpad.com>
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* Copyright (c) 2015 Semihalf
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/smp.h>
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#include <sys/cpuset.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <machine/smp.h>
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#include <machine/fdt.h>
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#include <machine/intr.h>
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#include <machine/cpu-v6.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/ofw_cpu.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#define AL_CPU_RESUME_WATERMARK_REG 0x00
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#define AL_CPU_RESUME_FLAGS_REG 0x04
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#define AL_CPU_RESUME_PCPU_RADDR_REG(cpu) (0x08 + 0x04 + 8*(cpu))
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#define AL_CPU_RESUME_PCPU_FLAGS(cpu) (0x08 + 8*(cpu))
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/* Per-CPU flags */
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#define AL_CPU_RESUME_FLG_PERCPU_DONT_RESUME (1 << 2)
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/* The expected magic number for validating the resume addresses */
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#define AL_CPU_RESUME_MAGIC_NUM 0xf0e1d200
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#define AL_CPU_RESUME_MAGIC_NUM_MASK 0xffffff00
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/* The expected minimal version number for validating the capabilities */
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#define AL_CPU_RESUME_MIN_VER 0x000000c3
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#define AL_CPU_RESUME_MIN_VER_MASK 0x000000ff
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/* Field controlling the boot-up of companion cores */
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#define AL_NB_INIT_CONTROL (0x8)
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#define AL_NB_CONFIG_STATUS_PWR_CTRL(cpu) (0x2020 + (cpu)*0x100)
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extern bus_addr_t al_devmap_pa;
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extern bus_addr_t al_devmap_size;
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extern void mpentry(void);
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static int platform_mp_get_core_cnt(void);
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static int alpine_get_cpu_resume_base(u_long *pbase, u_long *psize);
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static int alpine_get_nb_base(u_long *pbase, u_long *psize);
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static boolean_t alpine_validate_cpu(u_int, phandle_t, u_int, pcell_t *);
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static boolean_t
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alpine_validate_cpu(u_int id, phandle_t child, u_int addr_cell, pcell_t *reg)
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{
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return fdt_is_compatible(child, "arm,cortex-a15");
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}
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static int
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platform_mp_get_core_cnt(void)
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{
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static int ncores = 0;
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int nchilds;
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uint32_t reg;
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/* Calculate ncores value only once */
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if (ncores)
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return (ncores);
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reg = cp15_l2ctlr_get();
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ncores = CPUV7_L2CTLR_NPROC(reg);
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nchilds = ofw_cpu_early_foreach(alpine_validate_cpu, false);
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/* Limit CPUs if DTS has configured less than available */
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if ((nchilds > 0) && (nchilds < ncores)) {
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printf("SMP: limiting number of active CPUs to %d out of %d\n",
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nchilds, ncores);
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ncores = nchilds;
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}
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return (ncores);
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}
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void
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platform_mp_setmaxid(void)
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{
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mp_ncpus = platform_mp_get_core_cnt();
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mp_maxid = mp_ncpus - 1;
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}
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static int
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alpine_get_cpu_resume_base(u_long *pbase, u_long *psize)
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{
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phandle_t node;
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u_long base = 0;
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u_long size = 0;
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if (pbase == NULL || psize == NULL)
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return (EINVAL);
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if ((node = OF_finddevice("/")) == -1)
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return (EFAULT);
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if ((node =
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ofw_bus_find_compatible(node, "annapurna-labs,al-cpu-resume")) == 0)
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return (EFAULT);
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if (fdt_regsize(node, &base, &size))
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return (EFAULT);
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*pbase = base;
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*psize = size;
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return (0);
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}
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static int
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alpine_get_nb_base(u_long *pbase, u_long *psize)
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{
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phandle_t node;
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u_long base = 0;
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u_long size = 0;
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if (pbase == NULL || psize == NULL)
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return (EINVAL);
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if ((node = OF_finddevice("/")) == -1)
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return (EFAULT);
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if ((node =
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ofw_bus_find_compatible(node, "annapurna-labs,al-nb-service")) == 0)
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return (EFAULT);
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if (fdt_regsize(node, &base, &size))
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return (EFAULT);
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*pbase = base;
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*psize = size;
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return (0);
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}
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void
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platform_mp_start_ap(void)
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{
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uint32_t physaddr;
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vm_offset_t vaddr;
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uint32_t val;
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uint32_t start_mask;
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u_long cpu_resume_base;
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u_long nb_base;
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u_long cpu_resume_size;
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u_long nb_size;
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bus_addr_t cpu_resume_baddr;
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bus_addr_t nb_baddr;
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int a;
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if (alpine_get_cpu_resume_base(&cpu_resume_base, &cpu_resume_size))
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panic("Couldn't resolve cpu_resume_base address\n");
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if (alpine_get_nb_base(&nb_base, &nb_size))
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panic("Couldn't resolve_nb_base address\n");
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/* Proceed with start addresses for additional CPUs */
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if (bus_space_map(fdtbus_bs_tag, al_devmap_pa + cpu_resume_base,
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cpu_resume_size, 0, &cpu_resume_baddr))
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panic("Couldn't map CPU-resume area");
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if (bus_space_map(fdtbus_bs_tag, al_devmap_pa + nb_base,
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nb_size, 0, &nb_baddr))
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panic("Couldn't map NB-service area");
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/* Proceed with start addresses for additional CPUs */
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val = bus_space_read_4(fdtbus_bs_tag, cpu_resume_baddr,
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AL_CPU_RESUME_WATERMARK_REG);
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if (((val & AL_CPU_RESUME_MAGIC_NUM_MASK) != AL_CPU_RESUME_MAGIC_NUM) ||
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((val & AL_CPU_RESUME_MIN_VER_MASK) < AL_CPU_RESUME_MIN_VER)) {
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panic("CPU-resume device is not compatible");
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}
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vaddr = (vm_offset_t)mpentry;
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physaddr = pmap_kextract(vaddr);
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for (a = 1; a < platform_mp_get_core_cnt(); a++) {
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/* Power up the core */
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bus_space_write_4(fdtbus_bs_tag, nb_baddr,
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AL_NB_CONFIG_STATUS_PWR_CTRL(a), 0);
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mb();
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/* Enable resume */
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val = bus_space_read_4(fdtbus_bs_tag, cpu_resume_baddr,
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AL_CPU_RESUME_PCPU_FLAGS(a));
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val &= ~AL_CPU_RESUME_FLG_PERCPU_DONT_RESUME;
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bus_space_write_4(fdtbus_bs_tag, cpu_resume_baddr,
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AL_CPU_RESUME_PCPU_FLAGS(a), val);
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mb();
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/* Set resume physical address */
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bus_space_write_4(fdtbus_bs_tag, cpu_resume_baddr,
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AL_CPU_RESUME_PCPU_RADDR_REG(a), physaddr);
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mb();
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}
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/* Release cores from reset */
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if (bus_space_map(fdtbus_bs_tag, al_devmap_pa + nb_base,
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nb_size, 0, &nb_baddr))
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panic("Couldn't map NB-service area");
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start_mask = (1 << platform_mp_get_core_cnt()) - 1;
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/* Release cores from reset */
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val = bus_space_read_4(fdtbus_bs_tag, nb_baddr, AL_NB_INIT_CONTROL);
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val |= start_mask;
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bus_space_write_4(fdtbus_bs_tag, nb_baddr, AL_NB_INIT_CONTROL, val);
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dsb();
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bus_space_unmap(fdtbus_bs_tag, nb_baddr, nb_size);
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bus_space_unmap(fdtbus_bs_tag, cpu_resume_baddr, cpu_resume_size);
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}
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