c01f2b8301
- support for the new Gen-2, BT, and LP-CR cards. - T3 firmware 7.7.0 - shared "common code" updates. Approved by: gnn (mentor) Obtained from: Chelsio MFC after: 1 month
222 lines
6.1 KiB
C
222 lines
6.1 KiB
C
/**************************************************************************
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Copyright (c) 2008, Chelsio Inc.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Neither the name of the Chelsio Corporation nor the names of its
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contributors may be used to endorse or promote products derived from
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this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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***************************************************************************/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <cxgb_include.h>
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#undef msleep
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#define msleep t3_os_sleep
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/* TN1010 PHY specific registers. */
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enum {
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TN1010_VEND1_STAT = 1,
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};
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/* IEEE auto-negotiation 10GBASE-T registers */
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enum {
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ANEG_ADVER = 16,
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ANEG_LPA = 19,
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ANEG_10G_CTRL = 32,
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ANEG_10G_STAT = 33
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};
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#define ADVERTISE_ENPAGE (1 << 12)
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#define ADVERTISE_10000FULL (1 << 12)
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#define ADVERTISE_LOOP_TIMING (1 << 0)
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/* vendor specific status register fields */
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#define F_XS_LANE_ALIGN_STAT (1 << 0)
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#define F_PCS_BLK_LOCK (1 << 1)
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#define F_PMD_SIGNAL_OK (1 << 2)
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#define F_LINK_STAT (1 << 3)
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#define F_ANEG_SPEED_1G (1 << 4)
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#define F_ANEG_MASTER (1 << 5)
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#define S_ANEG_STAT 6
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#define M_ANEG_STAT 0x3
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#define G_ANEG_STAT(x) (((x) >> S_ANEG_STAT) & M_ANEG_STAT)
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enum { /* autonegotiation status */
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ANEG_IN_PROGR = 0,
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ANEG_COMPLETE = 1,
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ANEG_FAILED = 3
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};
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/*
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* Reset the PHY. May take up to 500ms to complete.
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*/
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static int tn1010_reset(struct cphy *phy, int wait)
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{
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int err = t3_phy_reset(phy, MDIO_DEV_PMA_PMD, wait);
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msleep(500);
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return err;
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}
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static int tn1010_power_down(struct cphy *phy, int enable)
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{
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return t3_mdio_change_bits(phy, MDIO_DEV_PMA_PMD, MII_BMCR,
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BMCR_PDOWN, enable ? BMCR_PDOWN : 0);
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}
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static int tn1010_autoneg_enable(struct cphy *phy)
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{
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int err;
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err = tn1010_power_down(phy, 0);
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if (!err)
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err = t3_mdio_change_bits(phy, MDIO_DEV_ANEG, MII_BMCR, 0,
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BMCR_ANENABLE | BMCR_ANRESTART);
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return err;
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}
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static int tn1010_autoneg_restart(struct cphy *phy)
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{
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int err;
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err = tn1010_power_down(phy, 0);
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if (!err)
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err = t3_mdio_change_bits(phy, MDIO_DEV_ANEG, MII_BMCR, 0,
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BMCR_ANRESTART);
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return err;
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}
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static int tn1010_advertise(struct cphy *phy, unsigned int advert)
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{
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int err, val;
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if (!(advert & ADVERTISED_1000baseT_Full))
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return -EINVAL; /* PHY can't disable 1000BASE-T */
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val = ADVERTISE_CSMA | ADVERTISE_ENPAGE | ADVERTISE_NPAGE;
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if (advert & ADVERTISED_Pause)
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val |= ADVERTISE_PAUSE_CAP;
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if (advert & ADVERTISED_Asym_Pause)
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val |= ADVERTISE_PAUSE_ASYM;
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err = mdio_write(phy, MDIO_DEV_ANEG, ANEG_ADVER, val);
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if (err)
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return err;
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val = (advert & ADVERTISED_10000baseT_Full) ? ADVERTISE_10000FULL : 0;
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return mdio_write(phy, MDIO_DEV_ANEG, ANEG_10G_CTRL, val |
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ADVERTISE_LOOP_TIMING);
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}
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static int tn1010_get_link_status(struct cphy *phy, int *link_ok,
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int *speed, int *duplex, int *fc)
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{
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unsigned int status, lpa, adv;
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int err, sp = -1, pause = 0;
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err = mdio_read(phy, MDIO_DEV_VEND1, TN1010_VEND1_STAT, &status);
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if (err)
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return err;
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if (link_ok)
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*link_ok = (status & F_LINK_STAT) != 0;
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if (G_ANEG_STAT(status) == ANEG_COMPLETE) {
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sp = (status & F_ANEG_SPEED_1G) ? SPEED_1000 : SPEED_10000;
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if (fc) {
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err = mdio_read(phy, MDIO_DEV_ANEG, ANEG_LPA, &lpa);
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if (!err)
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err = mdio_read(phy, MDIO_DEV_ANEG, ANEG_ADVER,
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&adv);
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if (err)
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return err;
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if (lpa & adv & ADVERTISE_PAUSE_CAP)
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pause = PAUSE_RX | PAUSE_TX;
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else if ((lpa & ADVERTISE_PAUSE_CAP) &&
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(lpa & ADVERTISE_PAUSE_ASYM) &&
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(adv & ADVERTISE_PAUSE_ASYM))
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pause = PAUSE_TX;
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else if ((lpa & ADVERTISE_PAUSE_ASYM) &&
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(adv & ADVERTISE_PAUSE_CAP))
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pause = PAUSE_RX;
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}
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}
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if (speed)
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*speed = sp;
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if (duplex)
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*duplex = DUPLEX_FULL;
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if (fc)
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*fc = pause;
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return 0;
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}
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static int tn1010_set_speed_duplex(struct cphy *phy, int speed, int duplex)
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{
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return -EINVAL; /* require autoneg */
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}
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#ifdef C99_NOT_SUPPORTED
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static struct cphy_ops tn1010_ops = {
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tn1010_reset,
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t3_phy_lasi_intr_enable,
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t3_phy_lasi_intr_disable,
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t3_phy_lasi_intr_clear,
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t3_phy_lasi_intr_handler,
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tn1010_autoneg_enable,
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tn1010_autoneg_restart,
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tn1010_advertise,
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NULL,
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tn1010_set_speed_duplex,
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tn1010_get_link_status,
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tn1010_power_down,
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};
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#else
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static struct cphy_ops tn1010_ops = {
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.reset = tn1010_reset,
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.intr_enable = t3_phy_lasi_intr_enable,
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.intr_disable = t3_phy_lasi_intr_disable,
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.intr_clear = t3_phy_lasi_intr_clear,
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.intr_handler = t3_phy_lasi_intr_handler,
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.autoneg_enable = tn1010_autoneg_enable,
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.autoneg_restart = tn1010_autoneg_restart,
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.advertise = tn1010_advertise,
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.set_speed_duplex = tn1010_set_speed_duplex,
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.get_link_status = tn1010_get_link_status,
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.power_down = tn1010_power_down,
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};
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#endif
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int t3_tn1010_phy_prep(pinfo_t *pinfo, int phy_addr,
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const struct mdio_ops *mdio_ops)
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{
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cphy_init(&pinfo->phy, pinfo->adapter, pinfo, phy_addr, &tn1010_ops, mdio_ops,
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SUPPORTED_1000baseT_Full | SUPPORTED_10000baseT_Full |
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SUPPORTED_Autoneg | SUPPORTED_AUI | SUPPORTED_TP,
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"1000/10GBASE-T");
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msleep(500); /* PHY needs up to 500ms to start responding to MDIO */
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return 0;
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}
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