529 lines
12 KiB
C
529 lines
12 KiB
C
/*-
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* Copyright (c) 2013 Ganbold Tsagaankhuu <ganbold@freebsd.org>
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* Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
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* Copyright (c) 2012 Luiz Otavio O Souza.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/gpio.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/cpufunc.h>
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#include <machine/resource.h>
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#include <machine/fdt.h>
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#include <machine/intr.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include "gpio_if.h"
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#include "a10_gpio.h"
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/*
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* A10 have 9 banks of gpio.
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* 32 pins per bank:
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* PA0 - PA17 | PB0 - PB23 | PC0 - PC24
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* PD0 - PD27 | PE0 - PE31 | PF0 - PF5
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* PG0 - PG9 | PH0 - PH27 | PI0 - PI12
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*/
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#define A10_GPIO_PINS 288
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#define A10_GPIO_DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \
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GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN)
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#define A10_GPIO_NONE 0
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#define A10_GPIO_PULLUP 1
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#define A10_GPIO_PULLDOWN 2
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#define A10_GPIO_INPUT 0
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#define A10_GPIO_OUTPUT 1
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struct a10_gpio_softc {
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device_t sc_dev;
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struct mtx sc_mtx;
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struct resource * sc_mem_res;
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struct resource * sc_irq_res;
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bus_space_tag_t sc_bst;
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bus_space_handle_t sc_bsh;
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void * sc_intrhand;
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int sc_gpio_npins;
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struct gpio_pin sc_gpio_pins[A10_GPIO_PINS];
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};
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#define A10_GPIO_LOCK(_sc) mtx_lock(&_sc->sc_mtx)
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#define A10_GPIO_UNLOCK(_sc) mtx_unlock(&_sc->sc_mtx)
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#define A10_GPIO_LOCK_ASSERT(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED)
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#define A10_GPIO_GP_CFG(_bank, _pin) 0x00 + ((_bank) * 0x24) + ((_pin)<<2)
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#define A10_GPIO_GP_DAT(_bank) 0x10 + ((_bank) * 0x24)
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#define A10_GPIO_GP_DRV(_bank, _pin) 0x14 + ((_bank) * 0x24) + ((_pin)<<2)
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#define A10_GPIO_GP_PUL(_bank, _pin) 0x1c + ((_bank) * 0x24) + ((_pin)<<2)
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#define A10_GPIO_GP_INT_CFG0 0x200
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#define A10_GPIO_GP_INT_CFG1 0x204
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#define A10_GPIO_GP_INT_CFG2 0x208
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#define A10_GPIO_GP_INT_CFG3 0x20c
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#define A10_GPIO_GP_INT_CTL 0x210
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#define A10_GPIO_GP_INT_STA 0x214
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#define A10_GPIO_GP_INT_DEB 0x218
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static struct a10_gpio_softc *a10_gpio_sc;
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#define A10_GPIO_WRITE(_sc, _off, _val) \
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bus_space_write_4(_sc->sc_bst, _sc->sc_bsh, _off, _val)
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#define A10_GPIO_READ(_sc, _off) \
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bus_space_read_4(_sc->sc_bst, _sc->sc_bsh, _off)
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static uint32_t
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a10_gpio_get_function(struct a10_gpio_softc *sc, uint32_t pin)
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{
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uint32_t bank, func, offset;
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bank = pin / 32;
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pin = pin - 32 * bank;
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func = pin >> 3;
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offset = ((pin & 0x07) << 2);
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A10_GPIO_LOCK(sc);
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func = (A10_GPIO_READ(sc, A10_GPIO_GP_CFG(bank, func)) >> offset) & 7;
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A10_GPIO_UNLOCK(sc);
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return (func);
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}
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static uint32_t
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a10_gpio_func_flag(uint32_t nfunc)
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{
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switch (nfunc) {
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case A10_GPIO_INPUT:
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return (GPIO_PIN_INPUT);
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case A10_GPIO_OUTPUT:
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return (GPIO_PIN_OUTPUT);
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}
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return (0);
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}
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static void
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a10_gpio_set_function(struct a10_gpio_softc *sc, uint32_t pin, uint32_t f)
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{
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uint32_t bank, func, data, offset;
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/* Must be called with lock held. */
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A10_GPIO_LOCK_ASSERT(sc);
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bank = pin / 32;
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pin = pin - 32 * bank;
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func = pin >> 3;
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offset = ((pin & 0x07) << 2);
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data = A10_GPIO_READ(sc, A10_GPIO_GP_CFG(bank, func));
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data &= ~(7 << offset);
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data |= (f << offset);
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A10_GPIO_WRITE(sc, A10_GPIO_GP_CFG(bank, func), data);
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}
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static void
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a10_gpio_set_pud(struct a10_gpio_softc *sc, uint32_t pin, uint32_t state)
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{
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uint32_t bank, offset, pull, val;
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/* Must be called with lock held. */
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A10_GPIO_LOCK_ASSERT(sc);
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bank = pin / 32;
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pin = pin - 32 * bank;
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pull = pin >> 4;
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offset = ((pin & 0x0f) << 1);
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val = A10_GPIO_READ(sc, A10_GPIO_GP_PUL(bank, pull));
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val &= ~(0x03 << offset);
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val |= (state << offset);
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A10_GPIO_WRITE(sc, A10_GPIO_GP_PUL(bank, pull), val);
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}
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static void
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a10_gpio_pin_configure(struct a10_gpio_softc *sc, struct gpio_pin *pin,
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unsigned int flags)
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{
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A10_GPIO_LOCK(sc);
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/*
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* Manage input/output.
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*/
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if (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) {
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pin->gp_flags &= ~(GPIO_PIN_INPUT|GPIO_PIN_OUTPUT);
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if (flags & GPIO_PIN_OUTPUT) {
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pin->gp_flags |= GPIO_PIN_OUTPUT;
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a10_gpio_set_function(sc, pin->gp_pin,
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A10_GPIO_OUTPUT);
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} else {
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pin->gp_flags |= GPIO_PIN_INPUT;
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a10_gpio_set_function(sc, pin->gp_pin,
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A10_GPIO_INPUT);
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}
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}
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/* Manage Pull-up/pull-down. */
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pin->gp_flags &= ~(GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN);
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if (flags & (GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN)) {
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if (flags & GPIO_PIN_PULLUP) {
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pin->gp_flags |= GPIO_PIN_PULLUP;
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a10_gpio_set_pud(sc, pin->gp_pin, A10_GPIO_PULLUP);
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} else {
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pin->gp_flags |= GPIO_PIN_PULLDOWN;
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a10_gpio_set_pud(sc, pin->gp_pin, A10_GPIO_PULLDOWN);
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}
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} else
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a10_gpio_set_pud(sc, pin->gp_pin, A10_GPIO_NONE);
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A10_GPIO_UNLOCK(sc);
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}
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static int
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a10_gpio_pin_max(device_t dev, int *maxpin)
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{
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*maxpin = A10_GPIO_PINS - 1;
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return (0);
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}
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static int
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a10_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
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{
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struct a10_gpio_softc *sc = device_get_softc(dev);
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int i;
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for (i = 0; i < sc->sc_gpio_npins; i++) {
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if (sc->sc_gpio_pins[i].gp_pin == pin)
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break;
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}
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if (i >= sc->sc_gpio_npins)
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return (EINVAL);
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A10_GPIO_LOCK(sc);
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*caps = sc->sc_gpio_pins[i].gp_caps;
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A10_GPIO_UNLOCK(sc);
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return (0);
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}
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static int
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a10_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
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{
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struct a10_gpio_softc *sc = device_get_softc(dev);
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int i;
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for (i = 0; i < sc->sc_gpio_npins; i++) {
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if (sc->sc_gpio_pins[i].gp_pin == pin)
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break;
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}
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if (i >= sc->sc_gpio_npins)
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return (EINVAL);
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A10_GPIO_LOCK(sc);
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*flags = sc->sc_gpio_pins[i].gp_flags;
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A10_GPIO_UNLOCK(sc);
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return (0);
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}
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static int
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a10_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
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{
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struct a10_gpio_softc *sc = device_get_softc(dev);
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int i;
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for (i = 0; i < sc->sc_gpio_npins; i++) {
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if (sc->sc_gpio_pins[i].gp_pin == pin)
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break;
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}
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if (i >= sc->sc_gpio_npins)
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return (EINVAL);
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A10_GPIO_LOCK(sc);
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memcpy(name, sc->sc_gpio_pins[i].gp_name, GPIOMAXNAME);
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A10_GPIO_UNLOCK(sc);
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return (0);
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}
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static int
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a10_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
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{
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struct a10_gpio_softc *sc = device_get_softc(dev);
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int i;
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for (i = 0; i < sc->sc_gpio_npins; i++) {
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if (sc->sc_gpio_pins[i].gp_pin == pin)
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break;
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}
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if (i >= sc->sc_gpio_npins)
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return (EINVAL);
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a10_gpio_pin_configure(sc, &sc->sc_gpio_pins[i], flags);
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return (0);
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}
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static int
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a10_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
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{
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struct a10_gpio_softc *sc = device_get_softc(dev);
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uint32_t bank, offset, data;
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int i;
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for (i = 0; i < sc->sc_gpio_npins; i++) {
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if (sc->sc_gpio_pins[i].gp_pin == pin)
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break;
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}
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if (i >= sc->sc_gpio_npins)
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return (EINVAL);
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bank = pin / 32;
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pin = pin - 32 * bank;
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offset = pin & 0x1f;
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A10_GPIO_LOCK(sc);
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data = A10_GPIO_READ(sc, A10_GPIO_GP_DAT(bank));
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if (value)
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data |= (1 << offset);
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else
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data &= ~(1 << offset);
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A10_GPIO_WRITE(sc, A10_GPIO_GP_DAT(bank), data);
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A10_GPIO_UNLOCK(sc);
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return (0);
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}
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static int
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a10_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
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{
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struct a10_gpio_softc *sc = device_get_softc(dev);
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uint32_t bank, offset, reg_data;
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int i;
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for (i = 0; i < sc->sc_gpio_npins; i++) {
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if (sc->sc_gpio_pins[i].gp_pin == pin)
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break;
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}
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if (i >= sc->sc_gpio_npins)
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return (EINVAL);
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bank = pin / 32;
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pin = pin - 32 * bank;
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offset = pin & 0x1f;
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A10_GPIO_LOCK(sc);
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reg_data = A10_GPIO_READ(sc, A10_GPIO_GP_DAT(bank));
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A10_GPIO_UNLOCK(sc);
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*val = (reg_data & (1 << offset)) ? 1 : 0;
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return (0);
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}
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static int
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a10_gpio_pin_toggle(device_t dev, uint32_t pin)
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{
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struct a10_gpio_softc *sc = device_get_softc(dev);
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uint32_t bank, data, offset;
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int i;
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for (i = 0; i < sc->sc_gpio_npins; i++) {
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if (sc->sc_gpio_pins[i].gp_pin == pin)
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break;
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}
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if (i >= sc->sc_gpio_npins)
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return (EINVAL);
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bank = pin / 32;
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pin = pin - 32 * bank;
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offset = pin & 0x1f;
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A10_GPIO_LOCK(sc);
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data = A10_GPIO_READ(sc, A10_GPIO_GP_DAT(bank));
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if (data & (1 << offset))
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data &= ~(1 << offset);
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else
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data |= (1 << offset);
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A10_GPIO_WRITE(sc, A10_GPIO_GP_DAT(bank), data);
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A10_GPIO_UNLOCK(sc);
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return (0);
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}
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static int
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a10_gpio_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_is_compatible(dev, "allwinner,sun4i-gpio"))
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return (ENXIO);
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device_set_desc(dev, "Allwinner GPIO controller");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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a10_gpio_attach(device_t dev)
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{
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struct a10_gpio_softc *sc = device_get_softc(dev);
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uint32_t func;
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int i, rid;
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phandle_t gpio;
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sc->sc_dev = dev;
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mtx_init(&sc->sc_mtx, "a10 gpio", "gpio", MTX_DEF);
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rid = 0;
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sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
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RF_ACTIVE);
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if (!sc->sc_mem_res) {
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device_printf(dev, "cannot allocate memory window\n");
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return (ENXIO);
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}
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sc->sc_bst = rman_get_bustag(sc->sc_mem_res);
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sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res);
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rid = 0;
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sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
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RF_ACTIVE);
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if (!sc->sc_irq_res) {
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bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
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device_printf(dev, "cannot allocate interrupt\n");
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return (ENXIO);
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}
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/* Find our node. */
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gpio = ofw_bus_get_node(sc->sc_dev);
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if (!OF_hasprop(gpio, "gpio-controller"))
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/* Node is not a GPIO controller. */
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goto fail;
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/* Initialize the software controlled pins. */
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for (i = 0; i < A10_GPIO_PINS; i++) {
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snprintf(sc->sc_gpio_pins[i].gp_name, GPIOMAXNAME,
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"pin %d", i);
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func = a10_gpio_get_function(sc, i);
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sc->sc_gpio_pins[i].gp_pin = i;
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sc->sc_gpio_pins[i].gp_caps = A10_GPIO_DEFAULT_CAPS;
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sc->sc_gpio_pins[i].gp_flags = a10_gpio_func_flag(func);
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}
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sc->sc_gpio_npins = i;
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device_add_child(dev, "gpioc", -1);
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device_add_child(dev, "gpiobus", -1);
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a10_gpio_sc = sc;
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return (bus_generic_attach(dev));
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fail:
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if (sc->sc_irq_res)
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bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
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if (sc->sc_mem_res)
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bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
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return (ENXIO);
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}
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static int
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a10_gpio_detach(device_t dev)
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{
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return (EBUSY);
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}
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static device_method_t a10_gpio_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, a10_gpio_probe),
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DEVMETHOD(device_attach, a10_gpio_attach),
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DEVMETHOD(device_detach, a10_gpio_detach),
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/* GPIO protocol */
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DEVMETHOD(gpio_pin_max, a10_gpio_pin_max),
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DEVMETHOD(gpio_pin_getname, a10_gpio_pin_getname),
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DEVMETHOD(gpio_pin_getflags, a10_gpio_pin_getflags),
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DEVMETHOD(gpio_pin_getcaps, a10_gpio_pin_getcaps),
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DEVMETHOD(gpio_pin_setflags, a10_gpio_pin_setflags),
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DEVMETHOD(gpio_pin_get, a10_gpio_pin_get),
|
|
DEVMETHOD(gpio_pin_set, a10_gpio_pin_set),
|
|
DEVMETHOD(gpio_pin_toggle, a10_gpio_pin_toggle),
|
|
|
|
DEVMETHOD_END
|
|
};
|
|
|
|
static devclass_t a10_gpio_devclass;
|
|
|
|
static driver_t a10_gpio_driver = {
|
|
"gpio",
|
|
a10_gpio_methods,
|
|
sizeof(struct a10_gpio_softc),
|
|
};
|
|
|
|
DRIVER_MODULE(a10_gpio, simplebus, a10_gpio_driver, a10_gpio_devclass, 0, 0);
|
|
|
|
int
|
|
a10_emac_gpio_config(uint32_t pin)
|
|
{
|
|
struct a10_gpio_softc *sc = a10_gpio_sc;
|
|
|
|
if (sc == NULL)
|
|
return (ENXIO);
|
|
|
|
/* Configure pin mux settings for MII. */
|
|
A10_GPIO_LOCK(sc);
|
|
a10_gpio_set_function(sc, pin, A10_GPIO_PULLDOWN);
|
|
A10_GPIO_UNLOCK(sc);
|
|
|
|
return (0);
|
|
}
|