f5f9340b98
New kernel events can be added at various location for sampling or counting. This will for example allow easy system profiling whatever the processor is with known tools like pmcstat(8). Simultaneous usage of software PMC and hardware PMC is possible, for example looking at the lock acquire failure, page fault while sampling on instructions. Sponsored by: NETASQ MFC after: 1 month
677 lines
16 KiB
C
677 lines
16 KiB
C
/*-
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* Copyright (c) 2009 Rui Paulo <rpaulo@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/pmc.h>
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#include <sys/pmckern.h>
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#include <machine/pmc_mdep.h>
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/*
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* Support for the Intel XScale network processors
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*
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* XScale processors have up to now three generations.
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*
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* The first generation has two PMC; the event selection, interrupt config
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* and overflow flag setup are done by writing to the PMNC register.
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* It also has less monitoring events than the latter generations.
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*
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* The second and third generatiosn have four PMCs, one register for the event
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* selection, one register for the interrupt config and one register for
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* the overflow flags.
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*/
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static int xscale_npmcs;
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static int xscale_gen; /* XScale Core generation */
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struct xscale_event_code_map {
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enum pmc_event pe_ev;
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uint8_t pe_code;
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};
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const struct xscale_event_code_map xscale_event_codes[] = {
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/* 1st and 2nd Generation XScale cores */
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{ PMC_EV_XSCALE_IC_FETCH, 0x00 },
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{ PMC_EV_XSCALE_IC_MISS, 0x01 },
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{ PMC_EV_XSCALE_DATA_DEPENDENCY_STALLED,0x02 },
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{ PMC_EV_XSCALE_ITLB_MISS, 0x03 },
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{ PMC_EV_XSCALE_DTLB_MISS, 0x04 },
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{ PMC_EV_XSCALE_BRANCH_RETIRED, 0x05 },
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{ PMC_EV_XSCALE_BRANCH_MISPRED, 0x06 },
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{ PMC_EV_XSCALE_INSTR_RETIRED, 0x07 },
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{ PMC_EV_XSCALE_DC_FULL_CYCLE, 0x08 },
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{ PMC_EV_XSCALE_DC_FULL_CONTIG, 0x09 },
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{ PMC_EV_XSCALE_DC_ACCESS, 0x0a },
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{ PMC_EV_XSCALE_DC_MISS, 0x0b },
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{ PMC_EV_XSCALE_DC_WRITEBACK, 0x0c },
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{ PMC_EV_XSCALE_PC_CHANGE, 0x0d },
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/* 3rd Generation XScale cores */
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{ PMC_EV_XSCALE_BRANCH_RETIRED_ALL, 0x0e },
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{ PMC_EV_XSCALE_INSTR_CYCLE, 0x0f },
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{ PMC_EV_XSCALE_CP_STALL, 0x17 },
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{ PMC_EV_XSCALE_PC_CHANGE_ALL, 0x18 },
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{ PMC_EV_XSCALE_PIPELINE_FLUSH, 0x19 },
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{ PMC_EV_XSCALE_BACKEND_STALL, 0x1a },
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{ PMC_EV_XSCALE_MULTIPLIER_USE, 0x1b },
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{ PMC_EV_XSCALE_MULTIPLIER_STALLED, 0x1c },
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{ PMC_EV_XSCALE_DATA_CACHE_STALLED, 0x1e },
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{ PMC_EV_XSCALE_L2_CACHE_REQ, 0x20 },
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{ PMC_EV_XSCALE_L2_CACHE_MISS, 0x23 },
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{ PMC_EV_XSCALE_ADDRESS_BUS_TRANS, 0x40 },
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{ PMC_EV_XSCALE_SELF_ADDRESS_BUS_TRANS, 0x41 },
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{ PMC_EV_XSCALE_DATA_BUS_TRANS, 0x48 },
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};
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const int xscale_event_codes_size =
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sizeof(xscale_event_codes) / sizeof(xscale_event_codes[0]);
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/*
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* Per-processor information.
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*/
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struct xscale_cpu {
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struct pmc_hw *pc_xscalepmcs;
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};
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static struct xscale_cpu **xscale_pcpu;
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/*
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* Performance Monitor Control Register
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*/
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static __inline uint32_t
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xscale_pmnc_read(void)
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{
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uint32_t reg;
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__asm __volatile("mrc p14, 0, %0, c0, c1, 0" : "=r" (reg));
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return (reg);
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}
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static __inline void
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xscale_pmnc_write(uint32_t reg)
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{
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__asm __volatile("mcr p14, 0, %0, c0, c1, 0" : : "r" (reg));
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}
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/*
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* Clock Counter Register
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*/
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static __inline uint32_t
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xscale_ccnt_read(void)
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{
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uint32_t reg;
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__asm __volatile("mrc p14, 0, %0, c1, c1, 0" : "=r" (reg));
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return (reg);
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}
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static __inline void
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xscale_ccnt_write(uint32_t reg)
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{
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__asm __volatile("mcr p14, 0, %0, c1, c1, 0" : : "r" (reg));
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}
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/*
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* Interrupt Enable Register
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*/
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static __inline uint32_t
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xscale_inten_read(void)
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{
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uint32_t reg;
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__asm __volatile("mrc p14, 0, %0, c4, c1, 0" : "=r" (reg));
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return (reg);
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}
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static __inline void
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xscale_inten_write(uint32_t reg)
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{
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__asm __volatile("mcr p14, 0, %0, c4, c1, 0" : : "r" (reg));
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}
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/*
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* Overflow Flag Register
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*/
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static __inline uint32_t
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xscale_flag_read(void)
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{
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uint32_t reg;
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__asm __volatile("mrc p14, 0, %0, c5, c1, 0" : "=r" (reg));
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return (reg);
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}
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static __inline void
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xscale_flag_write(uint32_t reg)
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{
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__asm __volatile("mcr p14, 0, %0, c5, c1, 0" : : "r" (reg));
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}
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/*
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* Event Selection Register
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*/
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static __inline uint32_t
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xscale_evtsel_read(void)
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{
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uint32_t reg;
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__asm __volatile("mrc p14, 0, %0, c8, c1, 0" : "=r" (reg));
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return (reg);
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}
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static __inline void
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xscale_evtsel_write(uint32_t reg)
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{
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__asm __volatile("mcr p14, 0, %0, c8, c1, 0" : : "r" (reg));
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}
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/*
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* Performance Count Register N
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*/
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static uint32_t
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xscale_pmcn_read(unsigned int pmc)
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{
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uint32_t reg = 0;
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KASSERT(pmc < 4, ("[xscale,%d] illegal PMC number %d", __LINE__, pmc));
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switch (pmc) {
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case 0:
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__asm __volatile("mrc p14, 0, %0, c0, c2, 0" : "=r" (reg));
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break;
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case 1:
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__asm __volatile("mrc p14, 0, %0, c1, c2, 0" : "=r" (reg));
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break;
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case 2:
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__asm __volatile("mrc p14, 0, %0, c2, c2, 0" : "=r" (reg));
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break;
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case 3:
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__asm __volatile("mrc p14, 0, %0, c3, c2, 0" : "=r" (reg));
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break;
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}
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return (reg);
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}
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static uint32_t
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xscale_pmcn_write(unsigned int pmc, uint32_t reg)
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{
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KASSERT(pmc < 4, ("[xscale,%d] illegal PMC number %d", __LINE__, pmc));
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switch (pmc) {
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case 0:
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__asm __volatile("mcr p14, 0, %0, c0, c2, 0" : : "r" (reg));
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break;
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case 1:
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__asm __volatile("mcr p14, 0, %0, c1, c2, 0" : : "r" (reg));
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break;
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case 2:
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__asm __volatile("mcr p14, 0, %0, c2, c2, 0" : : "r" (reg));
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break;
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case 3:
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__asm __volatile("mcr p14, 0, %0, c3, c2, 0" : : "r" (reg));
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break;
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}
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return (reg);
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}
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static int
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xscale_allocate_pmc(int cpu, int ri, struct pmc *pm,
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const struct pmc_op_pmcallocate *a)
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{
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enum pmc_event pe;
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uint32_t caps, config;
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int i;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[xscale,%d] illegal CPU value %d", __LINE__, cpu));
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KASSERT(ri >= 0 && ri < xscale_npmcs,
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("[xscale,%d] illegal row index %d", __LINE__, ri));
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caps = a->pm_caps;
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if (a->pm_class != PMC_CLASS_XSCALE)
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return (EINVAL);
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pe = a->pm_ev;
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for (i = 0; i < xscale_event_codes_size; i++) {
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if (xscale_event_codes[i].pe_ev == pe) {
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config = xscale_event_codes[i].pe_code;
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break;
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}
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}
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if (i == xscale_event_codes_size)
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return EINVAL;
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/* Generation 1 has fewer events */
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if (xscale_gen == 1 && i > PMC_EV_XSCALE_PC_CHANGE)
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return EINVAL;
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pm->pm_md.pm_xscale.pm_xscale_evsel = config;
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PMCDBG(MDP,ALL,2,"xscale-allocate ri=%d -> config=0x%x", ri, config);
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return 0;
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}
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static int
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xscale_read_pmc(int cpu, int ri, pmc_value_t *v)
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{
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struct pmc *pm;
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pmc_value_t tmp;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[xscale,%d] illegal CPU value %d", __LINE__, cpu));
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KASSERT(ri >= 0 && ri < xscale_npmcs,
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("[xscale,%d] illegal row index %d", __LINE__, ri));
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pm = xscale_pcpu[cpu]->pc_xscalepmcs[ri].phw_pmc;
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tmp = xscale_pmcn_read(ri);
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PMCDBG(MDP,REA,2,"xscale-read id=%d -> %jd", ri, tmp);
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if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
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*v = XSCALE_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp);
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else
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*v = tmp;
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return 0;
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}
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static int
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xscale_write_pmc(int cpu, int ri, pmc_value_t v)
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{
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struct pmc *pm;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[xscale,%d] illegal CPU value %d", __LINE__, cpu));
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KASSERT(ri >= 0 && ri < xscale_npmcs,
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("[xscale,%d] illegal row-index %d", __LINE__, ri));
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pm = xscale_pcpu[cpu]->pc_xscalepmcs[ri].phw_pmc;
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if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
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v = XSCALE_RELOAD_COUNT_TO_PERFCTR_VALUE(v);
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PMCDBG(MDP,WRI,1,"xscale-write cpu=%d ri=%d v=%jx", cpu, ri, v);
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xscale_pmcn_write(ri, v);
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return 0;
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}
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static int
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xscale_config_pmc(int cpu, int ri, struct pmc *pm)
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{
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struct pmc_hw *phw;
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PMCDBG(MDP,CFG,1, "cpu=%d ri=%d pm=%p", cpu, ri, pm);
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[xscale,%d] illegal CPU value %d", __LINE__, cpu));
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KASSERT(ri >= 0 && ri < xscale_npmcs,
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("[xscale,%d] illegal row-index %d", __LINE__, ri));
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phw = &xscale_pcpu[cpu]->pc_xscalepmcs[ri];
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KASSERT(pm == NULL || phw->phw_pmc == NULL,
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("[xscale,%d] pm=%p phw->pm=%p hwpmc not unconfigured",
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__LINE__, pm, phw->phw_pmc));
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phw->phw_pmc = pm;
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return 0;
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}
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static int
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xscale_start_pmc(int cpu, int ri)
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{
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uint32_t pmnc, config, evtsel;
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struct pmc *pm;
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struct pmc_hw *phw;
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phw = &xscale_pcpu[cpu]->pc_xscalepmcs[ri];
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pm = phw->phw_pmc;
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config = pm->pm_md.pm_xscale.pm_xscale_evsel;
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/*
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* Configure the event selection.
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*
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* On the XScale 2nd Generation there's no EVTSEL register.
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*/
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if (xscale_npmcs == 2) {
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pmnc = xscale_pmnc_read();
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switch (ri) {
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case 0:
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pmnc &= ~XSCALE_PMNC_EVT0_MASK;
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pmnc |= (config << 12) & XSCALE_PMNC_EVT0_MASK;
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break;
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case 1:
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pmnc &= ~XSCALE_PMNC_EVT1_MASK;
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pmnc |= (config << 20) & XSCALE_PMNC_EVT1_MASK;
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break;
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default:
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/* XXX */
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break;
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}
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xscale_pmnc_write(pmnc);
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} else {
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evtsel = xscale_evtsel_read();
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switch (ri) {
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case 0:
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evtsel &= ~XSCALE_EVTSEL_EVT0_MASK;
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evtsel |= config & XSCALE_EVTSEL_EVT0_MASK;
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break;
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case 1:
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evtsel &= ~XSCALE_EVTSEL_EVT1_MASK;
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evtsel |= (config << 8) & XSCALE_EVTSEL_EVT1_MASK;
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break;
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case 2:
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evtsel &= ~XSCALE_EVTSEL_EVT2_MASK;
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evtsel |= (config << 16) & XSCALE_EVTSEL_EVT2_MASK;
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break;
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case 3:
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evtsel &= ~XSCALE_EVTSEL_EVT3_MASK;
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evtsel |= (config << 24) & XSCALE_EVTSEL_EVT3_MASK;
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break;
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default:
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/* XXX */
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break;
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}
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xscale_evtsel_write(evtsel);
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}
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/*
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* Enable the PMC.
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*
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* Note that XScale provides only one bit to enable/disable _all_
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* performance monitoring units.
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*/
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pmnc = xscale_pmnc_read();
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pmnc |= XSCALE_PMNC_ENABLE;
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xscale_pmnc_write(pmnc);
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return 0;
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}
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static int
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xscale_stop_pmc(int cpu, int ri)
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{
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uint32_t pmnc, evtsel;
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struct pmc *pm;
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struct pmc_hw *phw;
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phw = &xscale_pcpu[cpu]->pc_xscalepmcs[ri];
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pm = phw->phw_pmc;
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/*
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* Disable the PMCs.
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*
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* Note that XScale provides only one bit to enable/disable _all_
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* performance monitoring units.
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*/
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pmnc = xscale_pmnc_read();
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pmnc &= ~XSCALE_PMNC_ENABLE;
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xscale_pmnc_write(pmnc);
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/*
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* A value of 0xff makes the corresponding PMU go into
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* power saving mode.
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*/
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if (xscale_npmcs == 2) {
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pmnc = xscale_pmnc_read();
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switch (ri) {
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case 0:
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pmnc |= XSCALE_PMNC_EVT0_MASK;
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break;
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case 1:
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pmnc |= XSCALE_PMNC_EVT1_MASK;
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break;
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default:
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/* XXX */
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break;
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}
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xscale_pmnc_write(pmnc);
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} else {
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evtsel = xscale_evtsel_read();
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switch (ri) {
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case 0:
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evtsel |= XSCALE_EVTSEL_EVT0_MASK;
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break;
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case 1:
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evtsel |= XSCALE_EVTSEL_EVT1_MASK;
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break;
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case 2:
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evtsel |= XSCALE_EVTSEL_EVT2_MASK;
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break;
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case 3:
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evtsel |= XSCALE_EVTSEL_EVT3_MASK;
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break;
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default:
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/* XXX */
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break;
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}
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xscale_evtsel_write(evtsel);
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}
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return 0;
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}
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static int
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xscale_release_pmc(int cpu, int ri, struct pmc *pmc)
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{
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struct pmc_hw *phw;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[xscale,%d] illegal CPU value %d", __LINE__, cpu));
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KASSERT(ri >= 0 && ri < xscale_npmcs,
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("[xscale,%d] illegal row-index %d", __LINE__, ri));
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phw = &xscale_pcpu[cpu]->pc_xscalepmcs[ri];
|
|
KASSERT(phw->phw_pmc == NULL,
|
|
("[xscale,%d] PHW pmc %p non-NULL", __LINE__, phw->phw_pmc));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
xscale_intr(int cpu, struct trapframe *tf)
|
|
{
|
|
printf("intr\n");
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
xscale_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
|
|
{
|
|
int error;
|
|
struct pmc_hw *phw;
|
|
char xscale_name[PMC_NAME_MAX];
|
|
|
|
KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
|
|
("[xscale,%d], illegal CPU %d", __LINE__, cpu));
|
|
KASSERT(ri >= 0 && ri < xscale_npmcs,
|
|
("[xscale,%d] row-index %d out of range", __LINE__, ri));
|
|
|
|
phw = &xscale_pcpu[cpu]->pc_xscalepmcs[ri];
|
|
snprintf(xscale_name, sizeof(xscale_name), "XSCALE-%d", ri);
|
|
if ((error = copystr(xscale_name, pi->pm_name, PMC_NAME_MAX,
|
|
NULL)) != 0)
|
|
return error;
|
|
pi->pm_class = PMC_CLASS_XSCALE;
|
|
if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
|
|
pi->pm_enabled = TRUE;
|
|
*ppmc = phw->phw_pmc;
|
|
} else {
|
|
pi->pm_enabled = FALSE;
|
|
*ppmc = NULL;
|
|
}
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
xscale_get_config(int cpu, int ri, struct pmc **ppm)
|
|
{
|
|
*ppm = xscale_pcpu[cpu]->pc_xscalepmcs[ri].phw_pmc;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* XXX don't know what we should do here.
|
|
*/
|
|
static int
|
|
xscale_switch_in(struct pmc_cpu *pc, struct pmc_process *pp)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
xscale_switch_out(struct pmc_cpu *pc, struct pmc_process *pp)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
xscale_pcpu_init(struct pmc_mdep *md, int cpu)
|
|
{
|
|
int first_ri, i;
|
|
struct pmc_cpu *pc;
|
|
struct xscale_cpu *pac;
|
|
struct pmc_hw *phw;
|
|
|
|
KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
|
|
("[xscale,%d] wrong cpu number %d", __LINE__, cpu));
|
|
PMCDBG(MDP,INI,1,"xscale-init cpu=%d", cpu);
|
|
|
|
xscale_pcpu[cpu] = pac = malloc(sizeof(struct xscale_cpu), M_PMC,
|
|
M_WAITOK|M_ZERO);
|
|
pac->pc_xscalepmcs = malloc(sizeof(struct pmc_hw) * xscale_npmcs,
|
|
M_PMC, M_WAITOK|M_ZERO);
|
|
pc = pmc_pcpu[cpu];
|
|
first_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_XSCALE].pcd_ri;
|
|
KASSERT(pc != NULL, ("[xscale,%d] NULL per-cpu pointer", __LINE__));
|
|
|
|
for (i = 0, phw = pac->pc_xscalepmcs; i < xscale_npmcs; i++, phw++) {
|
|
phw->phw_state = PMC_PHW_FLAG_IS_ENABLED |
|
|
PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(i);
|
|
phw->phw_pmc = NULL;
|
|
pc->pc_hwpmcs[i + first_ri] = phw;
|
|
}
|
|
|
|
/*
|
|
* Disable and put the PMUs into power save mode.
|
|
*/
|
|
if (xscale_npmcs == 2) {
|
|
xscale_pmnc_write(XSCALE_PMNC_EVT1_MASK |
|
|
XSCALE_PMNC_EVT0_MASK);
|
|
} else {
|
|
xscale_evtsel_write(XSCALE_EVTSEL_EVT3_MASK |
|
|
XSCALE_EVTSEL_EVT2_MASK | XSCALE_EVTSEL_EVT1_MASK |
|
|
XSCALE_EVTSEL_EVT0_MASK);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
xscale_pcpu_fini(struct pmc_mdep *md, int cpu)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
struct pmc_mdep *
|
|
pmc_xscale_initialize()
|
|
{
|
|
struct pmc_mdep *pmc_mdep;
|
|
struct pmc_classdep *pcd;
|
|
uint32_t idreg;
|
|
|
|
/* Get the Core Generation from CP15 */
|
|
__asm __volatile("mrc p15, 0, %0, c0, c0, 0" : "=r" (idreg));
|
|
xscale_gen = (idreg >> 13) & 0x3;
|
|
switch (xscale_gen) {
|
|
case 1:
|
|
xscale_npmcs = 2;
|
|
break;
|
|
case 2:
|
|
case 3:
|
|
xscale_npmcs = 4;
|
|
break;
|
|
default:
|
|
printf("%s: unknown XScale core generation\n", __func__);
|
|
return (NULL);
|
|
}
|
|
PMCDBG(MDP,INI,1,"xscale-init npmcs=%d", xscale_npmcs);
|
|
|
|
/*
|
|
* Allocate space for pointers to PMC HW descriptors and for
|
|
* the MDEP structure used by MI code.
|
|
*/
|
|
xscale_pcpu = malloc(sizeof(struct xscale_cpu *) * pmc_cpu_max(), M_PMC,
|
|
M_WAITOK|M_ZERO);
|
|
|
|
/* Just one class */
|
|
pmc_mdep = pmc_mdep_alloc(1);
|
|
|
|
pmc_mdep->pmd_cputype = PMC_CPU_INTEL_XSCALE;
|
|
|
|
pcd = &pmc_mdep->pmd_classdep[PMC_MDEP_CLASS_INDEX_XSCALE];
|
|
pcd->pcd_caps = XSCALE_PMC_CAPS;
|
|
pcd->pcd_class = PMC_CLASS_XSCALE;
|
|
pcd->pcd_num = xscale_npmcs;
|
|
pcd->pcd_ri = pmc_mdep->pmd_npmc;
|
|
pcd->pcd_width = 32;
|
|
|
|
pcd->pcd_allocate_pmc = xscale_allocate_pmc;
|
|
pcd->pcd_config_pmc = xscale_config_pmc;
|
|
pcd->pcd_pcpu_fini = xscale_pcpu_fini;
|
|
pcd->pcd_pcpu_init = xscale_pcpu_init;
|
|
pcd->pcd_describe = xscale_describe;
|
|
pcd->pcd_get_config = xscale_get_config;
|
|
pcd->pcd_read_pmc = xscale_read_pmc;
|
|
pcd->pcd_release_pmc = xscale_release_pmc;
|
|
pcd->pcd_start_pmc = xscale_start_pmc;
|
|
pcd->pcd_stop_pmc = xscale_stop_pmc;
|
|
pcd->pcd_write_pmc = xscale_write_pmc;
|
|
|
|
pmc_mdep->pmd_intr = xscale_intr;
|
|
pmc_mdep->pmd_switch_in = xscale_switch_in;
|
|
pmc_mdep->pmd_switch_out = xscale_switch_out;
|
|
|
|
pmc_mdep->pmd_npmc += xscale_npmcs;
|
|
|
|
return (pmc_mdep);
|
|
}
|
|
|
|
void
|
|
pmc_xscale_finalize(struct pmc_mdep *md)
|
|
{
|
|
}
|