3c1bfadaf9
They are valid as of the ARMv8.7 XML. While here switch to use shifted values as they are easier to compare with values in the Arm Reference Manual. Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D31093
205 lines
7.9 KiB
C
205 lines
7.9 KiB
C
/*-
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* Copyright (c) 2013, 2014 Andrew Turner
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* Copyright (c) 2021 The FreeBSD Foundation
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*
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* Portions of this software were developed by Andrew Turner
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* under sponsorship from the FreeBSD Foundation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_HYPERVISOR_H_
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#define _MACHINE_HYPERVISOR_H_
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/*
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* These registers are only useful when in hypervisor context,
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* e.g. specific to EL2, or controlling the hypervisor.
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*/
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/* CNTHCTL_EL2 - Counter-timer Hypervisor Control register */
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#define CNTHCTL_EVNTI_MASK (0xf << 4) /* Bit to trigger event stream */
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#define CNTHCTL_EVNTDIR (1 << 3) /* Control transition trigger bit */
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#define CNTHCTL_EVNTEN (1 << 2) /* Enable event stream */
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#define CNTHCTL_EL1PCEN (1 << 1) /* Allow EL0/1 physical timer access */
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#define CNTHCTL_EL1PCTEN (1 << 0) /*Allow EL0/1 physical counter access*/
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/* CPTR_EL2 - Architecture feature trap register */
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#define CPTR_RES0 0x7fefc800
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#define CPTR_RES1 0x000033ff
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#define CPTR_TFP 0x00000400
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#define CPTR_TTA 0x00100000
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#define CPTR_TCPAC 0x80000000
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/* HCR_EL2 - Hypervisor Config Register */
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#define HCR_VM (UL(0x1) << 0)
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#define HCR_SWIO (UL(0x1) << 1)
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#define HCR_PTW (UL(0x1) << 2)
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#define HCR_FMO (UL(0x1) << 3)
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#define HCR_IMO (UL(0x1) << 4)
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#define HCR_AMO (UL(0x1) << 5)
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#define HCR_VF (UL(0x1) << 6)
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#define HCR_VI (UL(0x1) << 7)
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#define HCR_VSE (UL(0x1) << 8)
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#define HCR_FB (UL(0x1) << 9)
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#define HCR_BSU_MASK (UL(0x3) << 10)
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#define HCR_BSU_IS (UL(0x1) << 10)
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#define HCR_BSU_OS (UL(0x2) << 10)
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#define HCR_BSU_FS (UL(0x3) << 10)
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#define HCR_DC (UL(0x1) << 12)
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#define HCR_TWI (UL(0x1) << 13)
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#define HCR_TWE (UL(0x1) << 14)
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#define HCR_TID0 (UL(0x1) << 15)
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#define HCR_TID1 (UL(0x1) << 16)
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#define HCR_TID2 (UL(0x1) << 17)
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#define HCR_TID3 (UL(0x1) << 18)
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#define HCR_TSC (UL(0x1) << 19)
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#define HCR_TIDCP (UL(0x1) << 20)
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#define HCR_TACR (UL(0x1) << 21)
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#define HCR_TSW (UL(0x1) << 22)
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#define HCR_TPCP (UL(0x1) << 23)
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#define HCR_TPU (UL(0x1) << 24)
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#define HCR_TTLB (UL(0x1) << 25)
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#define HCR_TVM (UL(0x1) << 26)
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#define HCR_TGE (UL(0x1) << 27)
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#define HCR_TDZ (UL(0x1) << 28)
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#define HCR_HCD (UL(0x1) << 29)
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#define HCR_TRVM (UL(0x1) << 30)
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#define HCR_RW (UL(0x1) << 31)
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#define HCR_CD (UL(0x1) << 32)
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#define HCR_ID (UL(0x1) << 33)
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#define HCR_E2H (UL(0x1) << 34)
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#define HCR_TLOR (UL(0x1) << 35)
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#define HCR_TERR (UL(0x1) << 36)
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#define HCR_TEA (UL(0x1) << 37)
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#define HCR_MIOCNCE (UL(0x1) << 38)
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/* Bit 39 is reserved */
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#define HCR_APK (UL(0x1) << 40)
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#define HCR_API (UL(0x1) << 41)
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#define HCR_NV (UL(0x1) << 42)
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#define HCR_NV1 (UL(0x1) << 43)
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#define HCR_AT (UL(0x1) << 44)
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#define HCR_NV2 (UL(0x1) << 45)
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#define HCR_FWB (UL(0x1) << 46)
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#define HCR_FIEN (UL(0x1) << 47)
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/* Bit 48 is reserved */
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#define HCR_TID4 (UL(0x1) << 49)
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#define HCR_TICAB (UL(0x1) << 50)
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#define HCR_AMVOFFEN (UL(0x1) << 51)
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#define HCR_TOCU (UL(0x1) << 52)
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#define HCR_EnSCXT (UL(0x1) << 53)
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#define HCR_TTLBIS (UL(0x1) << 54)
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#define HCR_TTLBOS (UL(0x1) << 55)
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#define HCR_ATA (UL(0x1) << 56)
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#define HCR_DCT (UL(0x1) << 57)
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#define HCR_TID5 (UL(0x1) << 58)
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#define HCR_TWEDEn (UL(0x1) << 59)
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#define HCR_TWEDEL_MASK (UL(0xf) << 60)
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/* HPFAR_EL2 - Hypervisor IPA Fault Address Register */
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#define HPFAR_EL2_FIPA_SHIFT 4
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#define HPFAR_EL2_FIPA_MASK 0xfffffffff0
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/* ICC_SRE_EL2 */
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#define ICC_SRE_EL2_SRE (1U << 0)
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#define ICC_SRE_EL2_EN (1U << 3)
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/* SCTLR_EL2 - System Control Register */
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#define SCTLR_EL2_RES1 0x30c50830
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#define SCTLR_EL2_M_SHIFT 0
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#define SCTLR_EL2_M (0x1 << SCTLR_EL2_M_SHIFT)
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#define SCTLR_EL2_A_SHIFT 1
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#define SCTLR_EL2_A (0x1 << SCTLR_EL2_A_SHIFT)
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#define SCTLR_EL2_C_SHIFT 2
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#define SCTLR_EL2_C (0x1 << SCTLR_EL2_C_SHIFT)
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#define SCTLR_EL2_SA_SHIFT 3
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#define SCTLR_EL2_SA (0x1 << SCTLR_EL2_SA_SHIFT)
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#define SCTLR_EL2_I_SHIFT 12
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#define SCTLR_EL2_I (0x1 << SCTLR_EL2_I_SHIFT)
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#define SCTLR_EL2_WXN_SHIFT 19
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#define SCTLR_EL2_WXN (0x1 << SCTLR_EL2_WXN_SHIFT)
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#define SCTLR_EL2_EE_SHIFT 25
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#define SCTLR_EL2_EE (0x1 << SCTLR_EL2_EE_SHIFT)
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/* TCR_EL2 - Translation Control Register */
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#define TCR_EL2_RES1 ((0x1UL << 31) | (0x1UL << 23))
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#define TCR_EL2_T0SZ_SHIFT 0
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#define TCR_EL2_T0SZ_MASK (0x3f << TCR_EL2_T0SZ_SHIFT)
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#define TCR_EL2_T0SZ(x) ((x) << TCR_EL2_T0SZ_SHIFT)
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/* Bits 7:6 are reserved */
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#define TCR_EL2_IRGN0_SHIFT 8
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#define TCR_EL2_IRGN0_MASK (0x3 << TCR_EL2_IRGN0_SHIFT)
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#define TCR_EL2_ORGN0_SHIFT 10
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#define TCR_EL2_ORGN0_MASK (0x3 << TCR_EL2_ORGN0_SHIFT)
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#define TCR_EL2_SH0_SHIFT 12
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#define TCR_EL2_SH0_MASK (0x3 << TCR_EL2_SH0_SHIFT)
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#define TCR_EL2_TG0_SHIFT 14
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#define TCR_EL2_TG0_MASK (0x3 << TCR_EL2_TG0_SHIFT)
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#define TCR_EL2_PS_SHIFT 16
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#define TCR_EL2_PS_32BITS (0 << TCR_EL2_PS_SHIFT)
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#define TCR_EL2_PS_36BITS (1 << TCR_EL2_PS_SHIFT)
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#define TCR_EL2_PS_40BITS (2 << TCR_EL2_PS_SHIFT)
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#define TCR_EL2_PS_42BITS (3 << TCR_EL2_PS_SHIFT)
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#define TCR_EL2_PS_44BITS (4 << TCR_EL2_PS_SHIFT)
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#define TCR_EL2_PS_48BITS (5 << TCR_EL2_PS_SHIFT)
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#define TCR_EL2_PS_52BITS (6 << TCR_EL2_PS_SHIFT) /* ARMv8.2-LPA */
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/* VMPDIR_EL2 - Virtualization Multiprocessor ID Register */
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#define VMPIDR_EL2_U 0x0000000040000000
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#define VMPIDR_EL2_MT 0x0000000001000000
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#define VMPIDR_EL2_RES1 0x0000000080000000
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/* VTCR_EL2 - Virtualization Translation Control Register */
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#define VTCR_EL2_RES1 (0x1 << 31)
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#define VTCR_EL2_T0SZ_MASK 0x3f
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#define VTCR_EL2_SL0_SHIFT 6
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#define VTCR_EL2_SL0_4K_LVL2 (0x0 << VTCR_EL2_SL0_SHIFT)
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#define VTCR_EL2_SL0_4K_LVL1 (0x1 << VTCR_EL2_SL0_SHIFT)
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#define VTCR_EL2_SL0_4K_LVL0 (0x2 << VTCR_EL2_SL0_SHIFT)
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#define VTCR_EL2_IRGN0_SHIFT 8
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#define VTCR_EL2_IRGN0_WBWA (0x1 << VTCR_EL2_IRGN0_SHIFT)
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#define VTCR_EL2_ORGN0_SHIFT 10
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#define VTCR_EL2_ORGN0_WBWA (0x1 << VTCR_EL2_ORGN0_SHIFT)
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#define VTCR_EL2_SH0_SHIFT 12
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#define VTCR_EL2_SH0_NS (0x0 << VTCR_EL2_SH0_SHIFT)
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#define VTCR_EL2_SH0_OS (0x2 << VTCR_EL2_SH0_SHIFT)
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#define VTCR_EL2_SH0_IS (0x3 << VTCR_EL2_SH0_SHIFT)
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#define VTCR_EL2_TG0_SHIFT 14
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#define VTCR_EL2_TG0_4K (0x0 << VTCR_EL2_TG0_SHIFT)
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#define VTCR_EL2_TG0_64K (0x1 << VTCR_EL2_TG0_SHIFT)
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#define VTCR_EL2_TG0_16K (0x2 << VTCR_EL2_TG0_SHIFT)
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#define VTCR_EL2_PS_SHIFT 16
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#define VTCR_EL2_PS_32BIT (0x0 << VTCR_EL2_PS_SHIFT)
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#define VTCR_EL2_PS_36BIT (0x1 << VTCR_EL2_PS_SHIFT)
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#define VTCR_EL2_PS_40BIT (0x2 << VTCR_EL2_PS_SHIFT)
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#define VTCR_EL2_PS_42BIT (0x3 << VTCR_EL2_PS_SHIFT)
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#define VTCR_EL2_PS_44BIT (0x4 << VTCR_EL2_PS_SHIFT)
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#define VTCR_EL2_PS_48BIT (0x5 << VTCR_EL2_PS_SHIFT)
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/* VTTBR_EL2 - Virtualization Translation Table Base Register */
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#define VTTBR_VMID_MASK 0xffff000000000000
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#define VTTBR_VMID_SHIFT 48
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#define VTTBR_HOST 0x0000000000000000
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#endif /* !_MACHINE_HYPERVISOR_H_ */
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