e67f80fd20
o ixp425 support o NPE network driver (requires Intel microcode) o h/w qmgr support o True IDE compact flash over expansion bus o pci (ath and hifn795x parts tested) o xscale watchdog timer o ds1672 RTC on i2c bus o ad7418 voltage + temp monitoring on i2c bus o uart Work done together with cognet, kevlo, and jmg. Parts of the ixp425 support obtaine/derived from netbsd. Reviewed by: cognet, imp MFC after: 1 month
289 lines
11 KiB
C
289 lines
11 KiB
C
/*-
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* Copyright (c) 2006 Sam Leffler, Errno Consulting
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce at minimum a disclaimer
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* similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
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* redistribution must be conditioned upon including a substantially
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* similar Disclaimer requirement for further binary redistribution.
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*
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* NO WARRANTY
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
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* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
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* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
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* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGES.
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*
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* $FreeBSD$
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*/
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/*
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* Copyright (c) 2001-2005, Intel Corporation.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Intel Corporation nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef ARM_XSCALE_IF_NPEREG_H
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#define ARM_XSCALE_IF_NPEREG_H
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/*
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* NPE/NPE tx/rx descriptor format. This is just the area
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* shared with ucode running in the NPE; the driver-specific
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* state is defined in the driver. The shared area must be
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* cacheline-aligned. We allocate NPE_MAXSEG "descriptors"
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* per buffer; this allows us to do minimal s/g. The number
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* of descriptors can be expanded but doing so uses memory
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* so should be done with care.
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*
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* The driver sets up buffers in uncached memory.
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*/
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#define NPE_MAXSEG 3 /* empirically selected */
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struct npehwbuf {
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struct { /* NPE shared area, cacheline aligned */
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uint32_t next; /* phys addr of next segment */
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uint32_t len; /* buffer/segment length (bytes) */
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uint32_t data; /* phys addr of data segment */
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uint32_t pad[5]; /* pad to cacheline */
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} ix_ne[NPE_MAXSEG];
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};
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/* NPE ID's */
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#define NPE_A 0
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#define NPE_B 1
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#define NPE_C 2
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#define NPE_MAX (NPE_C+1)
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#define NPE_PORTS_MAX 2 /* logical ports */
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#define NPE_FRAME_SIZE_DEFAULT 1536
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#define NPE_FRAME_SIZE_MAX (65536-64)
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#define NPE_FRAME_SIZE_MIN 64
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/*
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* Queue Manager-related definitions.
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*
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* These define the layout of 32-bit Q entries passed
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* between the host cpu and the NPE's.
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*/
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#define NPE_QM_Q_NPE(e) (((e)>>0)&0x3) /* NPE ID */
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#define NPE_QM_Q_PORT(e) (((e)>>3)&0x1) /* Port ID */
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#define NPE_QM_Q_PRIO(e) (((e)>>0)&0x3) /* 802.1d priority */
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#define NPE_QM_Q_ADDR(e) ((e)&0xfffffffe0) /* phys address */
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/*
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* Host->NPE requests written to the shared mailbox.
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* The NPE writes the same value back as an ACK.
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*/
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#define NPE_GETSTATUS 0x00 /* get firmware revision */
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#define NPE_SETPORTADDRESS 0x01 /* set port id and mac address */
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#define NPE_GETMACADDRDB 0x02 /* upload filter database */
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#define NPE_SETMACADDRDB 0x03 /* download filter database */
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#define NPE_GETSTATS 0x04 /* get statistics */
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#define NPE_RESETSTATS 0x05 /* reset stats + return result */
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#define NPE_SETMAXFRAME 0x06 /* configure max tx/rx frame lengths */
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#define NPE_SETRXTAGMODE 0x07 /* configure VLAN rx operating mode */
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#define NPE_SETDEFRXVID 0x08 /* set def VLAN tag + traffic class */
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#define NPE_SETRXQOSENTRY 0x0b /* map user pri -> QoS class+rx qid */
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#define NPE_SETFIREWALLMODE 0x0e /* config firewall services */
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#define NPE_SETLOOPBACK 0x12 /* enable/disable loopback */
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/* ... XXX more */
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#define NPE_MAC_MSGID_SHL 24
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#define NPE_MAC_PORTID_SHL 16
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/*
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* MAC register definitions; see section
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* 15.2 of the Intel Developers Manual.
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*/
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#define NPE_MAC_TX_CNTRL1 0x000
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#define NPE_MAC_TX_CNTRL2 0x004
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#define NPE_MAC_RX_CNTRL1 0x010
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#define NPE_MAC_RX_CNTRL2 0x014
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#define NPE_MAC_RANDOM_SEED 0x020
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#define NPE_MAC_THRESH_P_EMPTY 0x030
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#define NPE_MAC_THRESH_P_FULL 0x038
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#define NPE_MAC_BUF_SIZE_TX 0x040
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#define NPE_MAC_TX_DEFER 0x050
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#define NPE_MAC_RX_DEFER 0x054
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#define NPE_MAC_TX_TWO_DEFER_1 0x060
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#define NPE_MAC_TX_TWO_DEFER_2 0x064
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#define NPE_MAC_SLOT_TIME 0x070
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#define NPE_MAC_MDIO_CMD_1 0x080
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#define NPE_MAC_MDIO_CMD_2 0x084
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#define NPE_MAC_MDIO_CMD_3 0x088
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#define NPE_MAC_MDIO_CMD_4 0x08c
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#define NPE_MAC_MDIO_STS_1 0x090
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#define NPE_MAC_MDIO_STS_2 0x094
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#define NPE_MAC_MDIO_STS_3 0x098
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#define NPE_MAC_MDIO_STS_4 0x09c
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#define NPE_MAC_ADDR_MASK_1 0x0A0
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#define NPE_MAC_ADDR_MASK_2 0x0A4
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#define NPE_MAC_ADDR_MASK_3 0x0A8
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#define NPE_MAC_ADDR_MASK_4 0x0AC
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#define NPE_MAC_ADDR_MASK_5 0x0B0
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#define NPE_MAC_ADDR_MASK_6 0x0B4
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#define NPE_MAC_ADDR_1 0x0C0
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#define NPE_MAC_ADDR_2 0x0C4
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#define NPE_MAC_ADDR_3 0x0C8
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#define NPE_MAC_ADDR_4 0x0CC
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#define NPE_MAC_ADDR_5 0x0D0
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#define NPE_MAC_ADDR_6 0x0D4
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#define NPE_MAC_INT_CLK_THRESH 0x0E0
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#define NPE_MAC_UNI_ADDR_1 0x0F0
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#define NPE_MAC_UNI_ADDR_2 0x0F4
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#define NPE_MAC_UNI_ADDR_3 0x0F8
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#define NPE_MAC_UNI_ADDR_4 0x0FC
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#define NPE_MAC_UNI_ADDR_5 0x100
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#define NPE_MAC_UNI_ADDR_6 0x104
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#define NPE_MAC_CORE_CNTRL 0x1FC
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#define NPE_MAC_ADDR_MASK(i) (NPE_MAC_ADDR_MASK_1 + ((i)<<2))
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#define NPE_MAC_ADDR(i) (NPE_MAC_ADDR_1 + ((i)<<2))
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#define NPE_MAC_UNI_ADDR(i) (NPE_MAC_UNI_ADDR_1 + ((i)<<2))
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/*
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* Bit definitions
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*/
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/* TX Control Register 1*/
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#define NPE_TX_CNTRL1_TX_EN 0x01 /* enable TX engine */
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#define NPE_TX_CNTRL1_DUPLEX 0x02 /* select half duplex */
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#define NPE_TX_CNTRL1_RETRY 0x04 /* auto-retry on collision */
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#define NPE_TX_CNTRL1_PAD_EN 0x08 /* pad frames <64 bytes */
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#define NPE_TX_CNTRL1_FCS_EN 0x10 /* append FCS */
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#define NPE_TX_CNTRL1_2DEFER 0x20 /* select 2-part deferral */
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#define NPE_TX_CNTRL1_RMII 0x40
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/* TX Control Register 2 */
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#define NPE_TX_CNTRL2_RETRIES_MASK 0xf /* max retry count */
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/* RX Control Register 1 */
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#define NPE_RX_CNTRL1_RX_EN 0x01 /* enable RX engine */
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#define NPE_RX_CNTRL1_PADSTRIP_EN 0x02 /* strip frame padding */
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#define NPE_RX_CNTRL1_CRC_EN 0x04 /* include CRC in RX frame */
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#define NPE_RX_CNTRL1_PAUSE_EN 0x08 /* detect Pause frames */
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#define NPE_RX_CNTRL1_LOOP_EN 0x10 /* loopback tx/rx */
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#define NPE_RX_CNTRL1_ADDR_FLTR_EN 0x20 /* enable address filtering */
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#define NPE_RX_CNTRL1_RX_RUNT_EN 0x40 /* enable RX of runt frames */
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#define NPE_RX_CNTRL1_BCAST_DIS 0x80 /* discard broadcast frames */
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/* RX Control Register 2 */
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#define NPE_RX_CNTRL2_DEFER_EN 0x01
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/* Core Control Register */
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#define NPE_CORE_RESET 0x01 /* MAC reset state */
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#define NPE_CORE_RX_FIFO_FLUSH 0x02 /* flush RX FIFO */
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#define NPE_CORE_TX_FIFO_FLUSH 0x04 /* flush TX FIFO */
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#define NPE_CORE_SEND_JAM 0x08 /* send JAM on packet RX */
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#define NPE_CORE_MDC_EN 0x10 /* IXP42X drives MDC clock */
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/*
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* Stat block returned by NPE with NPE_GETSTATS msg.
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*/
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struct npestats {
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uint32_t dot3StatsAlignmentErrors;
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uint32_t dot3StatsFCSErrors;
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uint32_t dot3StatsInternalMacReceiveErrors;
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uint32_t RxOverrunDiscards;
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uint32_t RxLearnedEntryDiscards;
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uint32_t RxLargeFramesDiscards;
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uint32_t RxSTPBlockedDiscards;
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uint32_t RxVLANTypeFilterDiscards;
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uint32_t RxVLANIdFilterDiscards;
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uint32_t RxInvalidSourceDiscards;
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uint32_t RxBlackListDiscards;
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uint32_t RxWhiteListDiscards;
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uint32_t RxUnderflowEntryDiscards;
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uint32_t dot3StatsSingleCollisionFrames;
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uint32_t dot3StatsMultipleCollisionFrames;
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uint32_t dot3StatsDeferredTransmissions;
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uint32_t dot3StatsLateCollisions;
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uint32_t dot3StatsExcessiveCollisions;
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uint32_t dot3StatsInternalMacTransmitErrors;
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uint32_t dot3StatsCarrierSenseErrors;
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uint32_t TxLargeFrameDiscards;
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uint32_t TxVLANIdFilterDiscards;
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};
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/*
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* Default values
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*/
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#define NPE_MAC_INT_CLK_THRESH_DEFAULT 0x1
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#define NPE_MAC_RESET_DELAY 1
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/* This value applies to RMII */
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#define NPE_MAC_SLOT_TIME_RMII_DEFAULT 0xFF
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/*
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* MII definitions - these have been verified against the LXT971 and LXT972 PHYs
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*/
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#define NPE_MII_REG_SHL 16
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#define NPE_MII_ADDR_SHL 21
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/* NB: shorthands for mii bus mdio routines */
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#define NPE_MAC_MDIO_CMD NPE_MAC_MDIO_CMD_1
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#define NPE_MAC_MDIO_STS NPE_MAC_MDIO_STS_1
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#define NPE_MII_GO (1<<31)
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#define NPE_MII_WRITE (1<<26)
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#define NPE_MII_TIMEOUT_10TH_SECS 5
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#define NPE_MII_10TH_SEC_IN_MILLIS 100
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#define NPE_MII_READ_FAIL (1<<31)
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#define NPE_MII_PHY_DEF_DELAY 300 /* max delay before link up, etc. */
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#define NPE_MII_PHY_NO_DELAY 0x0 /* do not delay */
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#define NPE_MII_PHY_NULL 0xff /* PHY is not present */
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#define NPE_MII_PHY_DEF_ADDR 0x0 /* default PHY's logical address */
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/* Register definition */
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#define NPE_MII_CTRL_REG 0x0 /* Control Register */
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#define NPE_MII_STAT_REG 0x1 /* Status Register */
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#define NPE_MII_PHY_ID1_REG 0x2 /* PHY identifier 1 Register */
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#define NPE_MII_PHY_ID2_REG 0x3 /* PHY identifier 2 Register */
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#define NPE_MII_AN_ADS_REG 0x4 /* Auto-Negotiation */
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/* Advertisement Register */
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#define NPE_MII_AN_PRTN_REG 0x5 /* Auto-Negotiation */
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/* partner ability Register */
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#define NPE_MII_AN_EXP_REG 0x6 /* Auto-Negotiation */
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/* Expansion Register */
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#define NPE_MII_AN_NEXT_REG 0x7 /* Auto-Negotiation */
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/* next-page transmit Register */
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#endif /* ARM_XSCALE_IF_NPEREG_H */
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