f4c01f1508
ARM_TP_ADDRESS, where the tp will be stored. On CPUs that support it, a cache line will be allocated and locked for this address, so that it will never go to RAM. On CPUs that does not, a page is allocated for it (it will be a bit slower, and is wrong for SMP, but should be fine for UP). The tp is still stored in the mdthread struct, and at each context switch, ARM_TP_ADDRESS gets updated. Suggested by: davidxu
6 lines
142 B
Plaintext
6 lines
142 B
Plaintext
#XScale i80321 generic configuration
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#$FreeBSD$
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files "../xscale/i80321/files.i80321"
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include "../xscale/std.xscale"
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cpu CPU_XSCALE_80321
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