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o Chip full mask revision 2 or later controllers have to set correct Tx MAC and Tx offload clock depending on negotiated link speed. o JMC260 chip full mask revision 2 has a silicon bug that can't handle 64bit DMA addressing. Add workaround to the bug by limiting DMA address space to be within 32bit. o Valid FIFO space of receive control and status register was changed on chip full mask revision 2 or later controllers. For these controllers, use default 16QW as it's supposed to be the safest value for maximum PCIe compatibility. JMicron confirmed performance will not be reduced even if the FIFO space is set to 16QW. o When interface is put into suspend/shutdown state, remove Tx MAC and Tx offload clock to save more power. We don't need Tx clock at all in this state. o Added new register definition for chip full mask revision 2 or later controllers. Thanks to JMicron for their continuous support of FreeBSD.
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