f3b63bd388
goes after the npx/apm devices and any other motherboard devices that may get added down the track.
496 lines
12 KiB
C
496 lines
12 KiB
C
/*
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* Copyright (c) 1997, Stefan Esser <se@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $Id: pcibus.c,v 1.46 1999/08/10 09:22:21 peter Exp $
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*
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <pci/pcivar.h>
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#include <pci/pcireg.h>
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#include <i386/isa/pcibus.h>
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#ifdef PCI_COMPAT
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/* XXX this is a terrible hack, which keeps the Tekram AMD SCSI driver happy */
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#define cfgmech pci_mechanism
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int cfgmech;
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#else
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static int cfgmech;
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#endif /* PCI_COMPAT */
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static int devmax;
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/* enable configuration space accesses and return data port address */
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static int
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pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
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{
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int dataport = 0;
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if (bus <= PCI_BUSMAX
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&& slot < devmax
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&& func <= PCI_FUNCMAX
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&& reg <= PCI_REGMAX
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&& bytes != 3
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&& (unsigned) bytes <= 4
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&& (reg & (bytes -1)) == 0) {
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switch (cfgmech) {
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case 1:
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outl(CONF1_ADDR_PORT, (1 << 31)
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| (bus << 16) | (slot << 11)
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| (func << 8) | (reg & ~0x03));
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dataport = CONF1_DATA_PORT + (reg & 0x03);
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break;
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case 2:
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outb(CONF2_ENABLE_PORT, 0xf0 | (func << 1));
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outb(CONF2_FORWARD_PORT, bus);
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dataport = 0xc000 | (slot << 8) | reg;
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break;
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}
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}
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return (dataport);
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}
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/* disable configuration space accesses */
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static void
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pci_cfgdisable(void)
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{
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switch (cfgmech) {
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case 1:
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outl(CONF1_ADDR_PORT, 0);
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break;
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case 2:
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outb(CONF2_ENABLE_PORT, 0);
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outb(CONF2_FORWARD_PORT, 0);
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break;
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}
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}
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/* read configuration space register */
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int
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pci_cfgread(pcicfgregs *cfg, int reg, int bytes)
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{
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int data = -1;
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int port;
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port = pci_cfgenable(cfg->bus, cfg->slot, cfg->func, reg, bytes);
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if (port != 0) {
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switch (bytes) {
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case 1:
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data = inb(port);
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break;
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case 2:
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data = inw(port);
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break;
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case 4:
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data = inl(port);
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break;
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}
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pci_cfgdisable();
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}
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return (data);
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}
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/* write configuration space register */
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void
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pci_cfgwrite(pcicfgregs *cfg, int reg, int data, int bytes)
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{
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int port;
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port = pci_cfgenable(cfg->bus, cfg->slot, cfg->func, reg, bytes);
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if (port != 0) {
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switch (bytes) {
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case 1:
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outb(port, data);
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break;
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case 2:
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outw(port, data);
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break;
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case 4:
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outl(port, data);
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break;
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}
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pci_cfgdisable();
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}
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}
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/* check whether the configuration mechanism has been correct identified */
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static int
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pci_cfgcheck(int maxdev)
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{
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u_char device;
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if (bootverbose)
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printf("pci_cfgcheck:\tdevice ");
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for (device = 0; device < maxdev; device++) {
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unsigned id, class, header;
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if (bootverbose)
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printf("%d ", device);
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id = inl(pci_cfgenable(0, device, 0, 0, 4));
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if (id == 0 || id == -1)
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continue;
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class = inl(pci_cfgenable(0, device, 0, 8, 4)) >> 8;
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if (bootverbose)
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printf("[class=%06x] ", class);
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if (class == 0 || (class & 0xf870ff) != 0)
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continue;
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header = inb(pci_cfgenable(0, device, 0, 14, 1));
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if (bootverbose)
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printf("[hdr=%02x] ", header);
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if ((header & 0x7e) != 0)
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continue;
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if (bootverbose)
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printf("is there (id=%08x)\n", id);
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pci_cfgdisable();
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return (1);
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}
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if (bootverbose)
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printf("-- nothing found\n");
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pci_cfgdisable();
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return (0);
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}
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static int
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pci_cfgopen(void)
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{
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unsigned long mode1res,oldval1;
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unsigned char mode2res,oldval2;
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oldval1 = inl(CONF1_ADDR_PORT);
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if (bootverbose) {
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printf("pci_open(1):\tmode 1 addr port (0x0cf8) is 0x%08lx\n",
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oldval1);
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}
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if ((oldval1 & CONF1_ENABLE_MSK) == 0) {
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cfgmech = 1;
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devmax = 32;
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outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK);
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outb(CONF1_ADDR_PORT +3, 0);
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mode1res = inl(CONF1_ADDR_PORT);
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outl(CONF1_ADDR_PORT, oldval1);
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if (bootverbose)
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printf("pci_open(1a):\tmode1res=0x%08lx (0x%08lx)\n",
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mode1res, CONF1_ENABLE_CHK);
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if (mode1res) {
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if (pci_cfgcheck(32))
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return (cfgmech);
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}
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outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK1);
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mode1res = inl(CONF1_ADDR_PORT);
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outl(CONF1_ADDR_PORT, oldval1);
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if (bootverbose)
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printf("pci_open(1b):\tmode1res=0x%08lx (0x%08lx)\n",
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mode1res, CONF1_ENABLE_CHK1);
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if ((mode1res & CONF1_ENABLE_MSK1) == CONF1_ENABLE_RES1) {
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if (pci_cfgcheck(32))
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return (cfgmech);
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}
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}
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oldval2 = inb(CONF2_ENABLE_PORT);
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if (bootverbose) {
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printf("pci_open(2):\tmode 2 enable port (0x0cf8) is 0x%02x\n",
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oldval2);
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}
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if ((oldval2 & 0xf0) == 0) {
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cfgmech = 2;
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devmax = 16;
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outb(CONF2_ENABLE_PORT, CONF2_ENABLE_CHK);
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mode2res = inb(CONF2_ENABLE_PORT);
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outb(CONF2_ENABLE_PORT, oldval2);
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if (bootverbose)
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printf("pci_open(2a):\tmode2res=0x%02x (0x%02x)\n",
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mode2res, CONF2_ENABLE_CHK);
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if (mode2res == CONF2_ENABLE_RES) {
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if (bootverbose)
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printf("pci_open(2a):\tnow trying mechanism 2\n");
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if (pci_cfgcheck(16))
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return (cfgmech);
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}
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}
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cfgmech = 0;
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devmax = 0;
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return (cfgmech);
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}
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static devclass_t pcib_devclass;
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static const char *
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nexus_pcib_is_host_bridge(pcicfgregs *cfg,
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u_int32_t id, u_int8_t class, u_int8_t subclass,
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u_int8_t *busnum)
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{
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const char *s = NULL;
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static u_int8_t pxb[4]; /* hack for 450nx */
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*busnum = 0;
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switch (id) {
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case 0x12258086:
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s = "Intel 824?? host to PCI bridge";
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/* XXX This is a guess */
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*busnum = pci_cfgread(cfg, 0x41, 1);
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break;
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case 0x71808086:
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s = "Intel 82443LX (440 LX) host to PCI bridge";
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break;
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case 0x71908086:
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s = "Intel 82443BX (440 BX) host to PCI bridge";
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break;
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case 0x71928086:
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s = "Intel 82443BX host to PCI bridge (AGP disabled)";
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break;
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case 0x71a08086:
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s = "Intel 82443GX host to PCI bridge";
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break;
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case 0x71a18086:
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s = "Intel 82443GX host to AGP bridge";
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break;
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case 0x71a28086:
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s = "Intel 82443GX host to PCI bridge (AGP disabled)";
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break;
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case 0x84c48086:
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s = "Intel 82454KX/GX (Orion) host to PCI bridge";
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*busnum = pci_cfgread(cfg, 0x4a, 1);
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break;
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case 0x84ca8086:
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/*
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* For the 450nx chipset, there is a whole bundle of
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* things pretending to be host bridges. The MIOC will
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* be seen first and isn't really a pci bridge (the
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* actual busses are attached to the PXB's). We need to
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* read the registers of the MIOC to figure out the
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* bus numbers for the PXB channels.
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*
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* Since the MIOC doesn't have a pci bus attached, we
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* pretend it wasn't there.
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*/
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pxb[0] = pci_cfgread(cfg, 0xd0, 1); /* BUSNO[0] */
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pxb[1] = pci_cfgread(cfg, 0xd1, 1) + 1; /* SUBA[0]+1 */
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pxb[2] = pci_cfgread(cfg, 0xd3, 1); /* BUSNO[1] */
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pxb[3] = pci_cfgread(cfg, 0xd4, 1) + 1; /* SUBA[1]+1 */
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return NULL;
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case 0x84cb8086:
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switch (cfg->slot) {
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case 0x12:
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s = "Intel 82454NX PXB#0, Bus#A";
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*busnum = pxb[0];
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break;
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case 0x13:
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s = "Intel 82454NX PXB#0, Bus#B";
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*busnum = pxb[1];
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break;
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case 0x14:
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s = "Intel 82454NX PXB#1, Bus#A";
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*busnum = pxb[2];
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break;
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case 0x15:
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s = "Intel 82454NX PXB#1, Bus#B";
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*busnum = pxb[3];
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break;
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}
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break;
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/* SiS -- vendor 0x1039 */
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case 0x04961039:
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s = "SiS 85c496";
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break;
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case 0x04061039:
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s = "SiS 85c501";
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break;
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case 0x06011039:
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s = "SiS 85c601";
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break;
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case 0x55911039:
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s = "SiS 5591 host to PCI bridge";
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break;
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case 0x00011039:
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s = "SiS 5591 host to AGP bridge";
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break;
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/* VLSI -- vendor 0x1004 */
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case 0x00051004:
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s = "VLSI 82C592 Host to PCI bridge";
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break;
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/* XXX Here is MVP3, I got the datasheet but NO M/B to test it */
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/* totally. Please let me know if anything wrong. -F */
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/* XXX need info on the MVP3 -- any takers? */
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case 0x05981106:
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s = "VIA 82C598MVP (Apollo MVP3) host bridge";
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break;
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/* AcerLabs -- vendor 0x10b9 */
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/* Funny : The datasheet told me vendor id is "10b8",sub-vendor */
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/* id is '10b9" but the register always shows "10b9". -Foxfair */
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case 0x154110b9:
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s = "AcerLabs M1541 (Aladdin-V) PCI host bridge";
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break;
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/* OPTi -- vendor 0x1045 */
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case 0xc8221045:
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s = "OPTi 82C822 host to PCI Bridge";
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break;
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/* Ross (?) -- vendor 0x1166 */
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case 0x00051166:
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s = "Ross (?) host to PCI bridge";
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/* just guessing the secondary bus register number ... */
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*busnum = pci_cfgread(cfg, 0x45, 1);
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break;
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/* Integrated Micro Solutions -- vendor 0x10e0 */
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case 0x884910e0:
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s = "Integrated Micro Solutions VL Bridge";
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break;
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default:
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if (class == PCIC_BRIDGE && subclass == PCIS_BRIDGE_HOST)
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s = "Host to PCI bridge";
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break;
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}
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return s;
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}
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/*
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* Scan the first pci bus for host-pci bridges and add pcib instances
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* to the nexus for each bridge.
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*/
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static void
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nexus_pcib_identify(driver_t *driver, device_t parent)
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{
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pcicfgregs probe;
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if (pci_cfgopen() == 0)
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return;
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probe.hose = 0;
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probe.bus = 0;
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for (probe.slot = 0; probe.slot <= PCI_SLOTMAX; probe.slot++) {
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int pcifunchigh = 0;
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for (probe.func = 0;
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probe.func <= pcifunchigh;
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probe.func++) {
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/*
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* Read the IDs and class from the device.
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*/
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u_int32_t id;
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u_int8_t class, subclass, busnum;
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device_t child;
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const char *s;
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id = pci_cfgread(&probe, PCIR_DEVVENDOR, 4);
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if (id == -1)
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continue;
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class = pci_cfgread(&probe, PCIR_CLASS, 1);
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subclass = pci_cfgread(&probe, PCIR_SUBCLASS, 1);
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s = nexus_pcib_is_host_bridge(&probe, id,
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class, subclass,
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&busnum);
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if (s) {
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/*
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* Add at priority 100 to make sure we
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* go after any motherboard resources
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*/
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child = BUS_ADD_CHILD(parent, 100,
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"pcib", busnum);
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device_set_desc(child, s);
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}
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}
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}
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}
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static int
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nexus_pcib_probe(device_t dev)
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{
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if (pci_cfgopen() != 0) {
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device_add_child(dev, "pci", device_get_unit(dev), 0);
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return 0;
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}
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return ENXIO;
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}
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static device_method_t nexus_pcib_methods[] = {
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/* Device interface */
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DEVMETHOD(device_identify, nexus_pcib_identify),
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DEVMETHOD(device_probe, nexus_pcib_probe),
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DEVMETHOD(device_attach, bus_generic_attach),
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DEVMETHOD(device_shutdown, bus_generic_shutdown),
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DEVMETHOD(device_suspend, bus_generic_suspend),
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DEVMETHOD(device_resume, bus_generic_resume),
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/* Bus interface */
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DEVMETHOD(bus_print_child, bus_generic_print_child),
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DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource),
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DEVMETHOD(bus_release_resource, bus_generic_release_resource),
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DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
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DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
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DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
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DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
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{ 0, 0 }
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};
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static driver_t nexus_pcib_driver = {
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"pcib",
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nexus_pcib_methods,
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1,
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};
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DRIVER_MODULE(pcib, nexus, nexus_pcib_driver, pcib_devclass, 0, 0);
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