347 lines
9.2 KiB
C
347 lines
9.2 KiB
C
/*-
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* Copyright (c) 2005 Poul-Henning Kamp
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/param.h>
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#include <sys/kernel.h>
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#include <sys/systm.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <machine/stdarg.h>
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#include <sys/rman.h>
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/* vtophys */
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <machine/pmap.h>
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#define UPD7210_HW_DRIVER 1
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#include <dev/ieee488/upd7210.h>
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struct tnt_softc {
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int foo;
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struct upd7210 upd7210;
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struct resource *res[3];
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void *intr_handler;
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};
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static struct resource_spec tnt_res_spec[] = {
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{ SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE},
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{ SYS_RES_MEMORY, PCIR_BAR(1), RF_ACTIVE},
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{ SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE},
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{ -1, 0 }
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};
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enum tnt4882reg {
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dir = 0x00,
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cdor = 0x00,
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isr1 = 0x02,
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imr1 = 0x02,
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isr2 = 0x04,
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imr2 = 0x04,
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accwr = 0x05,
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spsr = 0x06,
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spmr = 0x06,
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intr = 0x07,
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adsr = 0x08,
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admr = 0x08,
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cnt2 = 0x09,
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cptr = 0x0a,
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auxmr = 0x0a,
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tauxcr = 0x0a, /* 9914 mode register */
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cnt3 = 0x0b,
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adr0 = 0x0c,
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adr = 0x0c,
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hssel = 0x0d,
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adr1 = 0x0e,
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eosr = 0x0e,
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sts1 = 0x10,
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cfg = 0x10,
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dsr = 0x11,
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sh_cnt = 0x11,
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imr3 = 0x12,
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hier = 0x13,
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cnt0 = 0x14,
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misc = 0x15,
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cnt1 = 0x16,
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csr = 0x17,
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keyreg = 0x17,
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fifob = 0x18,
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fifoa = 0x19,
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isr3 = 0x1a,
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ccr = 0x1a,
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sasr = 0x1b,
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dcr = 0x1b,
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sts2 = 0x1c,
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cmdr = 0x1c,
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isr0 = 0x1d,
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imr0 = 0x1d,
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timer = 0x1e,
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bsr = 0x1f,
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bcr = 0x1f
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};
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struct tst {
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enum {RD, WT, xDELAY, END}
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action;
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enum tnt4882reg reg;
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uint8_t val;
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};
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/*
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* From NI Application note 095:
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* Writing Functional Self-Tests for the TNT4882 GPIB Interface Chip
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* XXX: fill in the rest ?
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*/
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static struct tst tst_reset[] = {
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{WT, tauxcr, 0x80}, /* chip reset if in 9914 mode */
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{WT, auxmr, 0x80}, /* swrst if swapped */
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{WT, tauxcr, 0x99}, /* switch to 7210 mode */
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{WT, auxmr, 0x99}, /* switch to 7210 mode if swapped */
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{WT, auxmr, 0x02}, /* execute chip reset */
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{WT, keyreg, 0x00}, /* important! clear the swap bit */
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{WT, eosr, 0x00}, /* clear EOS register */
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{WT, cdor, 0x00}, /* clear data lines */
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{WT, imr1, 0x00}, /* disable all interrupts */
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{WT, imr2, 0x00},
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{WT, imr0, 0x80},
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{WT, adr, 0x80},
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{WT, adr, 0x00},
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{WT, admr, 0x00}, /* clear addressing modes */
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{WT, auxmr, 0x00}, /* release from idle state with pon */
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{WT, auxmr, 0x60}, /* reset ppr */
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{WT, bcr, 0x00}, /* reset bcr */
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{WT, misc, 0x04}, /* set wrap plug bit */
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{WT, cmdr, 0xB2}, /* issue soft reset */
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{WT, hssel, 0x00}, /* select two-chip mode */
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{END, 0, 0}
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};
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static struct tst tst_read_reg[] = {
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{RD, isr1, 0x00}, /* Verify mask registers are clear */
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{RD, isr2, 0x00},
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{RD, adsr, 0x40}, /* Verify ATN is not asserted */
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{RD, adr0, 0x00}, /* Verify Primary address not set */
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{RD, adr1, 0x00}, /* Verify Secondary address not set */
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{RD, sts1, 0x8B}, /* Verify DONE, STOP, HALT, and GSYNC set */
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{RD, isr3, 0x19}, /* Verify STOP, Not Full FIFO, & DONE set */
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{RD, sts2, 0x9A}, /* Verify FIFO A/B is empty */
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{RD, sasr, 0x00}, /* Verify clear */
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{RD, isr0, 0x01}, /* Verify SYNC bit is set */
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{END, 0, 0}
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};
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static struct tst tst_bsr_dcr[] = {
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{WT, bcr, 0x55}, /* Set DAV, NRFD, SRQ, and REN */
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{WT, dcr, 0xAA}, /* Write pattern to GPIB data lines */
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{RD, bsr, 0x55}, /* Verify DAV, NRFD, SRQ, and REN are set */
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{RD, dsr, 0xAA}, /* Verify data pattern written previously */
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{WT, bcr, 0xAA}, /* Set ATN, NDAC, EOI, & IFC */
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{WT, dcr, 0x55}, /* Write pattern to GPIB data lines */
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{RD, bsr, 0xAA}, /* Verify ATN, NDAC, EOI, & IFC are set */
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{RD, dsr, 0x55}, /* Verify data pattern written previously */
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{WT, bcr, 0x00}, /* Clear control lines */
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{WT, dcr, 0x00}, /* Clear data lines */
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{RD, bsr, 0x00}, /* Verify control lines are clear */
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{RD, dsr, 0x00}, /* Verify data lines are clear */
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{END, 0, 0}
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};
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static struct tst tst_adr0_1[] = {
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{WT, adr, 0x55}, /* Set Primary talk address */
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{WT, adr, 0xAA}, /* Set Secondary listen address */
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{RD, adr0, 0x55}, /* Read Primary address */
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{RD, adr1, 0x2A}, /* Read Secondary address */
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{WT, adr, 0x2A}, /* Set Primay listen address */
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{WT, adr, 0xD5}, /* Set Secondary talk address */
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{RD, adr0, 0x2A}, /* Read Primary address */
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{RD, adr1, 0x55}, /* Read Secondary address */
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{END, 0, 0}
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};
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static struct tst tst_cdor_dir[] = {
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{WT, admr, 0xF0}, /* program AT-GPIB as talker only and
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* listener only */
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{RD, isr1, 0x02}, /* check DO bit set */
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{RD, adsr, 0x46}, /* check AT-GPIB is both talker active
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* and listener active */
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{WT, cdor, 0xAA}, /* write out data byte */
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{xDELAY, 0, 1}, /* One ISA I/O Cycle (500-ns) */
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{RD, isr1, 0x03}, /* check DO and DI bits set */
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{RD, dir, 0xAA}, /* verify data received */
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{WT, cdor, 0x55}, /* write out data byte */
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{xDELAY, 0, 1}, /* One ISA I/O Cycle (500-ns) */
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{RD, dir, 0x55}, /* verify data received */
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{END, 0, 0}
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};
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static struct tst tst_spmr_spsr[] = {
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{WT, spsr, 0x00}, /* Write pattern to SPSR register */
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{RD, spmr, 0x00}, /* Read back previously written pattern */
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{WT, spsr, 0xBF}, /* Write pattern to SPSR register */
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{RD, spmr, 0xBF}, /* Read back previously written pattern */
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{END, 0, 0}
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};
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static struct tst tst_count0_1[] = {
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{WT, cnt0, 0x55}, /* Verify every other bit can be set */
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{WT, cnt1, 0xAA},
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{RD, cnt0, 0x55}, /* Read back previously written pattern */
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{RD, cnt1, 0xAA},
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{WT, cnt0, 0xAA}, /* Verify every other bit can be set */
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{WT, cnt1, 0x55},
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{RD, cnt0, 0xAA}, /* Read back previously written pattern */
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{RD, cnt1, 0x55},
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{END, 0, 0}
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};
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static int
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tst_exec(struct tnt_softc *sc, struct tst *tp, const char *name)
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{
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uint8_t u;
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int step;
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for (step = 0; tp->action != END; tp++, step++) {
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switch (tp->action) {
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case WT:
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bus_write_1(sc->res[1], tp->reg, tp->val);
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break;
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case RD:
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u = bus_read_1(sc->res[1], tp->reg);
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if (u != tp->val) {
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printf(
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"Test %s, step %d: reg(%02x) = %02x",
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name, step, tp->reg, u);
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printf( "should have been %02x\n", tp->val);
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return (1);
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}
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break;
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case xDELAY:
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DELAY(tp->val);
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break;
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default:
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printf("Unknown action in test %s, step %d: %d\n",
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name, step, tp->action);
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return (1);
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}
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}
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if (bootverbose)
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printf("Test %s passed\n", name);
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return (0);
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}
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static int
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tnt_probe(device_t dev)
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{
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if (pci_get_vendor(dev) == 0x1093 && pci_get_device(dev) == 0xc801) {
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device_set_desc(dev, "NI PCI-GPIB");
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return (BUS_PROBE_DEFAULT);
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}
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return (ENXIO);
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}
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static int
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tnt_attach(device_t dev)
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{
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struct tnt_softc *sc;
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int error, i;
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sc = device_get_softc(dev);
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error = bus_alloc_resources(dev, tnt_res_spec, sc->res);
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if (error)
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return (error);
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error = bus_setup_intr(dev, sc->res[2], INTR_TYPE_MISC | INTR_MPSAFE,
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upd7210intr, &sc->upd7210, &sc->intr_handler);
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/* Necessary magic for MITE */
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bus_write_4(sc->res[0], 0xc0, rman_get_start(sc->res[1]) | 0x80);
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tst_exec(sc, tst_reset, "Reset");
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tst_exec(sc, tst_read_reg, "Read registers");
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tst_exec(sc, tst_bsr_dcr, "BSR & DCR");
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tst_exec(sc, tst_adr0_1, "ADR0,1");
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tst_exec(sc, tst_cdor_dir, "CDOR/DIR");
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tst_exec(sc, tst_spmr_spsr, "CPMR/SPSR");
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tst_exec(sc, tst_count0_1, "COUNT0:1");
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tst_exec(sc, tst_reset, "Reset");
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/* pass 7210 interrupts through */
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bus_write_1(sc->res[1], imr3, 0x02);
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for (i = 0; i < 8; i++) {
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sc->upd7210.reg_res[i] = sc->res[1];
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sc->upd7210.reg_offset[i] = i * 2;
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}
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/* No DMA help */
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sc->upd7210.dmachan = -1;
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upd7210attach(&sc->upd7210);
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return (0);
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}
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static int
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tnt_detach(device_t dev)
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{
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struct tnt_softc *sc;
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sc = device_get_softc(dev);
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bus_teardown_intr(dev, sc->res[2], sc->intr_handler);
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upd7210detach(&sc->upd7210);
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bus_release_resources(dev, tnt_res_spec, sc->res);
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return (0);
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}
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static device_method_t tnt4882_methods[] = {
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DEVMETHOD(device_probe, tnt_probe),
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DEVMETHOD(device_attach, tnt_attach),
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DEVMETHOD(device_detach, tnt_detach),
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{ 0, 0 }
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};
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static driver_t pci_gpib_driver = {
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"tnt4882",
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tnt4882_methods,
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sizeof(struct tnt_softc)
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};
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static devclass_t pci_gpib_devclass;
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DRIVER_MODULE(pci_gpib, pci, pci_gpib_driver, pci_gpib_devclass, 0, 0);
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