950 lines
26 KiB
C
950 lines
26 KiB
C
/* $FreeBSD$ */
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/*-
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* Mailbox and Queue Entry Definitions for for Qlogic ISP SCSI adapters.
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*
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* Copyright (c) 1997, 1998, 1999, 2000 by Matthew Jacob
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice immediately at the beginning of the file, without modification,
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* this list of conditions, and the following disclaimer.
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* 2. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#ifndef _ISPMBOX_H
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#define _ISPMBOX_H
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/*
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* Mailbox Command Opcodes
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*/
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#define MBOX_NO_OP 0x0000
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#define MBOX_LOAD_RAM 0x0001
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#define MBOX_EXEC_FIRMWARE 0x0002
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#define MBOX_DUMP_RAM 0x0003
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#define MBOX_WRITE_RAM_WORD 0x0004
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#define MBOX_READ_RAM_WORD 0x0005
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#define MBOX_MAILBOX_REG_TEST 0x0006
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#define MBOX_VERIFY_CHECKSUM 0x0007
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#define MBOX_ABOUT_FIRMWARE 0x0008
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/* 9 */
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/* a */
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/* b */
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/* c */
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/* d */
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#define MBOX_CHECK_FIRMWARE 0x000e
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#define MBOX_READ_RAM_WORD_EXTENDED 0x000f
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#define MBOX_INIT_REQ_QUEUE 0x0010
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#define MBOX_INIT_RES_QUEUE 0x0011
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#define MBOX_EXECUTE_IOCB 0x0012
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#define MBOX_WAKE_UP 0x0013
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#define MBOX_STOP_FIRMWARE 0x0014
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#define MBOX_ABORT 0x0015
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#define MBOX_ABORT_DEVICE 0x0016
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#define MBOX_ABORT_TARGET 0x0017
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#define MBOX_BUS_RESET 0x0018
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#define MBOX_STOP_QUEUE 0x0019
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#define MBOX_START_QUEUE 0x001a
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#define MBOX_SINGLE_STEP_QUEUE 0x001b
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#define MBOX_ABORT_QUEUE 0x001c
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#define MBOX_GET_DEV_QUEUE_STATUS 0x001d
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/* 1e */
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#define MBOX_GET_FIRMWARE_STATUS 0x001f
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#define MBOX_GET_INIT_SCSI_ID 0x0020
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#define MBOX_GET_SELECT_TIMEOUT 0x0021
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#define MBOX_GET_RETRY_COUNT 0x0022
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#define MBOX_GET_TAG_AGE_LIMIT 0x0023
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#define MBOX_GET_CLOCK_RATE 0x0024
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#define MBOX_GET_ACT_NEG_STATE 0x0025
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#define MBOX_GET_ASYNC_DATA_SETUP_TIME 0x0026
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#define MBOX_GET_SBUS_PARAMS 0x0027
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#define MBOX_GET_PCI_PARAMS MBOX_GET_SBUS_PARAMS
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#define MBOX_GET_TARGET_PARAMS 0x0028
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#define MBOX_GET_DEV_QUEUE_PARAMS 0x0029
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#define MBOX_GET_RESET_DELAY_PARAMS 0x002a
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/* 2b */
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/* 2c */
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/* 2d */
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/* 2e */
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/* 2f */
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#define MBOX_SET_INIT_SCSI_ID 0x0030
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#define MBOX_SET_SELECT_TIMEOUT 0x0031
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#define MBOX_SET_RETRY_COUNT 0x0032
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#define MBOX_SET_TAG_AGE_LIMIT 0x0033
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#define MBOX_SET_CLOCK_RATE 0x0034
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#define MBOX_SET_ACT_NEG_STATE 0x0035
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#define MBOX_SET_ASYNC_DATA_SETUP_TIME 0x0036
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#define MBOX_SET_SBUS_CONTROL_PARAMS 0x0037
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#define MBOX_SET_PCI_PARAMETERS 0x0037
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#define MBOX_SET_TARGET_PARAMS 0x0038
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#define MBOX_SET_DEV_QUEUE_PARAMS 0x0039
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#define MBOX_SET_RESET_DELAY_PARAMS 0x003a
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/* 3b */
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/* 3c */
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/* 3d */
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/* 3e */
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/* 3f */
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#define MBOX_RETURN_BIOS_BLOCK_ADDR 0x0040
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#define MBOX_WRITE_FOUR_RAM_WORDS 0x0041
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#define MBOX_EXEC_BIOS_IOCB 0x0042
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#define MBOX_SET_FW_FEATURES 0x004a
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#define MBOX_GET_FW_FEATURES 0x004b
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#define FW_FEATURE_FAST_POST 0x1
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#define FW_FEATURE_LVD_NOTIFY 0x2
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#define FW_FEATURE_RIO_32BIT 0x4
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#define FW_FEATURE_RIO_16BIT 0x8
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#define MBOX_INIT_REQ_QUEUE_A64 0x0052
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#define MBOX_INIT_RES_QUEUE_A64 0x0053
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#define MBOX_ENABLE_TARGET_MODE 0x0055
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#define ENABLE_TARGET_FLAG 0x8000
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#define ENABLE_TQING_FLAG 0x0004
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#define ENABLE_MANDATORY_DISC 0x0002
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#define MBOX_GET_TARGET_STATUS 0x0056
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/* These are for the ISP2X00 FC cards */
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#define MBOX_GET_LOOP_ID 0x0020
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#define MBOX_GET_FIRMWARE_OPTIONS 0x0028
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#define MBOX_SET_FIRMWARE_OPTIONS 0x0038
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#define MBOX_GET_RESOURCE_COUNT 0x0042
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#define MBOX_ENHANCED_GET_PDB 0x0047
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#define MBOX_EXEC_COMMAND_IOCB_A64 0x0054
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#define MBOX_INIT_FIRMWARE 0x0060
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#define MBOX_GET_INIT_CONTROL_BLOCK 0x0061
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#define MBOX_INIT_LIP 0x0062
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#define MBOX_GET_FC_AL_POSITION_MAP 0x0063
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#define MBOX_GET_PORT_DB 0x0064
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#define MBOX_CLEAR_ACA 0x0065
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#define MBOX_TARGET_RESET 0x0066
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#define MBOX_CLEAR_TASK_SET 0x0067
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#define MBOX_ABORT_TASK_SET 0x0068
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#define MBOX_GET_FW_STATE 0x0069
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#define MBOX_GET_PORT_NAME 0x006A
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#define MBOX_GET_LINK_STATUS 0x006B
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#define MBOX_INIT_LIP_RESET 0x006C
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#define MBOX_SEND_SNS 0x006E
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#define MBOX_FABRIC_LOGIN 0x006F
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#define MBOX_SEND_CHANGE_REQUEST 0x0070
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#define MBOX_FABRIC_LOGOUT 0x0071
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#define MBOX_INIT_LIP_LOGIN 0x0072
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#define MBOX_LUN_RESET 0x007E
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#define MBOX_DRIVER_HEARTBEAT 0x005B
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#define MBOX_FW_HEARTBEAT 0x005C
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#define MBOX_GET_SET_DATA_RATE 0x005D /* 23XX only */
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#define MBGSD_GET_RATE 0
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#define MBGSD_SET_RATE 1
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#define MBGSD_ONEGB 0
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#define MBGSD_TWOGB 1
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#define MBGSD_AUTO 2
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#define ISP2100_SET_PCI_PARAM 0x00ff
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#define MBOX_BUSY 0x04
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typedef struct {
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u_int16_t param[8];
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} mbreg_t;
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/*
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* Mailbox Command Complete Status Codes
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*/
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#define MBOX_COMMAND_COMPLETE 0x4000
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#define MBOX_INVALID_COMMAND 0x4001
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#define MBOX_HOST_INTERFACE_ERROR 0x4002
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#define MBOX_TEST_FAILED 0x4003
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#define MBOX_COMMAND_ERROR 0x4005
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#define MBOX_COMMAND_PARAM_ERROR 0x4006
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#define MBOX_PORT_ID_USED 0x4007
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#define MBOX_LOOP_ID_USED 0x4008
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#define MBOX_ALL_IDS_USED 0x4009
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#define MBOX_NOT_LOGGED_IN 0x400A
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#define MBLOGALL 0x000f
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#define MBLOGNONE 0x0000
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#define MBLOGMASK(x) ((x) & 0xf)
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/*
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* Asynchronous event status codes
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*/
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#define ASYNC_BUS_RESET 0x8001
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#define ASYNC_SYSTEM_ERROR 0x8002
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#define ASYNC_RQS_XFER_ERR 0x8003
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#define ASYNC_RSP_XFER_ERR 0x8004
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#define ASYNC_QWAKEUP 0x8005
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#define ASYNC_TIMEOUT_RESET 0x8006
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#define ASYNC_DEVICE_RESET 0x8007
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#define ASYNC_EXTMSG_UNDERRUN 0x800A
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#define ASYNC_SCAM_INT 0x800B
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#define ASYNC_HUNG_SCSI 0x800C
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#define ASYNC_KILLED_BUS 0x800D
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#define ASYNC_BUS_TRANSIT 0x800E /* LVD -> HVD, eg. */
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#define ASYNC_LIP_OCCURRED 0x8010
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#define ASYNC_LOOP_UP 0x8011
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#define ASYNC_LOOP_DOWN 0x8012
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#define ASYNC_LOOP_RESET 0x8013
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#define ASYNC_PDB_CHANGED 0x8014
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#define ASYNC_CHANGE_NOTIFY 0x8015
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#define ASYNC_LIP_F8 0x8016
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#define ASYNC_CMD_CMPLT 0x8020
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#define ASYNC_CTIO_DONE 0x8021
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#define ASYNC_IP_XMIT_DONE 0x8022
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#define ASYNC_IP_RECV_DONE 0x8023
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#define ASYNC_IP_BROADCAST 0x8024
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#define ASYNC_IP_RCVQ_LOW 0x8025
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#define ASYNC_IP_RCVQ_EMPTY 0x8026
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#define ASYNC_IP_RECV_DONE_ALIGNED 0x8027
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#define ASYNC_PTPMODE 0x8030
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#define ASYNC_RIO1 0x8031
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#define ASYNC_RIO2 0x8032
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#define ASYNC_RIO3 0x8033
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#define ASYNC_RIO4 0x8034
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#define ASYNC_RIO5 0x8035
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#define ASYNC_CONNMODE 0x8036
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#define ISP_CONN_LOOP 1
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#define ISP_CONN_PTP 2
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#define ISP_CONN_BADLIP 3
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#define ISP_CONN_FATAL 4
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#define ISP_CONN_LOOPBACK 5
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#define ASYNC_RIO_RESP 0x8040
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#define ASYNC_RIO_COMP 0x8042
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/*
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* 2.01.31 2200 Only. Need Bit 13 in Mailbox 1 for Set Firmware Options
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* mailbox command to enable this.
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*/
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#define ASYNC_QFULL_SENT 0x8049
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/*
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* Mailbox Usages
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*/
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#define WRITE_REQUEST_QUEUE_IN_POINTER(isp, value) \
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ISP_WRITE(isp, isp->isp_rqstinrp, value)
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#define READ_REQUEST_QUEUE_OUT_POINTER(isp) \
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ISP_READ(isp, isp->isp_rqstoutrp)
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#define READ_RESPONSE_QUEUE_IN_POINTER(isp) \
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ISP_READ(isp, isp->isp_respinrp)
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#define WRITE_RESPONSE_QUEUE_OUT_POINTER(isp, value) \
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ISP_WRITE(isp, isp->isp_respoutrp, value)
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/*
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* Command Structure Definitions
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*/
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typedef struct {
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u_int32_t ds_base;
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u_int32_t ds_count;
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} ispds_t;
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typedef struct {
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u_int32_t ds_base;
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u_int32_t ds_basehi;
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u_int32_t ds_count;
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} ispds64_t;
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#define DSTYPE_32BIT 0
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#define DSTYPE_64BIT 1
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typedef struct {
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u_int16_t ds_type; /* 0-> ispds_t, 1-> ispds64_t */
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u_int32_t ds_segment; /* unused */
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u_int32_t ds_base; /* 32 bit address of DSD list */
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} ispdslist_t;
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/*
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* These elements get swizzled around for SBus instances.
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*/
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#define ISP_SWAP8(a, b) { \
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u_int8_t tmp; \
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tmp = a; \
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a = b; \
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b = tmp; \
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}
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typedef struct {
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u_int8_t rqs_entry_type;
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u_int8_t rqs_entry_count;
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u_int8_t rqs_seqno;
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u_int8_t rqs_flags;
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} isphdr_t;
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/* RQS Flag definitions */
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#define RQSFLAG_CONTINUATION 0x01
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#define RQSFLAG_FULL 0x02
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#define RQSFLAG_BADHEADER 0x04
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#define RQSFLAG_BADPACKET 0x08
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/* RQS entry_type definitions */
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#define RQSTYPE_REQUEST 0x01
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#define RQSTYPE_DATASEG 0x02
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#define RQSTYPE_RESPONSE 0x03
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#define RQSTYPE_MARKER 0x04
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#define RQSTYPE_CMDONLY 0x05
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#define RQSTYPE_ATIO 0x06 /* Target Mode */
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#define RQSTYPE_CTIO 0x07 /* Target Mode */
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#define RQSTYPE_SCAM 0x08
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#define RQSTYPE_A64 0x09
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#define RQSTYPE_A64_CONT 0x0a
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#define RQSTYPE_ENABLE_LUN 0x0b /* Target Mode */
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#define RQSTYPE_MODIFY_LUN 0x0c /* Target Mode */
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#define RQSTYPE_NOTIFY 0x0d /* Target Mode */
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#define RQSTYPE_NOTIFY_ACK 0x0e /* Target Mode */
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#define RQSTYPE_CTIO1 0x0f /* Target Mode */
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#define RQSTYPE_STATUS_CONT 0x10
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#define RQSTYPE_T2RQS 0x11
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#define RQSTYPE_IP_XMIT 0x13
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#define RQSTYPE_T4RQS 0x15
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#define RQSTYPE_ATIO2 0x16 /* Target Mode */
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#define RQSTYPE_CTIO2 0x17 /* Target Mode */
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#define RQSTYPE_CSET0 0x18
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#define RQSTYPE_T3RQS 0x19
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#define RQSTYPE_IP_XMIT_64 0x1b
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#define RQSTYPE_CTIO4 0x1e /* Target Mode */
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#define RQSTYPE_CTIO3 0x1f /* Target Mode */
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#define RQSTYPE_RIO1 0x21
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#define RQSTYPE_RIO2 0x22
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#define RQSTYPE_IP_RECV 0x23
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#define RQSTYPE_IP_RECV_CONT 0x24
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#define ISP_RQDSEG 4
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typedef struct {
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isphdr_t req_header;
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u_int32_t req_handle;
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u_int8_t req_lun_trn;
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u_int8_t req_target;
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u_int16_t req_cdblen;
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#define req_modifier req_cdblen /* marker packet */
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u_int16_t req_flags;
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u_int16_t req_reserved;
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u_int16_t req_time;
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u_int16_t req_seg_count;
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u_int8_t req_cdb[12];
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ispds_t req_dataseg[ISP_RQDSEG];
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} ispreq_t;
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#define ispreq64_t ispreqt3_t /* same as.... */
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#define ISP_RQDSEG_A64 2
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/*
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* A request packet can also be a marker packet.
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*/
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#define SYNC_DEVICE 0
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#define SYNC_TARGET 1
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#define SYNC_ALL 2
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#define ISP_RQDSEG_T2 3
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typedef struct {
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isphdr_t req_header;
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u_int32_t req_handle;
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u_int8_t req_lun_trn;
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u_int8_t req_target;
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u_int16_t req_scclun;
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u_int16_t req_flags;
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u_int16_t _res2;
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u_int16_t req_time;
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u_int16_t req_seg_count;
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u_int8_t req_cdb[16];
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u_int32_t req_totalcnt;
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ispds_t req_dataseg[ISP_RQDSEG_T2];
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} ispreqt2_t;
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#define ISP_RQDSEG_T3 2
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typedef struct {
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isphdr_t req_header;
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u_int32_t req_handle;
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u_int8_t req_lun_trn;
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u_int8_t req_target;
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u_int16_t req_scclun;
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u_int16_t req_flags;
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u_int16_t _res2;
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u_int16_t req_time;
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u_int16_t req_seg_count;
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u_int8_t req_cdb[16];
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u_int32_t req_totalcnt;
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ispds64_t req_dataseg[ISP_RQDSEG_T3];
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} ispreqt3_t;
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/* req_flag values */
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#define REQFLAG_NODISCON 0x0001
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#define REQFLAG_HTAG 0x0002
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#define REQFLAG_OTAG 0x0004
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#define REQFLAG_STAG 0x0008
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#define REQFLAG_TARGET_RTN 0x0010
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#define REQFLAG_NODATA 0x0000
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#define REQFLAG_DATA_IN 0x0020
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#define REQFLAG_DATA_OUT 0x0040
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#define REQFLAG_DATA_UNKNOWN 0x0060
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#define REQFLAG_DISARQ 0x0100
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#define REQFLAG_FRC_ASYNC 0x0200
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#define REQFLAG_FRC_SYNC 0x0400
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#define REQFLAG_FRC_WIDE 0x0800
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#define REQFLAG_NOPARITY 0x1000
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#define REQFLAG_STOPQ 0x2000
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#define REQFLAG_XTRASNS 0x4000
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#define REQFLAG_PRIORITY 0x8000
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typedef struct {
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isphdr_t req_header;
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u_int32_t req_handle;
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u_int8_t req_lun_trn;
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u_int8_t req_target;
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u_int16_t req_cdblen;
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u_int16_t req_flags;
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u_int16_t _res1;
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u_int16_t req_time;
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u_int16_t req_seg_count;
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u_int8_t req_cdb[44];
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} ispextreq_t;
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#define ISP_CDSEG 7
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typedef struct {
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isphdr_t req_header;
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u_int32_t _res1;
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ispds_t req_dataseg[ISP_CDSEG];
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} ispcontreq_t;
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#define ISP_CDSEG64 5
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typedef struct {
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isphdr_t req_header;
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ispds64_t req_dataseg[ISP_CDSEG64];
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} ispcontreq64_t;
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typedef struct {
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isphdr_t req_header;
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u_int32_t req_handle;
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u_int16_t req_scsi_status;
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u_int16_t req_completion_status;
|
|
u_int16_t req_state_flags;
|
|
u_int16_t req_status_flags;
|
|
u_int16_t req_time;
|
|
#define req_response_len req_time /* FC only */
|
|
u_int16_t req_sense_len;
|
|
u_int32_t req_resid;
|
|
u_int8_t req_response[8]; /* FC only */
|
|
u_int8_t req_sense_data[32];
|
|
} ispstatusreq_t;
|
|
|
|
typedef struct {
|
|
isphdr_t req_header;
|
|
u_int8_t req_sense_data[60];
|
|
} ispstatus_cont_t;
|
|
|
|
/*
|
|
* For Qlogic 2X00, the high order byte of SCSI status has
|
|
* additional meaning.
|
|
*/
|
|
#define RQCS_RU 0x800 /* Residual Under */
|
|
#define RQCS_RO 0x400 /* Residual Over */
|
|
#define RQCS_RESID (RQCS_RU|RQCS_RO)
|
|
#define RQCS_SV 0x200 /* Sense Length Valid */
|
|
#define RQCS_RV 0x100 /* FCP Response Length Valid */
|
|
|
|
/*
|
|
* Completion Status Codes.
|
|
*/
|
|
#define RQCS_COMPLETE 0x0000
|
|
#define RQCS_DMA_ERROR 0x0002
|
|
#define RQCS_RESET_OCCURRED 0x0004
|
|
#define RQCS_ABORTED 0x0005
|
|
#define RQCS_TIMEOUT 0x0006
|
|
#define RQCS_DATA_OVERRUN 0x0007
|
|
#define RQCS_DATA_UNDERRUN 0x0015
|
|
#define RQCS_QUEUE_FULL 0x001C
|
|
|
|
/* 1X00 Only Completion Codes */
|
|
#define RQCS_INCOMPLETE 0x0001
|
|
#define RQCS_TRANSPORT_ERROR 0x0003
|
|
#define RQCS_COMMAND_OVERRUN 0x0008
|
|
#define RQCS_STATUS_OVERRUN 0x0009
|
|
#define RQCS_BAD_MESSAGE 0x000a
|
|
#define RQCS_NO_MESSAGE_OUT 0x000b
|
|
#define RQCS_EXT_ID_FAILED 0x000c
|
|
#define RQCS_IDE_MSG_FAILED 0x000d
|
|
#define RQCS_ABORT_MSG_FAILED 0x000e
|
|
#define RQCS_REJECT_MSG_FAILED 0x000f
|
|
#define RQCS_NOP_MSG_FAILED 0x0010
|
|
#define RQCS_PARITY_ERROR_MSG_FAILED 0x0011
|
|
#define RQCS_DEVICE_RESET_MSG_FAILED 0x0012
|
|
#define RQCS_ID_MSG_FAILED 0x0013
|
|
#define RQCS_UNEXP_BUS_FREE 0x0014
|
|
#define RQCS_XACT_ERR1 0x0018
|
|
#define RQCS_XACT_ERR2 0x0019
|
|
#define RQCS_XACT_ERR3 0x001A
|
|
#define RQCS_BAD_ENTRY 0x001B
|
|
#define RQCS_PHASE_SKIPPED 0x001D
|
|
#define RQCS_ARQS_FAILED 0x001E
|
|
#define RQCS_WIDE_FAILED 0x001F
|
|
#define RQCS_SYNCXFER_FAILED 0x0020
|
|
#define RQCS_LVD_BUSERR 0x0021
|
|
|
|
/* 2X00 Only Completion Codes */
|
|
#define RQCS_PORT_UNAVAILABLE 0x0028
|
|
#define RQCS_PORT_LOGGED_OUT 0x0029
|
|
#define RQCS_PORT_CHANGED 0x002A
|
|
#define RQCS_PORT_BUSY 0x002B
|
|
|
|
/*
|
|
* 1X00 specific State Flags
|
|
*/
|
|
#define RQSF_GOT_BUS 0x0100
|
|
#define RQSF_GOT_TARGET 0x0200
|
|
#define RQSF_SENT_CDB 0x0400
|
|
#define RQSF_XFRD_DATA 0x0800
|
|
#define RQSF_GOT_STATUS 0x1000
|
|
#define RQSF_GOT_SENSE 0x2000
|
|
#define RQSF_XFER_COMPLETE 0x4000
|
|
|
|
/*
|
|
* 2X00 specific State Flags
|
|
* (same as 1X00 except RQSF_GOT_BUS/RQSF_GOT_TARGET are not available)
|
|
*/
|
|
#define RQSF_DATA_IN 0x0020
|
|
#define RQSF_DATA_OUT 0x0040
|
|
#define RQSF_STAG 0x0008
|
|
#define RQSF_OTAG 0x0004
|
|
#define RQSF_HTAG 0x0002
|
|
/*
|
|
* 1X00 Status Flags
|
|
*/
|
|
#define RQSTF_DISCONNECT 0x0001
|
|
#define RQSTF_SYNCHRONOUS 0x0002
|
|
#define RQSTF_PARITY_ERROR 0x0004
|
|
#define RQSTF_BUS_RESET 0x0008
|
|
#define RQSTF_DEVICE_RESET 0x0010
|
|
#define RQSTF_ABORTED 0x0020
|
|
#define RQSTF_TIMEOUT 0x0040
|
|
#define RQSTF_NEGOTIATION 0x0080
|
|
|
|
/*
|
|
* 2X00 specific state flags
|
|
*/
|
|
/* RQSF_SENT_CDB */
|
|
/* RQSF_XFRD_DATA */
|
|
/* RQSF_GOT_STATUS */
|
|
/* RQSF_XFER_COMPLETE */
|
|
|
|
/*
|
|
* 2X00 specific status flags
|
|
*/
|
|
/* RQSTF_ABORTED */
|
|
/* RQSTF_TIMEOUT */
|
|
#define RQSTF_DMA_ERROR 0x0080
|
|
#define RQSTF_LOGOUT 0x2000
|
|
|
|
/*
|
|
* Miscellaneous
|
|
*/
|
|
#ifndef ISP_EXEC_THROTTLE
|
|
#define ISP_EXEC_THROTTLE 16
|
|
#endif
|
|
|
|
/*
|
|
* About Firmware returns an 'attribute' word in mailbox 6.
|
|
*/
|
|
#define ISP_FW_ATTR_TMODE 0x01
|
|
#define ISP_FW_ATTR_SCCLUN 0x02
|
|
#define ISP_FW_ATTR_FABRIC 0x04
|
|
#define ISP_FW_ATTR_CLASS2 0x08
|
|
#define ISP_FW_ATTR_FCTAPE 0x10
|
|
#define ISP_FW_ATTR_IP 0x20
|
|
|
|
/*
|
|
* Reduced Interrupt Operation Response Queue Entreis
|
|
*/
|
|
|
|
typedef struct {
|
|
isphdr_t req_header;
|
|
u_int32_t req_handles[15];
|
|
} isp_rio1_t;
|
|
|
|
typedef struct {
|
|
isphdr_t req_header;
|
|
u_int16_t req_handles[30];
|
|
} isp_rio2_t;
|
|
|
|
/*
|
|
* FC (ISP2100) specific data structures
|
|
*/
|
|
|
|
/*
|
|
* Initialization Control Block
|
|
*
|
|
* Version One (prime) format.
|
|
*/
|
|
typedef struct isp_icb {
|
|
u_int8_t icb_version;
|
|
u_int8_t _reserved0;
|
|
u_int16_t icb_fwoptions;
|
|
u_int16_t icb_maxfrmlen;
|
|
u_int16_t icb_maxalloc;
|
|
u_int16_t icb_execthrottle;
|
|
u_int8_t icb_retry_count;
|
|
u_int8_t icb_retry_delay;
|
|
u_int8_t icb_portname[8];
|
|
u_int16_t icb_hardaddr;
|
|
u_int8_t icb_iqdevtype;
|
|
u_int8_t icb_logintime;
|
|
u_int8_t icb_nodename[8];
|
|
u_int16_t icb_rqstout;
|
|
u_int16_t icb_rspnsin;
|
|
u_int16_t icb_rqstqlen;
|
|
u_int16_t icb_rsltqlen;
|
|
u_int16_t icb_rqstaddr[4];
|
|
u_int16_t icb_respaddr[4];
|
|
u_int16_t icb_lunenables;
|
|
u_int8_t icb_ccnt;
|
|
u_int8_t icb_icnt;
|
|
u_int16_t icb_lunetimeout;
|
|
u_int16_t _reserved1;
|
|
u_int16_t icb_xfwoptions;
|
|
u_int8_t icb_racctimer;
|
|
u_int8_t icb_idelaytimer;
|
|
u_int16_t icb_zfwoptions;
|
|
u_int16_t _reserved2[13];
|
|
} isp_icb_t;
|
|
#define ICB_VERSION1 1
|
|
|
|
#define ICBOPT_HARD_ADDRESS 0x0001
|
|
#define ICBOPT_FAIRNESS 0x0002
|
|
#define ICBOPT_FULL_DUPLEX 0x0004
|
|
#define ICBOPT_FAST_POST 0x0008
|
|
#define ICBOPT_TGT_ENABLE 0x0010
|
|
#define ICBOPT_INI_DISABLE 0x0020
|
|
#define ICBOPT_INI_ADISC 0x0040
|
|
#define ICBOPT_INI_TGTTYPE 0x0080
|
|
#define ICBOPT_PDBCHANGE_AE 0x0100
|
|
#define ICBOPT_NOLIP 0x0200
|
|
#define ICBOPT_SRCHDOWN 0x0400
|
|
#define ICBOPT_PREVLOOP 0x0800
|
|
#define ICBOPT_STOP_ON_QFULL 0x1000
|
|
#define ICBOPT_FULL_LOGIN 0x2000
|
|
#define ICBOPT_BOTH_WWNS 0x4000
|
|
#define ICBOPT_EXTENDED 0x8000
|
|
|
|
#define ICBXOPT_CLASS2_ACK0 0x0200
|
|
#define ICBXOPT_CLASS2 0x0100
|
|
#define ICBXOPT_LOOP_ONLY (0 << 4)
|
|
#define ICBXOPT_PTP_ONLY (1 << 4)
|
|
#define ICBXOPT_LOOP_2_PTP (2 << 4)
|
|
#define ICBXOPT_PTP_2_LOOP (3 << 4)
|
|
|
|
/*
|
|
* The lower 4 bits of the xfwoptions field are the OPERATION MODE bits.
|
|
* RIO is not defined for the 23XX cards
|
|
*/
|
|
#define ICBXOPT_RIO_OFF 0
|
|
#define ICBXOPT_RIO_16BIT 1
|
|
#define ICBXOPT_RIO_32BIT 2
|
|
#define ICBXOPT_RIO_16BIT_IOCB 3
|
|
#define ICBXOPT_RIO_32BIT_IOCB 4
|
|
#define ICBXOPT_ZIO 5
|
|
|
|
#define ICBZOPT_ENA_RDXFR_RDY 0x01
|
|
#define ICBZOPT_ENA_OOF (1 << 6) /* out of order frame handling */
|
|
/* These 3 only apply to the 2300 */
|
|
#define ICBZOPT_RATE_ONEGB (MBGSD_ONEGB << 14)
|
|
#define ICBZOPT_RATE_TWOGB (MBGSD_TWOGB << 14)
|
|
#define ICBZOPT_RATE_AUTO (MBGSD_AUTO << 14)
|
|
|
|
|
|
#define ICB_MIN_FRMLEN 256
|
|
#define ICB_MAX_FRMLEN 2112
|
|
#define ICB_DFLT_FRMLEN 1024
|
|
#define ICB_DFLT_ALLOC 256
|
|
#define ICB_DFLT_THROTTLE 16
|
|
#define ICB_DFLT_RDELAY 5
|
|
#define ICB_DFLT_RCOUNT 3
|
|
|
|
|
|
#define RQRSP_ADDR0015 0
|
|
#define RQRSP_ADDR1631 1
|
|
#define RQRSP_ADDR3247 2
|
|
#define RQRSP_ADDR4863 3
|
|
|
|
|
|
#define ICB_NNM0 7
|
|
#define ICB_NNM1 6
|
|
#define ICB_NNM2 5
|
|
#define ICB_NNM3 4
|
|
#define ICB_NNM4 3
|
|
#define ICB_NNM5 2
|
|
#define ICB_NNM6 1
|
|
#define ICB_NNM7 0
|
|
|
|
#define MAKE_NODE_NAME_FROM_WWN(array, wwn) \
|
|
array[ICB_NNM0] = (u_int8_t) ((wwn >> 0) & 0xff), \
|
|
array[ICB_NNM1] = (u_int8_t) ((wwn >> 8) & 0xff), \
|
|
array[ICB_NNM2] = (u_int8_t) ((wwn >> 16) & 0xff), \
|
|
array[ICB_NNM3] = (u_int8_t) ((wwn >> 24) & 0xff), \
|
|
array[ICB_NNM4] = (u_int8_t) ((wwn >> 32) & 0xff), \
|
|
array[ICB_NNM5] = (u_int8_t) ((wwn >> 40) & 0xff), \
|
|
array[ICB_NNM6] = (u_int8_t) ((wwn >> 48) & 0xff), \
|
|
array[ICB_NNM7] = (u_int8_t) ((wwn >> 56) & 0xff)
|
|
|
|
#define MAKE_WWN_FROM_NODE_NAME(wwn, array) \
|
|
wwn = ((u_int64_t) array[ICB_NNM0]) | \
|
|
((u_int64_t) array[ICB_NNM1] << 8) | \
|
|
((u_int64_t) array[ICB_NNM2] << 16) | \
|
|
((u_int64_t) array[ICB_NNM3] << 24) | \
|
|
((u_int64_t) array[ICB_NNM4] << 32) | \
|
|
((u_int64_t) array[ICB_NNM5] << 40) | \
|
|
((u_int64_t) array[ICB_NNM6] << 48) | \
|
|
((u_int64_t) array[ICB_NNM7] << 56)
|
|
|
|
/*
|
|
* FC-AL Position Map
|
|
*
|
|
* This is an at most 128 byte map that returns either
|
|
* the LILP or Firmware generated list of ports.
|
|
*
|
|
* We deviate a bit from the returned qlogic format to
|
|
* use an extra bit to say whether this was a LILP or
|
|
* f/w generated map.
|
|
*/
|
|
typedef struct {
|
|
u_int8_t fwmap : 1,
|
|
count : 7;
|
|
u_int8_t map[127];
|
|
} fcpos_map_t;
|
|
|
|
/*
|
|
* Port Data Base Element
|
|
*/
|
|
|
|
typedef struct {
|
|
u_int16_t pdb_options;
|
|
u_int8_t pdb_mstate;
|
|
u_int8_t pdb_sstate;
|
|
#define BITS2WORD(x) ((x)[0] << 16 | (x)[3] << 8 | (x)[2])
|
|
u_int8_t pdb_hardaddr_bits[4];
|
|
u_int8_t pdb_portid_bits[4];
|
|
u_int8_t pdb_nodename[8];
|
|
u_int8_t pdb_portname[8];
|
|
u_int16_t pdb_execthrottle;
|
|
u_int16_t pdb_exec_count;
|
|
u_int8_t pdb_retry_count;
|
|
u_int8_t pdb_retry_delay;
|
|
u_int16_t pdb_resalloc;
|
|
u_int16_t pdb_curalloc;
|
|
u_int16_t pdb_qhead;
|
|
u_int16_t pdb_qtail;
|
|
u_int16_t pdb_tl_next;
|
|
u_int16_t pdb_tl_last;
|
|
u_int16_t pdb_features; /* PLOGI, Common Service */
|
|
u_int16_t pdb_pconcurrnt; /* PLOGI, Common Service */
|
|
u_int16_t pdb_roi; /* PLOGI, Common Service */
|
|
u_int8_t pdb_target;
|
|
u_int8_t pdb_initiator; /* PLOGI, Class 3 Control Flags */
|
|
u_int16_t pdb_rdsiz; /* PLOGI, Class 3 */
|
|
u_int16_t pdb_ncseq; /* PLOGI, Class 3 */
|
|
u_int16_t pdb_noseq; /* PLOGI, Class 3 */
|
|
u_int16_t pdb_labrtflg;
|
|
u_int16_t pdb_lstopflg;
|
|
u_int16_t pdb_sqhead;
|
|
u_int16_t pdb_sqtail;
|
|
u_int16_t pdb_ptimer;
|
|
u_int16_t pdb_nxt_seqid;
|
|
u_int16_t pdb_fcount;
|
|
u_int16_t pdb_prli_len;
|
|
u_int16_t pdb_prli_svc0;
|
|
u_int16_t pdb_prli_svc3;
|
|
u_int16_t pdb_loopid;
|
|
u_int16_t pdb_il_ptr;
|
|
u_int16_t pdb_sl_ptr;
|
|
} isp_pdb_t;
|
|
|
|
#define PDB_OPTIONS_XMITTING (1<<11)
|
|
#define PDB_OPTIONS_LNKXMIT (1<<10)
|
|
#define PDB_OPTIONS_ABORTED (1<<9)
|
|
#define PDB_OPTIONS_ADISC (1<<1)
|
|
|
|
#define PDB_STATE_DISCOVERY 0
|
|
#define PDB_STATE_WDISC_ACK 1
|
|
#define PDB_STATE_PLOGI 2
|
|
#define PDB_STATE_PLOGI_ACK 3
|
|
#define PDB_STATE_PRLI 4
|
|
#define PDB_STATE_PRLI_ACK 5
|
|
#define PDB_STATE_LOGGED_IN 6
|
|
#define PDB_STATE_PORT_UNAVAIL 7
|
|
#define PDB_STATE_PRLO 8
|
|
#define PDB_STATE_PRLO_ACK 9
|
|
#define PDB_STATE_PLOGO 10
|
|
#define PDB_STATE_PLOG_ACK 11
|
|
|
|
#define SVC3_TGT_ROLE 0x10
|
|
#define SVC3_INI_ROLE 0x20
|
|
#define SVC3_ROLE_MASK 0x30
|
|
#define SVC3_ROLE_SHIFT 4
|
|
|
|
/*
|
|
* CT definition
|
|
*
|
|
* This is as the QLogic f/w documentations defines it- which is just opposite,
|
|
* bit wise, from what the specification defines it as. Additionally, the
|
|
* ct_response and ct_resid (really from FC-GS-2) need to be byte swapped.
|
|
*/
|
|
|
|
typedef struct {
|
|
u_int8_t ct_revision;
|
|
u_int8_t ct_portid[3];
|
|
u_int8_t ct_fcs_type;
|
|
u_int8_t ct_fcs_subtype;
|
|
u_int8_t ct_options;
|
|
u_int8_t ct_res0;
|
|
u_int16_t ct_response;
|
|
u_int16_t ct_resid;
|
|
u_int8_t ct_res1;
|
|
u_int8_t ct_reason;
|
|
u_int8_t ct_explanation;
|
|
u_int8_t ct_vunique;
|
|
} ct_hdr_t;
|
|
#define FS_ACC 0x8002
|
|
#define FS_RJT 0x8001
|
|
|
|
#define FC4_IP 5 /* ISO/EEC 8802-2 LLC/SNAP "Out of Order Delivery" */
|
|
#define FC4_SCSI 8 /* SCSI-3 via Fivre Channel Protocol (FCP) */
|
|
#define FC4_FC_SVC 0x20 /* Fibre Channel Services */
|
|
|
|
#define SNS_GA_NXT 0x100
|
|
#define SNS_GPN_ID 0x112
|
|
#define SNS_GNN_ID 0x113
|
|
#define SNS_GFF_ID 0x11F
|
|
#define SNS_GID_FT 0x171
|
|
#define SNS_RFT_ID 0x217
|
|
typedef struct {
|
|
u_int16_t snscb_rblen; /* response buffer length (words) */
|
|
u_int16_t snscb_res0;
|
|
u_int16_t snscb_addr[4]; /* response buffer address */
|
|
u_int16_t snscb_sblen; /* subcommand buffer length (words) */
|
|
u_int16_t snscb_res1;
|
|
u_int16_t snscb_data[1]; /* variable data */
|
|
} sns_screq_t; /* Subcommand Request Structure */
|
|
|
|
typedef struct {
|
|
u_int16_t snscb_rblen; /* response buffer length (words) */
|
|
u_int16_t snscb_res0;
|
|
u_int16_t snscb_addr[4]; /* response buffer address */
|
|
u_int16_t snscb_sblen; /* subcommand buffer length (words) */
|
|
u_int16_t snscb_res1;
|
|
u_int16_t snscb_cmd;
|
|
u_int16_t snscb_res2;
|
|
u_int32_t snscb_res3;
|
|
u_int32_t snscb_port;
|
|
} sns_ga_nxt_req_t;
|
|
#define SNS_GA_NXT_REQ_SIZE (sizeof (sns_ga_nxt_req_t))
|
|
|
|
typedef struct {
|
|
u_int16_t snscb_rblen; /* response buffer length (words) */
|
|
u_int16_t snscb_res0;
|
|
u_int16_t snscb_addr[4]; /* response buffer address */
|
|
u_int16_t snscb_sblen; /* subcommand buffer length (words) */
|
|
u_int16_t snscb_res1;
|
|
u_int16_t snscb_cmd;
|
|
u_int16_t snscb_res2;
|
|
u_int32_t snscb_res3;
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u_int32_t snscb_portid;
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} sns_gxn_id_req_t;
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#define SNS_GXN_ID_REQ_SIZE (sizeof (sns_gxn_id_req_t))
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typedef struct {
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u_int16_t snscb_rblen; /* response buffer length (words) */
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u_int16_t snscb_res0;
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u_int16_t snscb_addr[4]; /* response buffer address */
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u_int16_t snscb_sblen; /* subcommand buffer length (words) */
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u_int16_t snscb_res1;
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u_int16_t snscb_cmd;
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u_int16_t snscb_mword_div_2;
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u_int32_t snscb_res3;
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u_int32_t snscb_fc4_type;
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} sns_gid_ft_req_t;
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#define SNS_GID_FT_REQ_SIZE (sizeof (sns_gid_ft_req_t))
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typedef struct {
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u_int16_t snscb_rblen; /* response buffer length (words) */
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u_int16_t snscb_res0;
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u_int16_t snscb_addr[4]; /* response buffer address */
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u_int16_t snscb_sblen; /* subcommand buffer length (words) */
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|
u_int16_t snscb_res1;
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|
u_int16_t snscb_cmd;
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u_int16_t snscb_res2;
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u_int32_t snscb_res3;
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u_int32_t snscb_port;
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u_int32_t snscb_fc4_types[8];
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} sns_rft_id_req_t;
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#define SNS_RFT_ID_REQ_SIZE (sizeof (sns_rft_id_req_t))
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typedef struct {
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ct_hdr_t snscb_cthdr;
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u_int8_t snscb_port_type;
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u_int8_t snscb_port_id[3];
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u_int8_t snscb_portname[8];
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u_int16_t snscb_data[1]; /* variable data */
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} sns_scrsp_t; /* Subcommand Response Structure */
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typedef struct {
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ct_hdr_t snscb_cthdr;
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u_int8_t snscb_port_type;
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u_int8_t snscb_port_id[3];
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u_int8_t snscb_portname[8];
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|
u_int8_t snscb_pnlen; /* symbolic port name length */
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|
u_int8_t snscb_pname[255]; /* symbolic port name */
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|
u_int8_t snscb_nodename[8];
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|
u_int8_t snscb_nnlen; /* symbolic node name length */
|
|
u_int8_t snscb_nname[255]; /* symbolic node name */
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|
u_int8_t snscb_ipassoc[8];
|
|
u_int8_t snscb_ipaddr[16];
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|
u_int8_t snscb_svc_class[4];
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|
u_int8_t snscb_fc4_types[32];
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|
u_int8_t snscb_fpname[8];
|
|
u_int8_t snscb_reserved;
|
|
u_int8_t snscb_hardaddr[3];
|
|
} sns_ga_nxt_rsp_t; /* Subcommand Response Structure */
|
|
#define SNS_GA_NXT_RESP_SIZE (sizeof (sns_ga_nxt_rsp_t))
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|
|
|
typedef struct {
|
|
ct_hdr_t snscb_cthdr;
|
|
u_int8_t snscb_wwn[8];
|
|
} sns_gxn_id_rsp_t;
|
|
#define SNS_GXN_ID_RESP_SIZE (sizeof (sns_gxn_id_rsp_t))
|
|
|
|
typedef struct {
|
|
ct_hdr_t snscb_cthdr;
|
|
u_int32_t snscb_fc4_features[32];
|
|
} sns_gff_id_rsp_t;
|
|
#define SNS_GFF_ID_RESP_SIZE (sizeof (sns_gff_id_rsp_t))
|
|
|
|
typedef struct {
|
|
ct_hdr_t snscb_cthdr;
|
|
struct {
|
|
u_int8_t control;
|
|
u_int8_t portid[3];
|
|
} snscb_ports[1];
|
|
} sns_gid_ft_rsp_t;
|
|
#define SNS_GID_FT_RESP_SIZE(x) ((sizeof (sns_gid_ft_rsp_t)) + ((x - 1) << 2))
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|
|
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#define SNS_RFT_ID_RESP_SIZE (sizeof (ct_hdr_t))
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|
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#endif /* _ISPMBOX_H */
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