682 lines
17 KiB
C
682 lines
17 KiB
C
/*-
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* Copyright (c) 2000
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* Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Bill Paul.
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* 4. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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/*
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* Driver for the Broadcom BCR5400 1000baseTX PHY. Speed is always
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* 1000mbps; all we need to negotiate here is full or half duplex.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/socket.h>
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#include <sys/bus.h>
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#include <net/if.h>
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#include <net/ethernet.h>
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#include <net/if_media.h>
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#include <dev/mii/mii.h>
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#include <dev/mii/miivar.h>
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#include "miidevs.h"
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#include <dev/mii/brgphyreg.h>
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#include <net/if_arp.h>
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#include <machine/bus.h>
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#include <dev/bge/if_bgereg.h>
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#include <dev/bce/if_bcereg.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include "miibus_if.h"
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static int brgphy_probe(device_t);
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static int brgphy_attach(device_t);
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static device_method_t brgphy_methods[] = {
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/* device interface */
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DEVMETHOD(device_probe, brgphy_probe),
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DEVMETHOD(device_attach, brgphy_attach),
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DEVMETHOD(device_detach, mii_phy_detach),
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DEVMETHOD(device_shutdown, bus_generic_shutdown),
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{ 0, 0 }
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};
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static devclass_t brgphy_devclass;
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static driver_t brgphy_driver = {
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"brgphy",
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brgphy_methods,
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sizeof(struct mii_softc)
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};
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DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0);
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static int brgphy_service(struct mii_softc *, struct mii_data *, int);
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static void brgphy_status(struct mii_softc *);
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static int brgphy_mii_phy_auto(struct mii_softc *);
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static void brgphy_reset(struct mii_softc *);
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static void brgphy_loop(struct mii_softc *);
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static void bcm5401_load_dspcode(struct mii_softc *);
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static void bcm5411_load_dspcode(struct mii_softc *);
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static void bcm5703_load_dspcode(struct mii_softc *);
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static void bcm5750_load_dspcode(struct mii_softc *);
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static int brgphy_mii_model;
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static const struct mii_phydesc brgphys[] = {
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MII_PHY_DESC(xxBROADCOM, BCM5400),
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MII_PHY_DESC(xxBROADCOM, BCM5401),
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MII_PHY_DESC(xxBROADCOM, BCM5411),
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MII_PHY_DESC(xxBROADCOM, BCM5752),
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MII_PHY_DESC(xxBROADCOM, BCM5701),
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MII_PHY_DESC(xxBROADCOM, BCM5703),
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MII_PHY_DESC(xxBROADCOM, BCM5704),
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MII_PHY_DESC(xxBROADCOM, BCM5705),
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MII_PHY_DESC(xxBROADCOM, BCM5750),
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MII_PHY_DESC(xxBROADCOM, BCM5714),
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MII_PHY_DESC(xxBROADCOM, BCM5780),
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MII_PHY_DESC(xxBROADCOM, BCM5706C),
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MII_PHY_DESC(xxBROADCOM, BCM5708C),
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MII_PHY_END
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};
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static int
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brgphy_probe(device_t dev)
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{
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struct mii_attach_args *ma;
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const struct mii_phydesc *mpd;
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ma = device_get_ivars(dev);
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mpd = mii_phy_match(ma, brgphys);
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if (mpd != NULL) {
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device_set_desc(dev, mpd->mpd_name);
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return (BUS_PROBE_DEFAULT);
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}
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return (ENXIO);
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}
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static int
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brgphy_attach(device_t dev)
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{
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struct mii_softc *sc;
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struct mii_attach_args *ma;
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struct mii_data *mii;
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const char *sep = "";
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struct bge_softc *bge_sc = NULL;
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struct bce_softc *bce_sc = NULL;
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int fast_ether_only = FALSE;
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sc = device_get_softc(dev);
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ma = device_get_ivars(dev);
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sc->mii_dev = device_get_parent(dev);
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mii = device_get_softc(sc->mii_dev);
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LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
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sc->mii_inst = mii->mii_instance;
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sc->mii_phy = ma->mii_phyno;
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sc->mii_service = brgphy_service;
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sc->mii_pdata = mii;
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sc->mii_flags |= MIIF_NOISOLATE;
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mii->mii_instance++;
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#define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL)
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#define PRINT(s) printf("%s%s", sep, s); sep = ", "
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst),
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BMCR_ISO);
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#if 0
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst),
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BMCR_LOOP|BMCR_S100);
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#endif
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brgphy_mii_model = MII_MODEL(ma->mii_id2);
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brgphy_reset(sc);
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sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
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sc->mii_capabilities &= ~BMSR_ANEG;
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device_printf(dev, " ");
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mii_add_media(sc);
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/* Find the driver associated with this PHY. */
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if (strcmp(mii->mii_ifp->if_dname, "bge") == 0) {
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bge_sc = mii->mii_ifp->if_softc;
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} else if (strcmp(mii->mii_ifp->if_dname, "bce") == 0) {
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bce_sc = mii->mii_ifp->if_softc;
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}
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/* The 590x chips are 10/100 only. */
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if (strcmp(mii->mii_ifp->if_dname, "bge") == 0 &&
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pci_get_vendor(bge_sc->bge_dev) == BCOM_VENDORID &&
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(pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901 ||
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pci_get_device(bge_sc->bge_dev) == BCOM_DEVICEID_BCM5901A2))
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fast_ether_only = TRUE;
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if (fast_ether_only == FALSE) {
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0,
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sc->mii_inst), BRGPHY_BMCR_FDX);
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PRINT(", 1000baseTX");
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T,
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IFM_FDX, sc->mii_inst), 0);
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PRINT("1000baseTX-FDX");
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}
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0);
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PRINT("auto");
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printf("\n");
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#undef ADD
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#undef PRINT
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MIIBUS_MEDIAINIT(sc->mii_dev);
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return(0);
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}
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static int
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brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
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{
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struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
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int reg, speed, gig;
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switch (cmd) {
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case MII_POLLSTAT:
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/*
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* If we're not polling our PHY instance, just return.
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*/
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if (IFM_INST(ife->ifm_media) != sc->mii_inst)
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return (0);
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break;
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case MII_MEDIACHG:
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/*
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* If the media indicates a different PHY instance,
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* isolate ourselves.
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*/
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if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
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reg = PHY_READ(sc, MII_BMCR);
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PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
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return (0);
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}
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/*
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* If the interface is not up, don't do anything.
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*/
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if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
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break;
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brgphy_reset(sc); /* XXX hardware bug work-around */
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switch (IFM_SUBTYPE(ife->ifm_media)) {
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case IFM_AUTO:
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#ifdef foo
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/*
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* If we're already in auto mode, just return.
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*/
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if (PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_AUTOEN)
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return (0);
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#endif
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(void) brgphy_mii_phy_auto(sc);
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break;
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case IFM_1000_T:
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speed = BRGPHY_S1000;
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goto setit;
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case IFM_100_TX:
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speed = BRGPHY_S100;
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goto setit;
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case IFM_10_T:
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speed = BRGPHY_S10;
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setit:
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brgphy_loop(sc);
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if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
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speed |= BRGPHY_BMCR_FDX;
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gig = BRGPHY_1000CTL_AFD;
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} else {
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gig = BRGPHY_1000CTL_AHD;
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}
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PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0);
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PHY_WRITE(sc, BRGPHY_MII_BMCR, speed);
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PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE);
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if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)
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break;
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PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig);
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PHY_WRITE(sc, BRGPHY_MII_BMCR,
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speed|BRGPHY_BMCR_AUTOEN|BRGPHY_BMCR_STARTNEG);
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if (brgphy_mii_model != MII_MODEL_xxBROADCOM_BCM5701)
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break;
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/*
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* When settning the link manually, one side must
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* be the master and the other the slave. However
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* ifmedia doesn't give us a good way to specify
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* this, so we fake it by using one of the LINK
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* flags. If LINK0 is set, we program the PHY to
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* be a master, otherwise it's a slave.
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*/
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if ((mii->mii_ifp->if_flags & IFF_LINK0)) {
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PHY_WRITE(sc, BRGPHY_MII_1000CTL,
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gig|BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC);
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} else {
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PHY_WRITE(sc, BRGPHY_MII_1000CTL,
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gig|BRGPHY_1000CTL_MSE);
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}
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break;
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#ifdef foo
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case IFM_NONE:
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PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN);
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break;
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#endif
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case IFM_100_T4:
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default:
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return (EINVAL);
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}
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break;
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case MII_TICK:
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/*
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* If we're not currently selected, just return.
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*/
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if (IFM_INST(ife->ifm_media) != sc->mii_inst)
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return (0);
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/*
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* Is the interface even up?
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*/
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if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
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return (0);
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/*
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* Only used for autonegotiation.
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*/
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if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
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break;
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/*
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* Check to see if we have link. If we do, we don't
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* need to restart the autonegotiation process. Read
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* the BMSR twice in case it's latched.
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*/
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reg = PHY_READ(sc, BRGPHY_MII_AUXSTS);
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if (reg & BRGPHY_AUXSTS_LINK)
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break;
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/*
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* Only retry autonegotiation every 5 seconds.
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*/
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if (++sc->mii_ticks <= 5)
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break;
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sc->mii_ticks = 0;
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brgphy_mii_phy_auto(sc);
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break;
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}
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/* Update the media status. */
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brgphy_status(sc);
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/*
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* Callback if something changed. Note that we need to poke
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* the DSP on the Broadcom PHYs if the media changes.
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*
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*/
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if (sc->mii_media_active != mii->mii_media_active ||
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sc->mii_media_status != mii->mii_media_status ||
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cmd == MII_MEDIACHG) {
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switch (brgphy_mii_model) {
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case MII_MODEL_xxBROADCOM_BCM5400:
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case MII_MODEL_xxBROADCOM_BCM5401:
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bcm5401_load_dspcode(sc);
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break;
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case MII_MODEL_xxBROADCOM_BCM5411:
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bcm5411_load_dspcode(sc);
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break;
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}
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}
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mii_phy_update(sc, cmd);
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return (0);
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}
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static void
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brgphy_status(struct mii_softc *sc)
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{
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struct mii_data *mii = sc->mii_pdata;
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struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
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int bmsr, bmcr;
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mii->mii_media_status = IFM_AVALID;
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mii->mii_media_active = IFM_ETHER;
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bmsr = PHY_READ(sc, BRGPHY_MII_BMSR);
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if (PHY_READ(sc, BRGPHY_MII_AUXSTS) & BRGPHY_AUXSTS_LINK)
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mii->mii_media_status |= IFM_ACTIVE;
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bmcr = PHY_READ(sc, BRGPHY_MII_BMCR);
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if (bmcr & BRGPHY_BMCR_LOOP)
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mii->mii_media_active |= IFM_LOOP;
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if (bmcr & BRGPHY_BMCR_AUTOEN) {
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if ((bmsr & BRGPHY_BMSR_ACOMP) == 0) {
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/* Erg, still trying, I guess... */
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mii->mii_media_active |= IFM_NONE;
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return;
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}
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switch (PHY_READ(sc, BRGPHY_MII_AUXSTS) &
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BRGPHY_AUXSTS_AN_RES) {
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case BRGPHY_RES_1000FD:
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mii->mii_media_active |= IFM_1000_T | IFM_FDX;
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break;
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case BRGPHY_RES_1000HD:
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mii->mii_media_active |= IFM_1000_T | IFM_HDX;
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break;
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case BRGPHY_RES_100FD:
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mii->mii_media_active |= IFM_100_TX | IFM_FDX;
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break;
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case BRGPHY_RES_100T4:
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mii->mii_media_active |= IFM_100_T4;
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break;
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case BRGPHY_RES_100HD:
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mii->mii_media_active |= IFM_100_TX | IFM_HDX;
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break;
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case BRGPHY_RES_10FD:
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mii->mii_media_active |= IFM_10_T | IFM_FDX;
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break;
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case BRGPHY_RES_10HD:
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mii->mii_media_active |= IFM_10_T | IFM_HDX;
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break;
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default:
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mii->mii_media_active |= IFM_NONE;
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break;
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}
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return;
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}
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mii->mii_media_active = ife->ifm_media;
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return;
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}
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static int
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brgphy_mii_phy_auto(struct mii_softc *mii)
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{
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int ktcr = 0;
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brgphy_loop(mii);
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brgphy_reset(mii);
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ktcr = BRGPHY_1000CTL_AFD|BRGPHY_1000CTL_AHD;
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if (brgphy_mii_model == MII_MODEL_xxBROADCOM_BCM5701)
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ktcr |= BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC;
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PHY_WRITE(mii, BRGPHY_MII_1000CTL, ktcr);
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ktcr = PHY_READ(mii, BRGPHY_MII_1000CTL);
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DELAY(1000);
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PHY_WRITE(mii, BRGPHY_MII_ANAR,
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BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA);
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DELAY(1000);
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PHY_WRITE(mii, BRGPHY_MII_BMCR,
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BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG);
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PHY_WRITE(mii, BRGPHY_MII_IMR, 0xFF00);
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return (EJUSTRETURN);
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}
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static void
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brgphy_loop(struct mii_softc *sc)
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{
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u_int32_t bmsr;
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int i;
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PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP);
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for (i = 0; i < 15000; i++) {
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bmsr = PHY_READ(sc, BRGPHY_MII_BMSR);
|
|
if (!(bmsr & BRGPHY_BMSR_LINK)) {
|
|
#if 0
|
|
device_printf(sc->mii_dev, "looped %d\n", i);
|
|
#endif
|
|
break;
|
|
}
|
|
DELAY(10);
|
|
}
|
|
}
|
|
|
|
/* Turn off tap power management on 5401. */
|
|
static void
|
|
bcm5401_load_dspcode(struct mii_softc *sc)
|
|
{
|
|
static const struct {
|
|
int reg;
|
|
uint16_t val;
|
|
} dspcode[] = {
|
|
{ BRGPHY_MII_AUXCTL, 0x0c20 },
|
|
{ BRGPHY_MII_DSP_ADDR_REG, 0x0012 },
|
|
{ BRGPHY_MII_DSP_RW_PORT, 0x1804 },
|
|
{ BRGPHY_MII_DSP_ADDR_REG, 0x0013 },
|
|
{ BRGPHY_MII_DSP_RW_PORT, 0x1204 },
|
|
{ BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
|
|
{ BRGPHY_MII_DSP_RW_PORT, 0x0132 },
|
|
{ BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
|
|
{ BRGPHY_MII_DSP_RW_PORT, 0x0232 },
|
|
{ BRGPHY_MII_DSP_ADDR_REG, 0x201f },
|
|
{ BRGPHY_MII_DSP_RW_PORT, 0x0a20 },
|
|
{ 0, 0 },
|
|
};
|
|
int i;
|
|
|
|
for (i = 0; dspcode[i].reg != 0; i++)
|
|
PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
|
|
DELAY(40);
|
|
}
|
|
|
|
static void
|
|
bcm5411_load_dspcode(struct mii_softc *sc)
|
|
{
|
|
static const struct {
|
|
int reg;
|
|
uint16_t val;
|
|
} dspcode[] = {
|
|
{ 0x1c, 0x8c23 },
|
|
{ 0x1c, 0x8ca3 },
|
|
{ 0x1c, 0x8c23 },
|
|
{ 0, 0 },
|
|
};
|
|
int i;
|
|
|
|
for (i = 0; dspcode[i].reg != 0; i++)
|
|
PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
|
|
}
|
|
|
|
static void
|
|
bcm5703_load_dspcode(struct mii_softc *sc)
|
|
{
|
|
static const struct {
|
|
int reg;
|
|
uint16_t val;
|
|
} dspcode[] = {
|
|
{ BRGPHY_MII_AUXCTL, 0x0c00 },
|
|
{ BRGPHY_MII_DSP_ADDR_REG, 0x201f },
|
|
{ BRGPHY_MII_DSP_RW_PORT, 0x2aaa },
|
|
{ 0, 0 },
|
|
};
|
|
int i;
|
|
|
|
for (i = 0; dspcode[i].reg != 0; i++)
|
|
PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
|
|
}
|
|
|
|
static void
|
|
bcm5704_load_dspcode(struct mii_softc *sc)
|
|
{
|
|
static const struct {
|
|
int reg;
|
|
u_int16_t val;
|
|
} dspcode[] = {
|
|
{ 0x1c, 0x8d68 },
|
|
{ 0x1c, 0x8d68 },
|
|
{ 0, 0 },
|
|
};
|
|
int i;
|
|
|
|
for (i = 0; dspcode[i].reg != 0; i++)
|
|
PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
|
|
}
|
|
|
|
static void
|
|
bcm5750_load_dspcode(struct mii_softc *sc)
|
|
{
|
|
static const struct {
|
|
int reg;
|
|
u_int16_t val;
|
|
} dspcode[] = {
|
|
{ 0x18, 0x0c00 },
|
|
{ 0x17, 0x000a },
|
|
{ 0x15, 0x310b },
|
|
{ 0x17, 0x201f },
|
|
{ 0x15, 0x9506 },
|
|
{ 0x17, 0x401f },
|
|
{ 0x15, 0x14e2 },
|
|
{ 0x18, 0x0400 },
|
|
{ 0, 0 },
|
|
};
|
|
int i;
|
|
|
|
for (i = 0; dspcode[i].reg != 0; i++)
|
|
PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
|
|
}
|
|
|
|
static void
|
|
brgphy_reset(struct mii_softc *sc)
|
|
{
|
|
u_int32_t val;
|
|
struct ifnet *ifp;
|
|
struct bge_softc *bge_sc = NULL;
|
|
struct bce_softc *bce_sc = NULL;
|
|
|
|
mii_phy_reset(sc);
|
|
|
|
switch (brgphy_mii_model) {
|
|
case MII_MODEL_xxBROADCOM_BCM5400:
|
|
case MII_MODEL_xxBROADCOM_BCM5401:
|
|
bcm5401_load_dspcode(sc);
|
|
break;
|
|
case MII_MODEL_xxBROADCOM_BCM5411:
|
|
bcm5411_load_dspcode(sc);
|
|
break;
|
|
case MII_MODEL_xxBROADCOM_BCM5703:
|
|
bcm5703_load_dspcode(sc);
|
|
break;
|
|
case MII_MODEL_xxBROADCOM_BCM5704:
|
|
bcm5704_load_dspcode(sc);
|
|
break;
|
|
case MII_MODEL_xxBROADCOM_BCM5750:
|
|
case MII_MODEL_xxBROADCOM_BCM5752:
|
|
case MII_MODEL_xxBROADCOM_BCM5714:
|
|
case MII_MODEL_xxBROADCOM_BCM5780:
|
|
case MII_MODEL_xxBROADCOM_BCM5706C:
|
|
case MII_MODEL_xxBROADCOM_BCM5708C:
|
|
bcm5750_load_dspcode(sc);
|
|
break;
|
|
}
|
|
|
|
ifp = sc->mii_pdata->mii_ifp;
|
|
|
|
/* Find the driver associated with this PHY. */
|
|
if (strcmp(ifp->if_dname, "bge") == 0) {
|
|
bge_sc = ifp->if_softc;
|
|
} else if (strcmp(ifp->if_dname, "bce") == 0) {
|
|
bce_sc = ifp->if_softc;
|
|
}
|
|
|
|
/* Handle any NetXtreme/bge workarounds. */
|
|
if (bge_sc) {
|
|
/*
|
|
* Don't enable Ethernet@WireSpeed for the 5700 or the
|
|
* 5705 A1 and A2 chips. Make sure we only do this test
|
|
* on "bge" NICs, since other drivers may use this same
|
|
* PHY subdriver.
|
|
*/
|
|
if (bge_sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
|
|
bge_sc->bge_chipid == BGE_CHIPID_BCM5705_A1 ||
|
|
bge_sc->bge_chipid == BGE_CHIPID_BCM5705_A2)
|
|
return;
|
|
|
|
/* Enable Ethernet@WireSpeed. */
|
|
PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007);
|
|
val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
|
|
PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4));
|
|
|
|
/* Enable Link LED on Dell boxes */
|
|
if (bge_sc->bge_flags & BGE_FLAG_NO3LED) {
|
|
PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
|
|
PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL)
|
|
& ~BRGPHY_PHY_EXTCTL_3_LED);
|
|
}
|
|
} else if (bce_sc) {
|
|
|
|
/* Set or clear jumbo frame settings in the PHY. */
|
|
if (ifp->if_mtu > ETHER_MAX_LEN) {
|
|
PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
|
|
val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
|
|
PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
|
|
val | BRGPHY_AUXCTL_LONG_PKT);
|
|
|
|
val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
|
|
PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
|
|
val | BRGPHY_PHY_EXTCTL_HIGH_LA);
|
|
} else {
|
|
PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
|
|
val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
|
|
PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
|
|
val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7));
|
|
|
|
val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
|
|
PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
|
|
val & ~BRGPHY_PHY_EXTCTL_HIGH_LA);
|
|
}
|
|
|
|
/* Enable Ethernet@Wirespeed */
|
|
PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007);
|
|
val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
|
|
PHY_WRITE(sc, BRGPHY_MII_AUXCTL, (val | (1 << 15) | (1 << 4)));
|
|
}
|
|
}
|