a07bd003bf
VT6122 gigabit ethernet chip and integrated 10/100/1000 copper PHY. The vge driver has been added to GENERIC for i386, pc98 and amd64, but not to sparc or ia64 since I don't have the ability to test it there. The vge(4) driver supports VLANs, checksum offload and jumbo frames. Also added the lge(4) and nge(4) drivers to GENERIC for i386 and pc98 since I was in the neighborhood. There's no reason to leave them out anymore.
352 lines
16 KiB
C
352 lines
16 KiB
C
/*
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* Copyright (c) 2004
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* Bill Paul <wpaul@windriver.com>. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Bill Paul.
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* 4. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _DEV_MII_CIPHYREG_H_
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#define _DEV_MII_CIPHYREG_H_
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/*
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* Register definitions for the Cicada CS8201 10/100/1000 gigE copper
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* PHY, embedded within the VIA Networks VT6122 controller.
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*/
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/* Command register */
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#define CIPHY_MII_BMCR 0x00
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#define CIPHY_BMCR_RESET 0x8000
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#define CIPHY_BMCR_LOOP 0x4000
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#define CIPHY_BMCR_SPD0 0x2000 /* speed select, lower bit */
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#define CIPHY_BMCR_AUTOEN 0x1000 /* Autoneg enabled */
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#define CIPHY_BMCR_PDOWN 0x0800 /* Power down */
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#define CIPHY_BMCR_STARTNEG 0x0200 /* Restart autoneg */
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#define CIPHY_BMCR_FDX 0x0100 /* Duplex mode */
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#define CIPHY_BMCR_CTEST 0x0080 /* Collision test enable */
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#define CIPHY_BMCR_SPD1 0x0040 /* Speed select, upper bit */
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#define CIPHY_S1000 CIPHY_BMCR_SPD1 /* 1000mbps */
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#define CIPHY_S100 CIPHY_BMCR_SPD0 /* 100mpbs */
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#define CIPHY_S10 0 /* 10mbps */
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/* Status register */
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#define CIPHY_MII_BMSR 0x01
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#define CIPHY_BMSR_100T4 0x8000 /* 100 base T4 capable */
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#define CIPHY_BMSR_100TXFDX 0x4000 /* 100 base Tx full duplex capable */
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#define CIPHY_BMSR_100TXHDX 0x2000 /* 100 base Tx half duplex capable */
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#define CIPHY_BMSR_10TFDX 0x1000 /* 10 base T full duplex capable */
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#define CIPHY_BMSR_10THDX 0x0800 /* 10 base T half duplex capable */
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#define CIPHY_BMSR_100T2FDX 0x0400 /* 100 base T2 full duplex capable */
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#define CIPHY_BMSR_100T2HDX 0x0200 /* 100 base T2 half duplex capable */
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#define CIPHY_BMSR_EXTSTS 0x0100 /* Extended status present */
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#define CIPHY_BMSR_PRESUB 0x0040 /* Preamble surpression */
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#define CIPHY_BMSR_ACOMP 0x0020 /* Autoneg complete */
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#define CIPHY_BMSR_RFAULT 0x0010 /* Remote fault condition occured */
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#define CIPHY_BMSR_ANEG 0x0008 /* Autoneg capable */
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#define CIPHY_BMSR_LINK 0x0004 /* Link status */
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#define CIPHY_BMSR_JABBER 0x0002 /* Jabber detected */
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#define CIPHY_BMSR_EXT 0x0001 /* Extended capability */
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/* PHY ID registers */
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#define CIPHY_MII_PHYIDR1 0x02
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#define CIPHY_MII_PHYIDR2 0x03
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/* Autoneg advertisement */
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#define CIPHY_MII_ANAR 0x04
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#define CIPHY_ANAR_NP 0x8000 /* Next page */
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#define CIPHY_ANAR_RF 0x2000 /* Remote fault */
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#define CIPHY_ANAR_ASP 0x0800 /* Asymmetric Pause */
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#define CIPHY_ANAR_PC 0x0400 /* Pause capable */
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#define CIPHY_ANAR_T4 0x0200 /* local device supports 100bT4 */
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#define CIPHY_ANAR_TX_FD 0x0100 /* local device supports 100bTx FD */
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#define CIPHY_ANAR_TX 0x0080 /* local device supports 100bTx */
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#define CIPHY_ANAR_10_FD 0x0040 /* local device supports 10bT FD */
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#define CIPHY_ANAR_10 0x0020 /* local device supports 10bT */
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#define CIPHY_ANAR_SEL 0x001F /* selector field, 00001=Ethernet */
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/* Autoneg link partner ability */
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#define CIPHY_MII_ANLPAR 0x05
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#define CIPHY_ANLPAR_NP 0x8000 /* Next page */
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#define CIPHY_ANLPAR_ACK 0x4000 /* link partner acknowledge */
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#define CIPHY_ANLPAR_RF 0x2000 /* Remote fault */
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#define CIPHY_ANLPAR_ASP 0x0800 /* Asymmetric Pause */
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#define CIPHY_ANLPAR_PC 0x0400 /* Pause capable */
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#define CIPHY_ANLPAR_T4 0x0200 /* link partner supports 100bT4 */
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#define CIPHY_ANLPAR_TX_FD 0x0100 /* link partner supports 100bTx FD */
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#define CIPHY_ANLPAR_TX 0x0080 /* link partner supports 100bTx */
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#define CIPHY_ANLPAR_10_FD 0x0040 /* link partner supports 10bT FD */
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#define CIPHY_ANLPAR_10 0x0020 /* link partner supports 10bT */
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#define CIPHY_ANLPAR_SEL 0x001F /* selector field, 00001=Ethernet */
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#define CIPHY_SEL_TYPE 0x0001 /* ethernet */
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/* Antoneg expansion register */
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#define CIPHY_MII_ANER 0x06
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#define CIPHY_ANER_PDF 0x0010 /* Parallel detection fault */
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#define CIPHY_ANER_LPNP 0x0008 /* Link partner can next page */
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#define CIPHY_ANER_NP 0x0004 /* Local PHY can next page */
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#define CIPHY_ANER_RX 0x0002 /* Next page received */
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#define CIPHY_ANER_LPAN 0x0001 /* Link partner autoneg capable */
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/* Autoneg next page transmit regisyer */
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#define CIPHY_MII_NEXTP 0x07
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#define CIPHY_NEXTP_MOREP 0x8000 /* More pages to follow */
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#define CIPHY_NEXTP_MESS 0x2000 /* 1 = message page, 0 = unformatted */
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#define CIPHY_NEXTP_ACK2 0x1000 /* MAC acknowledge */
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#define CIPHY_NEXTP_TOGGLE 0x0800 /* Toggle */
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#define CIPHY_NEXTP_CODE 0x07FF /* Code bits */
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/* Autoneg link partner next page receive register */
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#define CIPHY_MII_NEXTP_LP 0x08
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#define CIPHY_NEXTPLP_MOREP 0x8000 /* More pages to follow */
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#define CIPHY_NEXTPLP_MESS 0x2000 /* 1 = message page, 0 = unformatted */
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#define CIPHY_NEXTPLP_ACK2 0x1000 /* MAC acknowledge */
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#define CIPHY_NEXTPLP_TOGGLE 0x0800 /* Toggle */
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#define CIPHY_NEXTPLP_CODE 0x07FF /* Code bits */
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/* 1000BT control register */
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#define CIPHY_MII_1000CTL 0x09
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#define CIPHY_1000CTL_TST 0xE000 /* test modes */
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#define CIPHY_1000CTL_MSE 0x1000 /* Master/Slave manual enable */
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#define CIPHY_1000CTL_MSC 0x0800 /* Master/Slave select */
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#define CIPHY_1000CTL_RD 0x0400 /* Repeater/DTE */
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#define CIPHY_1000CTL_AFD 0x0200 /* Advertise full duplex */
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#define CIPHY_1000CTL_AHD 0x0100 /* Advertise half duplex */
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#define CIPHY_TEST_TX_JITTER 0x2000
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#define CIPHY_TEST_TX_JITTER_MASTER_MODE 0x4000
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#define CIPHY_TEST_TX_JITTER_SLAVE_MODE 0x6000
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#define CIPHY_TEST_TX_DISTORTION 0x8000
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/* 1000BT status register */
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#define CIPHY_MII_1000STS 0x0A
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#define CIPHY_1000STS_MSF 0x8000 /* Master/slave fault */
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#define CIPHY_1000STS_MSR 0x4000 /* Master/slave result */
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#define CIPHY_1000STS_LRS 0x2000 /* Local receiver status */
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#define CIPHY_1000STS_RRS 0x1000 /* Remote receiver status */
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#define CIPHY_1000STS_LPFD 0x0800 /* Link partner can FD */
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#define CIPHY_1000STS_LPHD 0x0400 /* Link partner can HD */
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#define CIPHY_1000STS_IEC 0x00FF /* Idle error count */
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#define CIPHY_MII_EXTSTS 0x0F /* Extended status */
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#define CIPHY_EXTSTS_X_FD_CAP 0x8000 /* 1000base-X FD capable */
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#define CIPHY_EXTSTS_X_HD_CAP 0x4000 /* 1000base-X HD capable */
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#define CIPHY_EXTSTS_T_FD_CAP 0x2000 /* 1000base-T FD capable */
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#define CIPHY_EXTSTS_T_HD_CAP 0x1000 /* 1000base-T HD capable */
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/* 1000BT status extension register #1 */
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#define CIPHY_MII_1000STS1 0x0F
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#define CIPHY_1000STS1_1000XFDX 0x8000 /* 1000baseX FDX capable */
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#define CIPHY_1000STS1_1000XHDX 0x4000 /* 1000baseX HDX capable */
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#define CIPHY_1000STS1_1000TFDX 0x2000 /* 1000baseT FDX capable */
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#define CIPHY_1000STS1_1000THDX 0x1000 /* 1000baseT HDX capable */
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/* Vendor-specific PHY registers */
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/* 100baseTX status extention register */
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#define CIPHY_MII_100STS 0x10
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#define CIPHY_100STS_DESLCK 0x8000 /* descrambler locked */
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#define CIPHY_100STS_LKCERR 0x4000 /* lock error detected/lock lost */
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#define CIPHY_100STS_DISC 0x2000 /* disconnect state */
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#define CIPHY_100STS_LINK 0x1000 /* current link state */
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#define CIPHY_100STS_RXERR 0x0800 /* receive error detected */
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#define CIPHY_100STS_TXERR 0x0400 /* transmit error detected */
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#define CIPHY_100STS_SSDERR 0x0200 /* false carrier error detected */
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#define CIPHY_100STS_ESDERR 0x0100 /* premature end of stream error */
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/* 1000BT status extention register #2 */
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#define CIPHY_MII_1000STS2 0x11
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#define CIPHY_1000STS2_DESLCK 0x8000 /* descrambler locked */
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#define CIPHY_1000STS2_LKCERR 0x4000 /* lock error detected/lock lost */
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#define CIPHY_1000STS2_DISC 0x2000 /* disconnect state */
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#define CIPHY_1000STS2_LINK 0x1000 /* current link state */
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#define CIPHY_1000STS2_RXERR 0x0800 /* receive error detected */
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#define CIPHY_1000STS2_TXERR 0x0400 /* transmit error detected */
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#define CIPHY_1000STS2_SSDERR 0x0200 /* false carrier error detected */
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#define CIPHY_1000STS2_ESDERR 0x0100 /* premature end of stream error */
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#define CIPHY_1000STS2_CARREXT 0x0080 /* carrier extention err detected */
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#define CIPHY_1000STS2_BCM5400 0x0040 /* non-complient BCM5400 detected */
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/* Bypass control register */
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#define CIPHY_MII_BYPASS 0x12
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#define CIPHY_BYPASS_TX 0x8000 /* transmit disable */
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#define CIPHY_BYPASS_4B5B 0x4000 /* bypass the 4B5B encoder */
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#define CIPHY_BYPASS_SCRAM 0x2000 /* bypass scrambler */
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#define CIPHY_BYPASS_DSCAM 0x1000 /* bypass descrambler */
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#define CIPHY_BYPASS_PCSRX 0x0800 /* bypass PCS receive */
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#define CIPHY_BYPASS_PCSTX 0x0400 /* bypass PCS transmit */
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#define CIPHY_BYPASS_LFI 0x0200 /* bypass LFI timer */
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#define CIPHY_BYPASS_TXCLK 0x0100 /* enable transmit clock on LED4 pin */
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#define CIPHY_BYPASS_BCM5400_F 0x0080 /* force BCM5400 detect */
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#define CIPHY_BYPASS_BCM5400 0x0040 /* bypass BCM5400 detect */
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#define CIPHY_BYPASS_PAIRSWAP 0x0020 /* disable automatic pair swap */
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#define CIPHY_BYPASS_POLARITY 0x0010 /* disable polarity correction */
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#define CIPHY_BYPASS_PARALLEL 0x0008 /* parallel detect enable */
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#define CIPHY_BYPASS_PULSE 0x0004 /* disable pulse shaping filter */
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#define CIPHY_BYPASS_1000BNP 0x0002 /* disable 1000BT next page exchange */
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/* RX error count register */
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#define CIPHY_MII_RXERR 0x13
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/* False carrier sense count register */
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#define CIPHY_MII_FCSERR 0x14
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/* Ddisconnect error counter */
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#define CIPHY_MII_DISCERR 0x15
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/* 10baseT control/status register */
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#define CIPHY_MII_10BTCSR 0x16
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#define CIPHY_10BTCSR_DLIT 0x8000 /* Disable data link integrity test */
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#define CIPHY_10BTCSR_JABBER 0x4000 /* Disable jabber detect */
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#define CIPHY_10BTCSR_ECHO 0x2000 /* Disable echo mode */
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#define CIPHY_10BTCSR_SQE 0x1000 /* Disable signal quality error */
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#define CIPHY_10BTCSR_SQUENCH 0x0C00 /* Squelch control */
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#define CIPHY_10BTCSR_EOFERR 0x0100 /* End of Frame error */
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#define CIPHY_10BTCSR_DISC 0x0080 /* Disconnect status */
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#define CIPHY_10BTCSR_LINK 0x0040 /* current link state */
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#define CIPHY_10BTCSR_ITRIM 0x0038 /* current reference trim */
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#define CIPHY_10BTCSR_CSR 0x0006 /* CSR behavior control */
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#define CIPHY_SQUELCH_300MV 0x0000
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#define CIPHY_SQUELCH_197MV 0x0400
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#define CIPHY_SQUELCH_450MV 0x0800
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#define CIPHY_SQUELCH_RSVD 0x0C00
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#define CIPHY_ITRIM_PLUS2 0x0000
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#define CIPHY_ITRIM_PLUS4 0x0008
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#define CIPHY_ITRIM_PLUS6 0x0010
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#define CIPHY_ITRIM_PLUS6_ 0x0018
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#define CIPHY_ITRIM_MINUS4 0x0020
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#define CIPHY_ITRIM_MINUS4_ 0x0028
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#define CIPHY_ITRIM_MINUS2 0x0030
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#define CIPHY_ITRIM_ZERO 0x0038
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/* Extended PHY control register #1 */
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#define CIPHY_MII_ECTL1 0x17
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#define CIPHY_ECTL1_ACTIPHY 0x0020 /* Enable ActiPHY power saving */
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/* Extended PHY control register #2 */
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#define CIPHY_MII_ECTL2 0x18
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#define CIPHY_ECTL2_ERATE 0xE000 /* 10/1000 edge rate control */
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#define CIPHY_ECTL2_VTRIM 0x1C00 /* voltage reference trim */
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#define CIPHY_ECTL2_CABLELEN 0x000E /* Cable quality/length */
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#define CIPHY_ECTL2_ANALOGLOOP 0x0001 /* 1000BT analog loopback */
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#define CIPHY_CABLELEN_0TO10M 0x0000
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#define CIPHY_CABLELEN_10TO20M 0x0002
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#define CIPHY_CABLELEN_20TO40M 0x0004
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#define CIPHY_CABLELEN_40TO80M 0x0006
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#define CIPHY_CABLELEN_80TO100M 0x0008
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#define CIPHY_CABLELEN_100TO140M 0x000A
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#define CIPHY_CABLELEN_140TO180M 0x000C
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#define CIPHY_CABLELEN_OVER180M 0x000E
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/* Interrupt mask register */
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#define CIPHY_MII_IMR 0x19
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#define CIPHY_IMR_PINENABLE 0x8000 /* Interrupt pin enable */
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#define CIPHY_IMR_SPEED 0x4000 /* speed changed event */
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#define CIPHY_IMR_LINK 0x2000 /* link change/ActiPHY event */
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#define CIPHY_IMR_DPX 0x1000 /* duplex change event */
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#define CIPHY_IMR_ANEGERR 0x0800 /* autoneg error event */
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#define CIPHY_IMR_ANEGDONE 0x0400 /* autoneg done event */
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#define CIPHY_IMR_NPRX 0x0200 /* page received event */
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#define CIPHY_IMR_SYMERR 0x0100 /* symbol error event */
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#define CIPHY_IMR_LOCKERR 0x0080 /* descrambler lock lost event */
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#define CIPHY_IMR_XOVER 0x0040 /* MDI crossover change event */
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#define CIPHY_IMR_POLARITY 0x0020 /* polarity change event */
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#define CIPHY_IMR_JABBER 0x0010 /* jabber detect event */
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#define CIPHY_IMR_SSDERR 0x0008 /* false carrier detect event */
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#define CIPHY_IMR_ESDERR 0x0004 /* parallel detect error event */
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#define CIPHY_IMR_MASTERSLAVE 0x0002 /* master/slave resolve done event */
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#define CIPHY_IMR_RXERR 0x0001 /* RX error event */
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/* Interrupt status register */
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#define CIPHY_MII_ISR 0x1A
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#define CIPHY_ISR_IPENDING 0x8000 /* Interrupt is pending */
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#define CIPHY_ISR_SPEED 0x4000 /* speed changed event */
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#define CIPHY_ISR_LINK 0x2000 /* link change/ActiPHY event */
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#define CIPHY_ISR_DPX 0x1000 /* duplex change event */
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#define CIPHY_ISR_ANEGERR 0x0800 /* autoneg error event */
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#define CIPHY_ISR_ANEGDONE 0x0400 /* autoneg done event */
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#define CIPHY_ISR_NPRX 0x0200 /* page received event */
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#define CIPHY_ISR_SYMERR 0x0100 /* symbol error event */
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#define CIPHY_ISR_LOCKERR 0x0080 /* descrambler lock lost event */
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#define CIPHY_ISR_XOVER 0x0040 /* MDI crossover change event */
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#define CIPHY_ISR_POLARITY 0x0020 /* polarity change event */
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#define CIPHY_ISR_JABBER 0x0010 /* jabber detect event */
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#define CIPHY_ISR_SSDERR 0x0008 /* false carrier detect event */
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#define CIPHY_ISR_ESDERR 0x0004 /* parallel detect error event */
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#define CIPHY_ISR_MASTERSLAVE 0x0002 /* master/slave resolve done event */
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#define CIPHY_ISR_RXERR 0x0001 /* RX error event */
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/* LED control register */
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#define CIPHY_MII_LED 0x1B
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#define CIPHY_LED_LINK10FORCE 0x8000 /* Force on link10 LED */
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#define CIPHY_LED_LINK10DIS 0x4000 /* Disable link10 LED */
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#define CIPHY_LED_LINK100FORCE 0x2000 /* Force on link10 LED */
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#define CIPHY_LED_LINK100DIS 0x1000 /* Disable link100 LED */
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#define CIPHY_LED_LINK1000FORCE 0x0800 /* Force on link1000 LED */
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#define CIPHY_LED_LINK1000DIS 0x0400 /* Disable link1000 LED */
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#define CIPHY_LED_FDXFORCE 0x0200 /* Force on duplex LED */
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#define CIPHY_LED_FDXDIS 0x0100 /* Disable duplex LED */
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#define CIPHY_LED_ACTFORCE 0x0080 /* Force on activity LED */
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#define CIPHY_LED_ACTDIS 0x0040 /* Disable activity LED */
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#define CIPHY_LED_PULSE 0x0008 /* LED pulse enable */
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#define CIPHY_LED_LINKACTBLINK 0x0004 /* enable link/activity LED blink */
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#define CIPHY_LED_BLINKRATE 0x0002 /* blink rate 0=10hz, 1=5hz */
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/* Auxilliary control and status register */
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#define CIPHY_MII_AUXCSR 0x1C
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#define CIPHY_AUXCSR_ANEGDONE 0x8000 /* Autoneg complete */
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#define CIPHY_AUXCSR_ANEGOFF 0x4000 /* Autoneg disabled */
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#define CIPHY_AUXCSR_XOVER 0x2000 /* MDI/MDI-X crossover indication */
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#define CIPHY_AUXCSR_PAIRSWAP 0x1000 /* pair swap indication */
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#define CIPHY_AUXCSR_APOLARITY 0x0800 /* polarity inversion pair A */
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#define CIPHY_AUXCSR_BPOLARITY 0x0400 /* polarity inversion pair B */
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#define CIPHY_AUXCSR_CPOLARITY 0x0200 /* polarity inversion pair C */
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#define CIPHY_AUXCSR_DPOLARITY 0x0100 /* polarity inversion pair D */
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#define CIPHY_AUXCSR_FDX 0x0020 /* duplex 1=full, 0=half */
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#define CIPHY_AUXCSR_SPEED 0x0018 /* speed */
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#define CIPHY_AUXCSR_MDPPS 0x0004 /* No idea, not documented */
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#define CIPHY_AUXCSR_STICKYREST 0x0002 /* reset clears sticky bits */
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#define CIPHY_SPEED10 0x0000
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#define CIPHY_SPEED100 0x0008
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#define CIPHY_SPEED1000 0x0010
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/* Delay skew status register */
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#define CIPHY_MII_DSKEW 0x1D
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#define CIPHY_DSKEW_PAIRA 0x7000 /* Pair A skew in symbol times */
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#define CIPHY_DSKEW_PAIRB 0x0700 /* Pair B skew in symbol times */
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#define CIPHY_DSKEW_PAIRC 0x0070 /* Pair C skew in symbol times */
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#define CIPHY_DSKEW_PAIRD 0x0007 /* Pair D skew in symbol times */
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#endif /* _DEV_CIPHY_MIIREG_H_ */
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