a324b7f71d
When turning IBRS mitigation using sysctl, as opposed to loader tunable, send IPI to tweak MSR on all cores. Right now code only performed MSR write onr the CPU where sysctl was run. Properly report hw.ibrs_active for IBRS_ALL. Split hw_ibrs_ibpb_active out from ibrs_active, to keep the current semantic of guiding kernel entry and exit handlers. Reported and tested by: mav Sponsored by: The FreeBSD Foundation MFC after: 1 week
605 lines
15 KiB
C
605 lines
15 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2006-2008 Stanislav Sedov <stas@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/conf.h>
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#include <sys/fcntl.h>
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#include <sys/ioccom.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/priv.h>
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#include <sys/proc.h>
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#include <sys/queue.h>
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#include <sys/sched.h>
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#include <sys/kernel.h>
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#include <sys/sysctl.h>
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#include <sys/uio.h>
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#include <sys/pcpu.h>
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#include <sys/smp.h>
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#include <sys/pmckern.h>
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#include <sys/cpuctl.h>
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#include <vm/vm.h>
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#include <vm/vm_param.h>
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#include <vm/pmap.h>
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#include <machine/cpufunc.h>
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#include <machine/md_var.h>
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#include <machine/specialreg.h>
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#include <x86/ucode.h>
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static d_open_t cpuctl_open;
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static d_ioctl_t cpuctl_ioctl;
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#define CPUCTL_VERSION 1
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#ifdef CPUCTL_DEBUG
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# define DPRINTF(format,...) printf(format, __VA_ARGS__);
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#else
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# define DPRINTF(...)
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#endif
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#define UCODE_SIZE_MAX (4 * 1024 * 1024)
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static int cpuctl_do_msr(int cpu, cpuctl_msr_args_t *data, u_long cmd,
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struct thread *td);
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static int cpuctl_do_cpuid(int cpu, cpuctl_cpuid_args_t *data,
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struct thread *td);
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static int cpuctl_do_cpuid_count(int cpu, cpuctl_cpuid_count_args_t *data,
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struct thread *td);
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static int cpuctl_do_eval_cpu_features(int cpu, struct thread *td);
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static int cpuctl_do_update(int cpu, cpuctl_update_args_t *data,
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struct thread *td);
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static int update_intel(int cpu, cpuctl_update_args_t *args,
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struct thread *td);
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static int update_amd(int cpu, cpuctl_update_args_t *args, struct thread *td);
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static int update_via(int cpu, cpuctl_update_args_t *args,
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struct thread *td);
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static struct cdev **cpuctl_devs;
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static MALLOC_DEFINE(M_CPUCTL, "cpuctl", "CPUCTL buffer");
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static struct cdevsw cpuctl_cdevsw = {
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.d_version = D_VERSION,
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.d_open = cpuctl_open,
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.d_ioctl = cpuctl_ioctl,
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.d_name = "cpuctl",
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};
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/*
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* This function checks if specified cpu enabled or not.
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*/
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static int
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cpu_enabled(int cpu)
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{
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return (pmc_cpu_is_disabled(cpu) == 0);
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}
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/*
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* Check if the current thread is bound to a specific cpu.
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*/
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static int
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cpu_sched_is_bound(struct thread *td)
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{
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int ret;
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thread_lock(td);
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ret = sched_is_bound(td);
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thread_unlock(td);
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return (ret);
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}
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/*
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* Switch to target cpu to run.
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*/
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static void
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set_cpu(int cpu, struct thread *td)
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{
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KASSERT(cpu >= 0 && cpu <= mp_maxid && cpu_enabled(cpu),
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("[cpuctl,%d]: bad cpu number %d", __LINE__, cpu));
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thread_lock(td);
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sched_bind(td, cpu);
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thread_unlock(td);
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KASSERT(td->td_oncpu == cpu,
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("[cpuctl,%d]: cannot bind to target cpu %d on cpu %d", __LINE__,
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cpu, td->td_oncpu));
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}
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static void
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restore_cpu(int oldcpu, int is_bound, struct thread *td)
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{
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KASSERT(oldcpu >= 0 && oldcpu <= mp_maxid && cpu_enabled(oldcpu),
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("[cpuctl,%d]: bad cpu number %d", __LINE__, oldcpu));
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thread_lock(td);
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if (is_bound == 0)
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sched_unbind(td);
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else
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sched_bind(td, oldcpu);
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thread_unlock(td);
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}
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int
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cpuctl_ioctl(struct cdev *dev, u_long cmd, caddr_t data,
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int flags, struct thread *td)
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{
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int cpu, ret;
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cpu = dev2unit(dev);
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if (cpu > mp_maxid || !cpu_enabled(cpu)) {
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DPRINTF("[cpuctl,%d]: bad cpu number %d\n", __LINE__, cpu);
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return (ENXIO);
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}
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/* Require write flag for "write" requests. */
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if ((cmd == CPUCTL_MSRCBIT || cmd == CPUCTL_MSRSBIT ||
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cmd == CPUCTL_UPDATE || cmd == CPUCTL_WRMSR ||
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cmd == CPUCTL_EVAL_CPU_FEATURES) &&
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(flags & FWRITE) == 0)
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return (EPERM);
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switch (cmd) {
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case CPUCTL_RDMSR:
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ret = cpuctl_do_msr(cpu, (cpuctl_msr_args_t *)data, cmd, td);
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break;
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case CPUCTL_MSRSBIT:
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case CPUCTL_MSRCBIT:
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case CPUCTL_WRMSR:
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ret = priv_check(td, PRIV_CPUCTL_WRMSR);
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if (ret != 0)
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goto fail;
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ret = cpuctl_do_msr(cpu, (cpuctl_msr_args_t *)data, cmd, td);
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break;
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case CPUCTL_CPUID:
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ret = cpuctl_do_cpuid(cpu, (cpuctl_cpuid_args_t *)data, td);
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break;
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case CPUCTL_UPDATE:
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ret = priv_check(td, PRIV_CPUCTL_UPDATE);
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if (ret != 0)
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goto fail;
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ret = cpuctl_do_update(cpu, (cpuctl_update_args_t *)data, td);
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break;
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case CPUCTL_CPUID_COUNT:
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ret = cpuctl_do_cpuid_count(cpu,
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(cpuctl_cpuid_count_args_t *)data, td);
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break;
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case CPUCTL_EVAL_CPU_FEATURES:
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ret = cpuctl_do_eval_cpu_features(cpu, td);
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break;
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default:
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ret = EINVAL;
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break;
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}
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fail:
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return (ret);
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}
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/*
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* Actually perform cpuid operation.
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*/
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static int
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cpuctl_do_cpuid_count(int cpu, cpuctl_cpuid_count_args_t *data,
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struct thread *td)
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{
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int is_bound = 0;
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int oldcpu;
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KASSERT(cpu >= 0 && cpu <= mp_maxid,
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("[cpuctl,%d]: bad cpu number %d", __LINE__, cpu));
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/* Explicitly clear cpuid data to avoid returning stale info. */
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bzero(data->data, sizeof(data->data));
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DPRINTF("[cpuctl,%d]: retrieving cpuid lev %#0x type %#0x for %d cpu\n",
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__LINE__, data->level, data->level_type, cpu);
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#ifdef __i386__
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if (cpu_id == 0)
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return (ENODEV);
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#endif
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oldcpu = td->td_oncpu;
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is_bound = cpu_sched_is_bound(td);
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set_cpu(cpu, td);
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cpuid_count(data->level, data->level_type, data->data);
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restore_cpu(oldcpu, is_bound, td);
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return (0);
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}
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static int
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cpuctl_do_cpuid(int cpu, cpuctl_cpuid_args_t *data, struct thread *td)
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{
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cpuctl_cpuid_count_args_t cdata;
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int error;
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cdata.level = data->level;
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/* Override the level type. */
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cdata.level_type = 0;
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error = cpuctl_do_cpuid_count(cpu, &cdata, td);
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bcopy(cdata.data, data->data, sizeof(data->data)); /* Ignore error */
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return (error);
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}
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/*
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* Actually perform MSR operations.
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*/
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static int
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cpuctl_do_msr(int cpu, cpuctl_msr_args_t *data, u_long cmd, struct thread *td)
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{
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uint64_t reg;
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int is_bound = 0;
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int oldcpu;
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int ret;
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KASSERT(cpu >= 0 && cpu <= mp_maxid,
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("[cpuctl,%d]: bad cpu number %d", __LINE__, cpu));
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/*
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* Explicitly clear cpuid data to avoid returning stale
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* info
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*/
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DPRINTF("[cpuctl,%d]: operating on MSR %#0x for %d cpu\n", __LINE__,
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data->msr, cpu);
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#ifdef __i386__
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if ((cpu_feature & CPUID_MSR) == 0)
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return (ENODEV);
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#endif
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oldcpu = td->td_oncpu;
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is_bound = cpu_sched_is_bound(td);
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set_cpu(cpu, td);
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if (cmd == CPUCTL_RDMSR) {
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data->data = 0;
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ret = rdmsr_safe(data->msr, &data->data);
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} else if (cmd == CPUCTL_WRMSR) {
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ret = wrmsr_safe(data->msr, data->data);
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} else if (cmd == CPUCTL_MSRSBIT) {
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critical_enter();
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ret = rdmsr_safe(data->msr, ®);
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if (ret == 0)
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ret = wrmsr_safe(data->msr, reg | data->data);
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critical_exit();
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} else if (cmd == CPUCTL_MSRCBIT) {
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critical_enter();
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ret = rdmsr_safe(data->msr, ®);
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if (ret == 0)
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ret = wrmsr_safe(data->msr, reg & ~data->data);
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critical_exit();
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} else
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panic("[cpuctl,%d]: unknown operation requested: %lu",
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__LINE__, cmd);
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restore_cpu(oldcpu, is_bound, td);
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return (ret);
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}
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/*
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* Actually perform microcode update.
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*/
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static int
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cpuctl_do_update(int cpu, cpuctl_update_args_t *data, struct thread *td)
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{
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cpuctl_cpuid_args_t args = {
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.level = 0,
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};
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char vendor[13];
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int ret;
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KASSERT(cpu >= 0 && cpu <= mp_maxid,
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("[cpuctl,%d]: bad cpu number %d", __LINE__, cpu));
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DPRINTF("[cpuctl,%d]: XXX %d", __LINE__, cpu);
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ret = cpuctl_do_cpuid(cpu, &args, td);
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if (ret != 0)
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return (ret);
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((uint32_t *)vendor)[0] = args.data[1];
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((uint32_t *)vendor)[1] = args.data[3];
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((uint32_t *)vendor)[2] = args.data[2];
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vendor[12] = '\0';
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if (strncmp(vendor, INTEL_VENDOR_ID, sizeof(INTEL_VENDOR_ID)) == 0)
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ret = update_intel(cpu, data, td);
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else if(strncmp(vendor, AMD_VENDOR_ID, sizeof(AMD_VENDOR_ID)) == 0)
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ret = update_amd(cpu, data, td);
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else if(strncmp(vendor, CENTAUR_VENDOR_ID, sizeof(CENTAUR_VENDOR_ID))
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== 0)
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ret = update_via(cpu, data, td);
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else
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ret = ENXIO;
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return (ret);
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}
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struct ucode_update_data {
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void *ptr;
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int cpu;
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int ret;
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};
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static void
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ucode_intel_load_rv(void *arg)
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{
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struct ucode_update_data *d;
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d = arg;
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if (PCPU_GET(cpuid) == d->cpu)
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d->ret = ucode_intel_load(d->ptr, true, NULL, NULL);
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}
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static int
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update_intel(int cpu, cpuctl_update_args_t *args, struct thread *td)
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{
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struct ucode_update_data d;
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void *ptr;
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int is_bound, oldcpu, ret;
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if (args->size == 0 || args->data == NULL) {
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DPRINTF("[cpuctl,%d]: zero-sized firmware image", __LINE__);
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return (EINVAL);
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}
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if (args->size > UCODE_SIZE_MAX) {
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DPRINTF("[cpuctl,%d]: firmware image too large", __LINE__);
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return (EINVAL);
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}
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/*
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* 16 byte alignment required. Rely on the fact that
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* malloc(9) always returns the pointer aligned at least on
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* the size of the allocation.
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*/
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ptr = malloc(args->size + 16, M_CPUCTL, M_WAITOK);
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if (copyin(args->data, ptr, args->size) != 0) {
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DPRINTF("[cpuctl,%d]: copyin %p->%p of %zd bytes failed",
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__LINE__, args->data, ptr, args->size);
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ret = EFAULT;
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goto out;
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}
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oldcpu = td->td_oncpu;
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is_bound = cpu_sched_is_bound(td);
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set_cpu(cpu, td);
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d.ptr = ptr;
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d.cpu = cpu;
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smp_rendezvous(NULL, ucode_intel_load_rv, NULL, &d);
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restore_cpu(oldcpu, is_bound, td);
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ret = d.ret;
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/*
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* Replace any existing update. This ensures that the new update
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* will be reloaded automatically during ACPI resume.
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*/
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if (ret == 0)
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ptr = ucode_update(ptr);
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out:
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free(ptr, M_CPUCTL);
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return (ret);
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}
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/*
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* NB: MSR 0xc0010020, MSR_K8_UCODE_UPDATE, is not documented by AMD.
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* Coreboot, illumos and Linux source code was used to understand
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* its workings.
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*/
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static void
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amd_ucode_wrmsr(void *ucode_ptr)
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{
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uint32_t tmp[4];
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wrmsr_safe(MSR_K8_UCODE_UPDATE, (uintptr_t)ucode_ptr);
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do_cpuid(0, tmp);
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}
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static int
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update_amd(int cpu, cpuctl_update_args_t *args, struct thread *td)
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{
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void *ptr;
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int ret;
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if (args->size == 0 || args->data == NULL) {
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DPRINTF("[cpuctl,%d]: zero-sized firmware image", __LINE__);
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return (EINVAL);
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}
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if (args->size > UCODE_SIZE_MAX) {
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DPRINTF("[cpuctl,%d]: firmware image too large", __LINE__);
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return (EINVAL);
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}
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/*
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* 16 byte alignment required. Rely on the fact that
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* malloc(9) always returns the pointer aligned at least on
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* the size of the allocation.
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*/
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ptr = malloc(args->size + 16, M_CPUCTL, M_ZERO | M_WAITOK);
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if (copyin(args->data, ptr, args->size) != 0) {
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DPRINTF("[cpuctl,%d]: copyin %p->%p of %zd bytes failed",
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__LINE__, args->data, ptr, args->size);
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ret = EFAULT;
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goto fail;
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}
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smp_rendezvous(NULL, amd_ucode_wrmsr, NULL, ptr);
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ret = 0;
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fail:
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free(ptr, M_CPUCTL);
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return (ret);
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}
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static int
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update_via(int cpu, cpuctl_update_args_t *args, struct thread *td)
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{
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void *ptr;
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uint64_t rev0, rev1, res;
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uint32_t tmp[4];
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int is_bound;
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int oldcpu;
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int ret;
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if (args->size == 0 || args->data == NULL) {
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DPRINTF("[cpuctl,%d]: zero-sized firmware image", __LINE__);
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return (EINVAL);
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}
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if (args->size > UCODE_SIZE_MAX) {
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DPRINTF("[cpuctl,%d]: firmware image too large", __LINE__);
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return (EINVAL);
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}
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/*
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* 4 byte alignment required.
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*/
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ptr = malloc(args->size, M_CPUCTL, M_WAITOK);
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if (copyin(args->data, ptr, args->size) != 0) {
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DPRINTF("[cpuctl,%d]: copyin %p->%p of %zd bytes failed",
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__LINE__, args->data, ptr, args->size);
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ret = EFAULT;
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goto fail;
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}
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oldcpu = td->td_oncpu;
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is_bound = cpu_sched_is_bound(td);
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set_cpu(cpu, td);
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critical_enter();
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rdmsr_safe(MSR_BIOS_SIGN, &rev0); /* Get current microcode revision. */
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/*
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* Perform update.
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*/
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wrmsr_safe(MSR_BIOS_UPDT_TRIG, (uintptr_t)(ptr));
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do_cpuid(1, tmp);
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/*
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|
* Result are in low byte of MSR FCR5:
|
|
* 0x00: No update has been attempted since RESET.
|
|
* 0x01: The last attempted update was successful.
|
|
* 0x02: The last attempted update was unsuccessful due to a bad
|
|
* environment. No update was loaded and any preexisting
|
|
* patches are still active.
|
|
* 0x03: The last attempted update was not applicable to this processor.
|
|
* No update was loaded and any preexisting patches are still
|
|
* active.
|
|
* 0x04: The last attempted update was not successful due to an invalid
|
|
* update data block. No update was loaded and any preexisting
|
|
* patches are still active
|
|
*/
|
|
rdmsr_safe(0x1205, &res);
|
|
res &= 0xff;
|
|
critical_exit();
|
|
rdmsr_safe(MSR_BIOS_SIGN, &rev1); /* Get new microcode revision. */
|
|
restore_cpu(oldcpu, is_bound, td);
|
|
|
|
DPRINTF("[cpu,%d]: rev0=%x rev1=%x res=%x\n", __LINE__,
|
|
(unsigned)(rev0 >> 32), (unsigned)(rev1 >> 32), (unsigned)res);
|
|
|
|
if (res != 0x01)
|
|
ret = EINVAL;
|
|
else
|
|
ret = 0;
|
|
fail:
|
|
free(ptr, M_CPUCTL);
|
|
return (ret);
|
|
}
|
|
|
|
static int
|
|
cpuctl_do_eval_cpu_features(int cpu, struct thread *td)
|
|
{
|
|
int is_bound = 0;
|
|
int oldcpu;
|
|
|
|
KASSERT(cpu >= 0 && cpu <= mp_maxid,
|
|
("[cpuctl,%d]: bad cpu number %d", __LINE__, cpu));
|
|
|
|
#ifdef __i386__
|
|
if (cpu_id == 0)
|
|
return (ENODEV);
|
|
#endif
|
|
oldcpu = td->td_oncpu;
|
|
is_bound = cpu_sched_is_bound(td);
|
|
set_cpu(cpu, td);
|
|
identify_cpu1();
|
|
identify_cpu2();
|
|
restore_cpu(oldcpu, is_bound, td);
|
|
hw_ibrs_recalculate(true);
|
|
hw_ssb_recalculate(true);
|
|
#ifdef __amd64__
|
|
amd64_syscall_ret_flush_l1d_recalc();
|
|
pmap_allow_2m_x_ept_recalculate();
|
|
#endif
|
|
hw_mds_recalculate();
|
|
x86_taa_recalculate();
|
|
printcpuinfo();
|
|
return (0);
|
|
}
|
|
|
|
|
|
int
|
|
cpuctl_open(struct cdev *dev, int flags, int fmt __unused, struct thread *td)
|
|
{
|
|
int ret = 0;
|
|
int cpu;
|
|
|
|
cpu = dev2unit(dev);
|
|
if (cpu > mp_maxid || !cpu_enabled(cpu)) {
|
|
DPRINTF("[cpuctl,%d]: incorrect cpu number %d\n", __LINE__,
|
|
cpu);
|
|
return (ENXIO);
|
|
}
|
|
if (flags & FWRITE)
|
|
ret = securelevel_gt(td->td_ucred, 0);
|
|
return (ret);
|
|
}
|
|
|
|
static int
|
|
cpuctl_modevent(module_t mod __unused, int type, void *data __unused)
|
|
{
|
|
int cpu;
|
|
|
|
switch(type) {
|
|
case MOD_LOAD:
|
|
if (bootverbose)
|
|
printf("cpuctl: access to MSR registers/cpuid info.\n");
|
|
cpuctl_devs = malloc(sizeof(*cpuctl_devs) * (mp_maxid + 1), M_CPUCTL,
|
|
M_WAITOK | M_ZERO);
|
|
CPU_FOREACH(cpu)
|
|
if (cpu_enabled(cpu))
|
|
cpuctl_devs[cpu] = make_dev(&cpuctl_cdevsw, cpu,
|
|
UID_ROOT, GID_KMEM, 0640, "cpuctl%d", cpu);
|
|
break;
|
|
case MOD_UNLOAD:
|
|
CPU_FOREACH(cpu) {
|
|
if (cpuctl_devs[cpu] != NULL)
|
|
destroy_dev(cpuctl_devs[cpu]);
|
|
}
|
|
free(cpuctl_devs, M_CPUCTL);
|
|
break;
|
|
case MOD_SHUTDOWN:
|
|
break;
|
|
default:
|
|
return (EOPNOTSUPP);
|
|
}
|
|
return (0);
|
|
}
|
|
|
|
DEV_MODULE(cpuctl, cpuctl_modevent, NULL);
|
|
MODULE_VERSION(cpuctl, CPUCTL_VERSION);
|