142f4ed4b1
the alternate status and the control registers. Remove the local version of ata_reset. Add support for the ADI Pronghorn Metro boards. They use CS3 and CS4 instead of Avila's CS1 and CS2.
592 lines
20 KiB
C
592 lines
20 KiB
C
/* $NetBSD: ixp425reg.h,v 1.19 2005/12/11 12:16:51 christos Exp $ */
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/*
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* Copyright (c) 2003
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* Ichiro FUKUHARA <ichiro@ichiro.org>.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Ichiro FUKUHARA.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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#ifndef _IXP425REG_H_
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#define _IXP425REG_H_
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/*
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* Physical memory map for the Intel IXP425
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*/
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/*
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* CC00 00FF ---------------------------
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* SDRAM Configuration Registers
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* CC00 0000 ---------------------------
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*
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* C800 BFFF ---------------------------
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* System and Peripheral Registers
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* C800 0000 ---------------------------
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* Expansion Bus Configuration Registers
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* C400 0000 ---------------------------
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* PCI Configuration and Status Registers
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* C000 0000 ---------------------------
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*
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* 6400 0000 ---------------------------
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* Queue manager
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* 6000 0000 ---------------------------
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* Expansion Bus Data
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* 5000 0000 ---------------------------
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* PCI Data
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* 4800 0000 ---------------------------
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*
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* 4000 0000 ---------------------------
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* SDRAM
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* 1000 0000 ---------------------------
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*/
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/*
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* Virtual memory map for the Intel IXP425 integrated devices
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*/
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/*
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* FFFF FFFF ---------------------------
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*
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* FC00 0000 ---------------------------
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* PCI Data (memory space)
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* F800 0000 ---------------------------
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*
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* F020 1000 ---------------------------
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* SDRAM Controller
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* F020 0000 ---------------------------
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*
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* F001 2000 ---------------------------
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* PCI Configuration and Status Registers
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* F001 1000 ---------------------------
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* Expansion bus Configuration Registers
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* F001 0000 ---------------------------
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* System and Peripheral Registers
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* VA F000 0000 = PA C800 0000 (SIZE 0x10000)
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* F000 0000 ---------------------------
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*
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* 0000 0000 ---------------------------
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*
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*/
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/* Physical/Virtual address for I/O space */
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#define IXP425_IO_VBASE 0xf0000000UL
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#define IXP425_IO_HWBASE 0xc8000000UL
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#define IXP425_IO_SIZE 0x00010000UL
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/* Offset */
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#define IXP425_UART0_OFFSET 0x00000000UL
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#define IXP425_UART1_OFFSET 0x00001000UL
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#define IXP425_PMC_OFFSET 0x00002000UL
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#define IXP425_INTR_OFFSET 0x00003000UL
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#define IXP425_GPIO_OFFSET 0x00004000UL
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#define IXP425_TIMER_OFFSET 0x00005000UL
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#define IXP425_NPE_A_OFFSET 0x00006000UL /* Not User Programmable */
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#define IXP425_NPE_B_OFFSET 0x00007000UL /* Not User Programmable */
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#define IXP425_NPE_C_OFFSET 0x00008000UL /* Not User Programmable */
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#define IXP425_MAC_A_OFFSET 0x00009000UL
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#define IXP425_MAC_B_OFFSET 0x0000a000UL
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#define IXP425_USB_OFFSET 0x0000b000UL
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#define IXP425_REG_SIZE 0x1000
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/*
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* UART
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* UART0 0xc8000000
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* UART1 0xc8001000
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*
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*/
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/* I/O space */
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#define IXP425_UART0_HWBASE (IXP425_IO_HWBASE + IXP425_UART0_OFFSET)
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#define IXP425_UART1_HWBASE (IXP425_IO_HWBASE + IXP425_UART1_OFFSET)
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#define IXP425_UART0_VBASE (IXP425_IO_VBASE + IXP425_UART0_OFFSET)
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/* 0xf0000000 */
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#define IXP425_UART1_VBASE (IXP425_IO_VBASE + IXP425_UART1_OFFSET)
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/* 0xf0001000 */
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#define IXP425_UART_FREQ 14745600
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#define IXP425_UART_IER 0x01 /* interrupt enable register */
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#define IXP425_UART_IER_RTOIE 0x10 /* receiver timeout interrupt enable */
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#define IXP425_UART_IER_UUE 0x40 /* UART Unit enable */
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/*#define IXP4XX_COM_NPORTS 8*/
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/*
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* Timers
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*
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*/
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#define IXP425_TIMER_HWBASE (IXP425_IO_HWBASE + IXP425_TIMER_OFFSET)
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#define IXP425_TIMER_VBASE (IXP425_IO_VBASE + IXP425_TIMER_OFFSET)
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#define IXP425_OST_TS 0x0000
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#define IXP425_OST_TIM0 0x0004
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#define IXP425_OST_TIM1 0x000C
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#define IXP425_OST_TIM0_RELOAD 0x0008
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#define IXP425_OST_TIM1_RELOAD 0x0010
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#define TIMERRELOAD_MASK 0xFFFFFFFC
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#define OST_ONESHOT_EN (1U << 1)
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#define OST_TIMER_EN (1U << 0)
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#define IXP425_OST_STATUS 0x0020
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#define OST_WARM_RESET (1U << 4)
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#define OST_WDOG_INT (1U << 3)
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#define OST_TS_INT (1U << 2)
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#define OST_TIM1_INT (1U << 1)
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#define OST_TIM0_INT (1U << 0)
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#define IXP425_OST_WDOG 0x0014
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#define IXP425_OST_WDOG_ENAB 0x0018
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#define IXP425_OST_WDOG_KEY 0x001c
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#define OST_WDOG_KEY_MAJICK 0x482e
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#define OST_WDOG_ENAB_RST_ENA (1u << 0)
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#define OST_WDOG_ENAB_INT_ENA (1u << 1)
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#define OST_WDOG_ENAB_CNT_ENA (1u << 2)
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/*
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* Interrupt Controller Unit.
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* PA 0xc8003000
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*/
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#define IXP425_IRQ_HWBASE IXP425_IO_HWBASE + IXP425_INTR_OFFSET
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#define IXP425_IRQ_VBASE IXP425_IO_VBASE + IXP425_INTR_OFFSET
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/* 0xf0003000 */
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#define IXP425_IRQ_SIZE 0x00000020UL
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#define IXP425_INT_STATUS (IXP425_IRQ_VBASE + 0x00)
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#define IXP425_INT_ENABLE (IXP425_IRQ_VBASE + 0x04)
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#define IXP425_INT_SELECT (IXP425_IRQ_VBASE + 0x08)
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#define IXP425_IRQ_STATUS (IXP425_IRQ_VBASE + 0x0C)
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#define IXP425_FIQ_STATUS (IXP425_IRQ_VBASE + 0x10)
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#define IXP425_INT_PRTY (IXP425_IRQ_VBASE + 0x14)
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#define IXP425_IRQ_ENC (IXP425_IRQ_VBASE + 0x18)
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#define IXP425_FIQ_ENC (IXP425_IRQ_VBASE + 0x1C)
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#define IXP425_INT_SW1 31 /* SW Interrupt 1 */
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#define IXP425_INT_SW0 30 /* SW Interrupt 0 */
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#define IXP425_INT_GPIO_12 29 /* GPIO 12 */
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#define IXP425_INT_GPIO_11 28 /* GPIO 11 */
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#define IXP425_INT_GPIO_10 27 /* GPIO 11 */
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#define IXP425_INT_GPIO_9 26 /* GPIO 9 */
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#define IXP425_INT_GPIO_8 25 /* GPIO 8 */
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#define IXP425_INT_GPIO_7 24 /* GPIO 7 */
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#define IXP425_INT_GPIO_6 23 /* GPIO 6 */
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#define IXP425_INT_GPIO_5 22 /* GPIO 5 */
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#define IXP425_INT_GPIO_4 21 /* GPIO 4 */
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#define IXP425_INT_GPIO_3 20 /* GPIO 3 */
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#define IXP425_INT_GPIO_2 19 /* GPIO 2 */
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#define IXP425_INT_XSCALE_PMU 18 /* XScale PMU */
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#define IXP425_INT_AHB_PMU 17 /* AHB PMU */
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#define IXP425_INT_WDOG 16 /* Watchdog Timer */
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#define IXP425_INT_UART0 15 /* HighSpeed UART */
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#define IXP425_INT_STAMP 14 /* Timestamp Timer */
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#define IXP425_INT_UART1 13 /* Console UART */
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#define IXP425_INT_USB 12 /* USB */
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#define IXP425_INT_TMR1 11 /* General-Purpose Timer1 */
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#define IXP425_INT_PCIDMA2 10 /* PCI DMA Channel 2 */
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#define IXP425_INT_PCIDMA1 9 /* PCI DMA Channel 1 */
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#define IXP425_INT_PCIINT 8 /* PCI Interrupt */
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#define IXP425_INT_GPIO_1 7 /* GPIO 1 */
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#define IXP425_INT_GPIO_0 6 /* GPIO 0 */
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#define IXP425_INT_TMR0 5 /* General-Purpose Timer0 */
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#define IXP425_INT_QUE33_64 4 /* Queue Manager 33-64 */
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#define IXP425_INT_QUE1_32 3 /* Queue Manager 1-32 */
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#define IXP425_INT_NPE_C 2 /* NPE C */
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#define IXP425_INT_NPE_B 1 /* NPE B */
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#define IXP425_INT_NPE_A 0 /* NPE A */
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/*
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* software interrupt
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*/
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#define IXP425_INT_bit31 31
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#define IXP425_INT_bit30 30
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#define IXP425_INT_bit14 14
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#define IXP425_INT_bit11 11
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#define IXP425_INT_HWMASK (0xffffffff & \
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~((1 << IXP425_INT_bit31) | \
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(1 << IXP425_INT_bit30) | \
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(1 << IXP425_INT_bit14) | \
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(1 << IXP425_INT_bit11)))
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#define IXP425_INT_GPIOMASK (0x3ff800c0u)
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/*
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* GPIO
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*/
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#define IXP425_GPIO_HWBASE IXP425_IO_HWBASE + IXP425_GPIO_OFFSET
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#define IXP425_GPIO_VBASE IXP425_IO_VBASE + IXP425_GPIO_OFFSET
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/* 0xf0004000 */
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#define IXP425_GPIO_SIZE 0x00000020UL
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#define IXP425_GPIO_GPOUTR 0x00
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#define IXP425_GPIO_GPOER 0x04
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#define IXP425_GPIO_GPINR 0x08
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#define IXP425_GPIO_GPISR 0x0c
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#define IXP425_GPIO_GPIT1R 0x10
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#define IXP425_GPIO_GPIT2R 0x14
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#define IXP425_GPIO_GPCLKR 0x18
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# define GPCLKR_MUX14 (1U << 8)
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# define GPCLKR_CLK0TC_SHIFT 4
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# define GPCLKR_CLK0DC_SHIFT 0
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/* GPIO Output */
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#define GPOUT_ON 0x1
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#define GPOUT_OFF 0x0
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/* GPIO direction */
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#define GPOER_INPUT 0x1
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#define GPOER_OUTPUT 0x0
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/* GPIO Type bits */
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#define GPIO_TYPE_ACT_HIGH 0x0
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#define GPIO_TYPE_ACT_LOW 0x1
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#define GPIO_TYPE_EDG_RISING 0x2
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#define GPIO_TYPE_EDG_FALLING 0x3
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#define GPIO_TYPE_TRANSITIONAL 0x4
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#define GPIO_TYPE_MASK 0x7
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#define GPIO_TYPE(b,v) ((v) << (((b) & 0x7) * 3))
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#define GPIO_TYPE_REG(b) (((b)&8)?IXP425_GPIO_GPIT2R:IXP425_GPIO_GPIT1R)
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/*
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* Expansion Bus Configuration Space.
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*/
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#define IXP425_EXP_HWBASE 0xc4000000UL
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#define IXP425_EXP_VBASE (IXP425_IO_VBASE + IXP425_IO_SIZE)
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/* 0xf0010000 */
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#define IXP425_EXP_SIZE IXP425_REG_SIZE /* 0x1000 */
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/* offset */
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#define EXP_TIMING_CS0_OFFSET 0x0000
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#define EXP_TIMING_CS1_OFFSET 0x0004
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#define EXP_TIMING_CS2_OFFSET 0x0008
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#define EXP_TIMING_CS3_OFFSET 0x000c
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#define EXP_TIMING_CS4_OFFSET 0x0010
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#define EXP_TIMING_CS5_OFFSET 0x0014
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#define EXP_TIMING_CS6_OFFSET 0x0018
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#define EXP_TIMING_CS7_OFFSET 0x001c
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#define EXP_CNFG0_OFFSET 0x0020
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#define EXP_CNFG1_OFFSET 0x0024
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#define EXP_FCTRL_OFFSET 0x0028
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#define IXP425_EXP_RECOVERY_SHIFT 16
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#define IXP425_EXP_HOLD_SHIFT 20
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#define IXP425_EXP_STROBE_SHIFT 22
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#define IXP425_EXP_SETUP_SHIFT 26
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#define IXP425_EXP_ADDR_SHIFT 28
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#define IXP425_EXP_CS_EN (1U << 31)
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#define IXP425_EXP_RECOVERY_T(x) (((x) & 15) << IXP425_EXP_RECOVERY_SHIFT)
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#define IXP425_EXP_HOLD_T(x) (((x) & 3) << IXP425_EXP_HOLD_SHIFT)
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#define IXP425_EXP_STROBE_T(x) (((x) & 15) << IXP425_EXP_STROBE_SHIFT)
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#define IXP425_EXP_SETUP_T(x) (((x) & 3) << IXP425_EXP_SETUP_SHIFT)
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#define IXP425_EXP_ADDR_T(x) (((x) & 3) << IXP425_EXP_ADDR_SHIFT)
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/* EXP_CSn bits */
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#define EXP_BYTE_EN 0x00000001 /* bus uses only 8-bit data */
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#define EXP_WR_EN 0x00000002 /* ena writes to CS region */
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/* bit 2 is reserved */
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#define EXP_SPLT_EN 0x00000008 /* ena AHB split transfers */
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#define EXP_MUX_EN 0x00000010 /* multiplexed address/data */
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#define EXP_HRDY_POL 0x00000020 /* HPI|HRDY polarity */
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#define EXP_BYTE_RD16 0x00000040 /* byte rd access to word dev */
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#define EXP_CNFG 0x00003c00 /* device config size */
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#define EXP_SZ_512 (0 << 10)
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#define EXP_SZ_1K (1 << 10)
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#define EXP_SZ_2K (2 << 10)
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#define EXP_SZ_4K (3 << 10)
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#define EXP_SZ_8K (4 << 10)
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#define EXP_SZ_16K (5 << 10)
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#define EXP_SZ_32K (6 << 10)
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#define EXP_SZ_64K (7 << 10)
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#define EXP_SZ_128K (8 << 10)
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#define EXP_SZ_256K (9 << 10)
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#define EXP_SZ_512K (10 << 10)
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#define EXP_SZ_1M (11 << 10)
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#define EXP_SZ_2M (12 << 10)
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#define EXP_SZ_4M (13 << 10)
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#define EXP_SZ_8M (14 << 10)
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#define EXP_SZ_16M (15 << 10)
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#define EXP_CYC_TYPE 0x0000c000 /* bus cycle "type" */
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#define EXP_CYC_INTEL (0 << 14)
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#define EXP_CYC_MOTO (1 << 14)
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#define EXP_CYC_HPI (2 << 14)
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#define EXP_T5 0x000f0000 /* recovery timing */
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#define EXP_T4 0x00300000 /* hold timing */
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#define EXP_T3 0x03c00000 /* strobe timing */
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#define EXP_T2 0x0c000000 /* setup/chip select timing */
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#define EXP_T1 0x30000000 /* address timing */
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/* bit 30 is reserved */
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#define EXP_CS_EN 0x80000000 /* chip select enabled */
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/* EXP_CNFG0 bits */
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#define EXP_CNFG0_8BIT (1 << 0)
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#define EXP_CNFG0_PCI_HOST (1 << 1)
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#define EXP_CNFG0_PCI_ARB (1 << 2)
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#define EXP_CNFG0_PCI_66MHZ (1 << 4)
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#define EXP_CNFG0_MEM_MAP (1 << 31)
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/* EXP_CNFG1 bits */
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#define EXP_CNFG1_SW_INT0 (1 << 0)
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#define EXP_CNFG1_SW_INT1 (1 << 1)
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#define EXP_FCTRL_RCOMP (1<<0)
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#define EXP_FCTRL_USB (1<<1)
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#define EXP_FCTRL_HASH (1<<2)
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#define EXP_FCTRL_AES (1<<3)
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#define EXP_FCTRL_DES (1<<4)
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#define EXP_FCTRL_HDLC (1<<5)
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#define EXP_FCTRL_AAL (1<<6)
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#define EXP_FCTRL_HSS (1<<7)
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#define EXP_FCTRL_UTOPIA (1<<8)
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#define EXP_FCTRL_ETH0 (1<<9)
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#define EXP_FCTRL_ETH1 (1<<10)
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#define EXP_FCTRL_NPEA (1<<11)
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#define EXP_FCTRL_NPEB (1<<12)
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#define EXP_FCTRL_NPEC (1<<13)
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#define EXP_FCTRL_PCI (1<<14)
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/* XXX more stuff we don't care about */
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/*
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* PCI
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*/
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#define IXP425_PCI_HWBASE 0xc0000000
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#define IXP425_PCI_VBASE (IXP425_EXP_VBASE + IXP425_EXP_SIZE)
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/* 0xf0011000 */
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#define IXP425_PCI_SIZE IXP425_REG_SIZE /* 0x1000 */
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/*
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* Mapping registers of IXP425 PCI Configuration
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*/
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/* PCI_ID_REG 0x00 */
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/* PCI_COMMAND_STATUS_REG 0x04 */
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/* PCI_CLASS_REG 0x08 */
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/* PCI_BHLC_REG 0x0c */
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#define PCI_MAPREG_BAR0 0x10 /* Base Address 0 */
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#define PCI_MAPREG_BAR1 0x14 /* Base Address 1 */
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#define PCI_MAPREG_BAR2 0x18 /* Base Address 2 */
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#define PCI_MAPREG_BAR3 0x1c /* Base Address 3 */
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#define PCI_MAPREG_BAR4 0x20 /* Base Address 4 */
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#define PCI_MAPREG_BAR5 0x24 /* Base Address 5 */
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/* PCI_SUBSYS_ID_REG 0x2c */
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/* PCI_INTERRUPT_REG 0x3c */
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#define PCI_RTOTTO 0x40
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/* PCI Controller CSR Base Address */
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#define IXP425_PCI_CSR_BASE IXP425_PCI_VBASE
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/* PCI Memory Space */
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#define IXP425_PCI_MEM_HWBASE 0x48000000UL
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#define IXP425_PCI_MEM_VBASE 0xf8000000UL
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#define IXP425_PCI_MEM_SIZE 0x04000000UL /* 64MB */
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/* PCI I/O Space */
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#define IXP425_PCI_IO_HWBASE 0x00000000UL
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#define IXP425_PCI_IO_SIZE 0x00100000UL /* 1Mbyte */
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/* PCI Controller Configuration Offset */
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#define PCI_NP_AD 0x00
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#define PCI_NP_CBE 0x04
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# define NP_CBE_SHIFT 4
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#define PCI_NP_WDATA 0x08
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#define PCI_NP_RDATA 0x0c
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#define PCI_CRP_AD_CBE 0x10
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#define PCI_CRP_AD_WDATA 0x14
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#define PCI_CRP_AD_RDATA 0x18
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#define PCI_CSR 0x1c
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# define CSR_PRST (1U << 16)
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# define CSR_IC (1U << 15)
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# define CSR_ABE (1U << 4)
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# define CSR_PDS (1U << 3)
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# define CSR_ADS (1U << 2)
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# define CSR_HOST (1U << 0)
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#define PCI_ISR 0x20
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# define ISR_AHBE (1U << 3)
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# define ISR_PPE (1U << 2)
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# define ISR_PFE (1U << 1)
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# define ISR_PSE (1U << 0)
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#define PCI_INTEN 0x24
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#define PCI_DMACTRL 0x28
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#define PCI_AHBMEMBASE 0x2c
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#define PCI_AHBIOBASE 0x30
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#define PCI_PCIMEMBASE 0x34
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#define PCI_AHBDOORBELL 0x38
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#define PCI_PCIDOORBELL 0x3c
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#define PCI_ATPDMA0_AHBADDR 0x40
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#define PCI_ATPDMA0_PCIADDR 0x44
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#define PCI_ATPDMA0_LENGTH 0x48
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#define PCI_ATPDMA1_AHBADDR 0x4c
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#define PCI_ATPDMA1_PCIADDR 0x50
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#define PCI_ATPDMA1_LENGTH 0x54
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#define PCI_PTADMA0_AHBADDR 0x58
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#define PCI_PTADMA0_PCIADDR 0x5c
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#define PCI_PTADMA0_LENGTH 0x60
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#define PCI_PTADMA1_AHBADDR 0x64
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#define PCI_PTADMA1_PCIADDR 0x68
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#define PCI_PTADMA1_LENGTH 0x6c
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/* PCI target(T)/initiator(I) Interface Commands for PCI_NP_CBE register */
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#define COMMAND_NP_IA 0x0 /* Interrupt Acknowledge (I)*/
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#define COMMAND_NP_SC 0x1 /* Special Cycle (I)*/
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#define COMMAND_NP_IO_READ 0x2 /* I/O Read (T)(I) */
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#define COMMAND_NP_IO_WRITE 0x3 /* I/O Write (T)(I) */
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#define COMMAND_NP_MEM_READ 0x6 /* Memory Read (T)(I) */
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#define COMMAND_NP_MEM_WRITE 0x7 /* Memory Write (T)(I) */
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#define COMMAND_NP_CONF_READ 0xa /* Configuration Read (T)(I) */
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#define COMMAND_NP_CONF_WRITE 0xb /* Configuration Write (T)(I) */
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/* PCI byte enables */
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#define BE_8BIT(a) ((0x10u << ((a) & 0x03)) ^ 0xf0)
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#define BE_16BIT(a) ((0x30u << ((a) & 0x02)) ^ 0xf0)
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#define BE_32BIT(a) 0x00
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/* PCI byte selects */
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#define READ_8BIT(v,a) ((u_int8_t)((v) >> (((a) & 3) * 8)))
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#define READ_16BIT(v,a) ((u_int16_t)((v) >> (((a) & 2) * 8)))
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#define WRITE_8BIT(v,a) (((u_int32_t)(v)) << (((a) & 3) * 8))
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#define WRITE_16BIT(v,a) (((u_int32_t)(v)) << (((a) & 2) * 8))
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/* PCI Controller Configuration Commands for PCI_CRP_AD_CBE */
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#define COMMAND_CRP_READ 0x00
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#define COMMAND_CRP_WRITE (1U << 16)
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/*
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* SDRAM Configuration Register
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*/
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#define IXP425_MCU_HWBASE 0xcc000000UL
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#define IXP425_MCU_VBASE 0xf0200000UL
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#define IXP425_MCU_SIZE 0x1000 /* Actually only 256 bytes */
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#define MCU_SDR_CONFIG 0x00
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#define MCU_SDR_CONFIG_MCONF(x) ((x) & 0x7)
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#define MCU_SDR_CONFIG_64MBIT (1u << 5)
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#define MCU_SDR_REFRESH 0x04
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#define MCU_SDR_IR 0x08
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/*
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* Performance Monitoring Unit (CP14)
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*
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* CP14.0.1 Performance Monitor Control Register(PMNC)
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* CP14.1.1 Clock Counter(CCNT)
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* CP14.4.1 Interrupt Enable Register(INTEN)
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* CP14.5.1 Overflow Flag Register(FLAG)
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* CP14.8.1 Event Selection Register(EVTSEL)
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* CP14.0.2 Performance Counter Register 0(PMN0)
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* CP14.1.2 Performance Counter Register 0(PMN1)
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* CP14.2.2 Performance Counter Register 0(PMN2)
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* CP14.3.2 Performance Counter Register 0(PMN3)
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*/
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#define PMNC_E 0x00000001 /* enable all counters */
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#define PMNC_P 0x00000002 /* reset all PMNs to 0 */
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#define PMNC_C 0x00000004 /* clock counter reset */
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#define PMNC_D 0x00000008 /* clock counter / 64 */
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#define INTEN_CC_IE 0x00000001 /* enable clock counter interrupt */
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#define INTEN_PMN0_IE 0x00000002 /* enable PMN0 interrupt */
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#define INTEN_PMN1_IE 0x00000004 /* enable PMN1 interrupt */
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#define INTEN_PMN2_IE 0x00000008 /* enable PMN2 interrupt */
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#define INTEN_PMN3_IE 0x00000010 /* enable PMN3 interrupt */
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#define FLAG_CC_IF 0x00000001 /* clock counter overflow */
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#define FLAG_PMN0_IF 0x00000002 /* PMN0 overflow */
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#define FLAG_PMN1_IF 0x00000004 /* PMN1 overflow */
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#define FLAG_PMN2_IF 0x00000008 /* PMN2 overflow */
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#define FLAG_PMN3_IF 0x00000010 /* PMN3 overflow */
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#define EVTSEL_EVCNT_MASK 0x0000000ff /* event to count for PMNs */
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#define PMNC_EVCNT0_SHIFT 0
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#define PMNC_EVCNT1_SHIFT 8
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#define PMNC_EVCNT2_SHIFT 16
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#define PMNC_EVCNT3_SHIFT 24
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/*
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* Queue Manager
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*/
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#define IXP425_QMGR_HWBASE 0x60000000UL
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#define IXP425_QMGR_VBASE (IXP425_PCI_VBASE + IXP425_PCI_SIZE)
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#define IXP425_QMGR_SIZE 0x4000
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/*
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* Network Processing Engines (NPE's) and associated Ethernet MAC's.
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*/
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#define IXP425_NPE_A_HWBASE (IXP425_IO_HWBASE + IXP425_NPE_A_OFFSET)
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#define IXP425_NPE_A_VBASE (IXP425_IO_VBASE + IXP425_NPE_A_OFFSET)
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#define IXP425_NPE_A_SIZE 0x1000 /* Actually only 256 bytes */
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#define IXP425_NPE_B_HWBASE (IXP425_IO_HWBASE + IXP425_NPE_B_OFFSET)
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#define IXP425_NPE_B_VBASE (IXP425_IO_VBASE + IXP425_NPE_B_OFFSET)
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#define IXP425_NPE_B_SIZE 0x1000 /* Actually only 256 bytes */
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#define IXP425_NPE_C_HWBASE (IXP425_IO_HWBASE + IXP425_NPE_C_OFFSET)
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#define IXP425_NPE_C_VBASE (IXP425_IO_VBASE + IXP425_NPE_C_OFFSET)
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#define IXP425_NPE_C_SIZE 0x1000 /* Actually only 256 bytes */
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#define IXP425_MAC_A_HWBASE (IXP425_IO_HWBASE + IXP425_MAC_A_OFFSET)
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#define IXP425_MAC_A_VBASE (IXP425_IO_VBASE + IXP425_MAC_A_OFFSET)
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#define IXP425_MAC_A_SIZE 0x1000 /* Actually only 256 bytes */
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#define IXP425_MAC_B_HWBASE (IXP425_IO_HWBASE + IXP425_MAC_B_OFFSET)
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#define IXP425_MAC_B_VBASE (IXP425_IO_VBASE + IXP425_MAC_B_OFFSET)
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#define IXP425_MAC_B_SIZE 0x1000 /* Actually only 256 bytes */
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/*
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* Expansion Bus Data Space.
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*/
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#define IXP425_EXP_BUS_HWBASE 0x50000000UL
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#define IXP425_EXP_BUS_SIZE 0x01000000 /* max, typically smaller */
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#define IXP425_EXP_BUS_CSx_HWBASE(i) \
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(IXP425_EXP_BUS_HWBASE + (i)*IXP425_EXP_BUS_SIZE)
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#define IXP425_EXP_BUS_CSx_VBASE(i) \
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(IXP425_MAC_B_VBASE + (i)*IXP425_MAC_B_SIZE)
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#define IXP425_EXP_BUS_CS1_HWBASE IXP425_EXP_BUS_CSx_HWBASE(1)
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#define IXP425_EXP_BUS_CS1_VBASE IXP425_EXP_BUS_CSx_VBASE(1)
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#define IXP425_EXP_BUS_CS1_SIZE 0x1000
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#define IXP425_EXP_BUS_CS2_HWBASE IXP425_EXP_BUS_CSx_HWBASE(2)
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#define IXP425_EXP_BUS_CS2_VBASE IXP425_EXP_BUS_CSx_VBASE(2)
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#define IXP425_EXP_BUS_CS2_SIZE 0x1000
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#define IXP425_EXP_BUS_CS3_HWBASE IXP425_EXP_BUS_CSx_HWBASE(3)
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#define IXP425_EXP_BUS_CS3_VBASE IXP425_EXP_BUS_CSx_VBASE(3)
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#define IXP425_EXP_BUS_CS3_SIZE 0x1000
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#define IXP425_EXP_BUS_CS4_HWBASE IXP425_EXP_BUS_CSx_HWBASE(4)
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#define IXP425_EXP_BUS_CS4_VBASE IXP425_EXP_BUS_CSx_VBASE(4)
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#define IXP425_EXP_BUS_CS4_SIZE 0x1000
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/* NB: not mapped (yet) */
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#define IXP425_EXP_BUS_CS0_HWBASE IXP425_EXP_BUS_CSx_HWBASE(0)
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#define IXP425_EXP_BUS_CS5_HWBASE IXP425_EXP_BUS_CSx_HWBASE(5)
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#define IXP425_EXP_BUS_CS6_HWBASE IXP425_EXP_BUS_CSx_HWBASE(6)
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#define IXP425_EXP_BUS_CS7_HWBASE IXP425_EXP_BUS_CSx_HWBASE(7)
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#endif /* _IXP425REG_H_ */
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