959bd29aa8
Obtained from: pfSense MFC after: 2 weeks Sponsored by: Rubicon Communications, LLC (Netgate)
346 lines
9.0 KiB
C
346 lines
9.0 KiB
C
/*-
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* Copyright (c) 2013 Tsubai Masanari
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* Copyright (c) 2013 Bryan Venteicher <bryanv@FreeBSD.org>
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* $FreeBSD$
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*/
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#ifndef _IF_VMXVAR_H
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#define _IF_VMXVAR_H
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struct vmxnet3_softc;
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struct vmxnet3_dma_alloc {
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bus_addr_t dma_paddr;
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caddr_t dma_vaddr;
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bus_dma_tag_t dma_tag;
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bus_dmamap_t dma_map;
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bus_size_t dma_size;
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};
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/*
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* The number of Rx/Tx queues this driver prefers.
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*/
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#define VMXNET3_DEF_RX_QUEUES 8
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#define VMXNET3_DEF_TX_QUEUES 8
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/*
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* The number of Rx rings in each Rx queue.
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*/
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#define VMXNET3_RXRINGS_PERQ 2
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/*
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* The number of descriptors in each Rx/Tx ring.
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*/
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#define VMXNET3_DEF_TX_NDESC 512
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#define VMXNET3_MAX_TX_NDESC 4096
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#define VMXNET3_MIN_TX_NDESC 32
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#define VMXNET3_MASK_TX_NDESC 0x1F
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#define VMXNET3_DEF_RX_NDESC 256
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#define VMXNET3_MAX_RX_NDESC 2048
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#define VMXNET3_MIN_RX_NDESC 32
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#define VMXNET3_MASK_RX_NDESC 0x1F
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#define VMXNET3_MAX_TX_NCOMPDESC VMXNET3_MAX_TX_NDESC
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#define VMXNET3_MAX_RX_NCOMPDESC \
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(VMXNET3_MAX_RX_NDESC * VMXNET3_RXRINGS_PERQ)
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struct vmxnet3_txbuf {
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bus_dmamap_t vtxb_dmamap;
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struct mbuf *vtxb_m;
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};
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struct vmxnet3_txring {
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struct vmxnet3_txbuf *vxtxr_txbuf;
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u_int vxtxr_head;
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u_int vxtxr_next;
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u_int vxtxr_ndesc;
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int vxtxr_gen;
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bus_dma_tag_t vxtxr_txtag;
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struct vmxnet3_txdesc *vxtxr_txd;
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struct vmxnet3_dma_alloc vxtxr_dma;
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};
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static inline int
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VMXNET3_TXRING_AVAIL(struct vmxnet3_txring *txr)
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{
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int avail = txr->vxtxr_next - txr->vxtxr_head - 1;
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return (avail < 0 ? txr->vxtxr_ndesc + avail : avail);
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}
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struct vmxnet3_rxbuf {
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bus_dmamap_t vrxb_dmamap;
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struct mbuf *vrxb_m;
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};
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struct vmxnet3_rxring {
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struct vmxnet3_rxbuf *vxrxr_rxbuf;
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struct vmxnet3_rxdesc *vxrxr_rxd;
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u_int vxrxr_fill;
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u_int vxrxr_ndesc;
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int vxrxr_gen;
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int vxrxr_rid;
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bus_dma_tag_t vxrxr_rxtag;
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struct vmxnet3_dma_alloc vxrxr_dma;
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bus_dmamap_t vxrxr_spare_dmap;
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};
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static inline void
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vmxnet3_rxr_increment_fill(struct vmxnet3_rxring *rxr)
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{
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if (++rxr->vxrxr_fill == rxr->vxrxr_ndesc) {
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rxr->vxrxr_fill = 0;
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rxr->vxrxr_gen ^= 1;
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}
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}
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struct vmxnet3_comp_ring {
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union {
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struct vmxnet3_txcompdesc *txcd;
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struct vmxnet3_rxcompdesc *rxcd;
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} vxcr_u;
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u_int vxcr_next;
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u_int vxcr_ndesc;
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int vxcr_gen;
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struct vmxnet3_dma_alloc vxcr_dma;
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};
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struct vmxnet3_txq_stats {
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uint64_t vmtxs_opackets; /* if_opackets */
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uint64_t vmtxs_obytes; /* if_obytes */
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uint64_t vmtxs_omcasts; /* if_omcasts */
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uint64_t vmtxs_csum;
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uint64_t vmtxs_tso;
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uint64_t vmtxs_full;
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uint64_t vmtxs_offload_failed;
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};
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struct vmxnet3_txqueue {
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struct mtx vxtxq_mtx;
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struct vmxnet3_softc *vxtxq_sc;
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#ifndef VMXNET3_LEGACY_TX
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struct buf_ring *vxtxq_br;
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#endif
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int vxtxq_id;
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int vxtxq_intr_idx;
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int vxtxq_watchdog;
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struct vmxnet3_txring vxtxq_cmd_ring;
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struct vmxnet3_comp_ring vxtxq_comp_ring;
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struct vmxnet3_txq_stats vxtxq_stats;
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struct vmxnet3_txq_shared *vxtxq_ts;
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struct sysctl_oid_list *vxtxq_sysctl;
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#ifndef VMXNET3_LEGACY_TX
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struct task vxtxq_defrtask;
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#endif
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char vxtxq_name[16];
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} __aligned(CACHE_LINE_SIZE);
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#define VMXNET3_TXQ_LOCK(_txq) mtx_lock(&(_txq)->vxtxq_mtx)
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#define VMXNET3_TXQ_TRYLOCK(_txq) mtx_trylock(&(_txq)->vxtxq_mtx)
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#define VMXNET3_TXQ_UNLOCK(_txq) mtx_unlock(&(_txq)->vxtxq_mtx)
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#define VMXNET3_TXQ_LOCK_ASSERT(_txq) \
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mtx_assert(&(_txq)->vxtxq_mtx, MA_OWNED)
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#define VMXNET3_TXQ_LOCK_ASSERT_NOTOWNED(_txq) \
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mtx_assert(&(_txq)->vxtxq_mtx, MA_NOTOWNED)
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struct vmxnet3_rxq_stats {
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uint64_t vmrxs_ipackets; /* if_ipackets */
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uint64_t vmrxs_ibytes; /* if_ibytes */
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uint64_t vmrxs_iqdrops; /* if_iqdrops */
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uint64_t vmrxs_ierrors; /* if_ierrors */
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};
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struct vmxnet3_rxqueue {
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struct mtx vxrxq_mtx;
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struct vmxnet3_softc *vxrxq_sc;
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int vxrxq_id;
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int vxrxq_intr_idx;
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struct mbuf *vxrxq_mhead;
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struct mbuf *vxrxq_mtail;
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struct vmxnet3_rxring vxrxq_cmd_ring[VMXNET3_RXRINGS_PERQ];
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struct vmxnet3_comp_ring vxrxq_comp_ring;
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struct vmxnet3_rxq_stats vxrxq_stats;
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struct vmxnet3_rxq_shared *vxrxq_rs;
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struct sysctl_oid_list *vxrxq_sysctl;
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char vxrxq_name[16];
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} __aligned(CACHE_LINE_SIZE);
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#define VMXNET3_RXQ_LOCK(_rxq) mtx_lock(&(_rxq)->vxrxq_mtx)
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#define VMXNET3_RXQ_UNLOCK(_rxq) mtx_unlock(&(_rxq)->vxrxq_mtx)
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#define VMXNET3_RXQ_LOCK_ASSERT(_rxq) \
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mtx_assert(&(_rxq)->vxrxq_mtx, MA_OWNED)
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#define VMXNET3_RXQ_LOCK_ASSERT_NOTOWNED(_rxq) \
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mtx_assert(&(_rxq)->vxrxq_mtx, MA_NOTOWNED)
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struct vmxnet3_statistics {
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uint32_t vmst_defragged;
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uint32_t vmst_defrag_failed;
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uint32_t vmst_mgetcl_failed;
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uint32_t vmst_mbuf_load_failed;
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};
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struct vmxnet3_interrupt {
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struct resource *vmxi_irq;
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int vmxi_rid;
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void *vmxi_handler;
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};
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struct vmxnet3_softc {
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device_t vmx_dev;
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struct ifnet *vmx_ifp;
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struct vmxnet3_driver_shared *vmx_ds;
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uint32_t vmx_flags;
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#define VMXNET3_FLAG_NO_MSIX 0x0001
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#define VMXNET3_FLAG_RSS 0x0002
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struct vmxnet3_rxqueue *vmx_rxq;
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struct vmxnet3_txqueue *vmx_txq;
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struct resource *vmx_res0;
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bus_space_tag_t vmx_iot0;
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bus_space_handle_t vmx_ioh0;
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struct resource *vmx_res1;
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bus_space_tag_t vmx_iot1;
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bus_space_handle_t vmx_ioh1;
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struct resource *vmx_msix_res;
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int vmx_link_active;
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int vmx_link_speed;
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int vmx_if_flags;
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int vmx_ntxqueues;
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int vmx_nrxqueues;
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int vmx_ntxdescs;
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int vmx_nrxdescs;
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int vmx_max_rxsegs;
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int vmx_rx_max_chain;
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struct vmxnet3_statistics vmx_stats;
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int vmx_intr_type;
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int vmx_intr_mask_mode;
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int vmx_event_intr_idx;
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int vmx_nintrs;
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struct vmxnet3_interrupt vmx_intrs[VMXNET3_MAX_INTRS];
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struct mtx vmx_mtx;
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#ifndef VMXNET3_LEGACY_TX
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struct taskqueue *vmx_tq;
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#endif
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uint8_t *vmx_mcast;
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void *vmx_qs;
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struct vmxnet3_rss_shared *vmx_rss;
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struct callout vmx_tick;
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struct vmxnet3_dma_alloc vmx_ds_dma;
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struct vmxnet3_dma_alloc vmx_qs_dma;
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struct vmxnet3_dma_alloc vmx_mcast_dma;
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struct vmxnet3_dma_alloc vmx_rss_dma;
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struct ifmedia vmx_media;
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int vmx_max_ntxqueues;
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int vmx_max_nrxqueues;
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eventhandler_tag vmx_vlan_attach;
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eventhandler_tag vmx_vlan_detach;
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uint32_t vmx_vlan_filter[4096/32];
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uint8_t vmx_lladdr[ETHER_ADDR_LEN];
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};
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#define VMXNET3_CORE_LOCK_INIT(_sc, _name) \
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mtx_init(&(_sc)->vmx_mtx, _name, "VMXNET3 Lock", MTX_DEF)
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#define VMXNET3_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->vmx_mtx)
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#define VMXNET3_CORE_LOCK(_sc) mtx_lock(&(_sc)->vmx_mtx)
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#define VMXNET3_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->vmx_mtx)
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#define VMXNET3_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->vmx_mtx, MA_OWNED)
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#define VMXNET3_CORE_LOCK_ASSERT_NOTOWNED(_sc) \
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mtx_assert(&(_sc)->vmx_mtx, MA_NOTOWNED)
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/*
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* Our driver version we report to the hypervisor; we just keep
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* this value constant.
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*/
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#define VMXNET3_DRIVER_VERSION 0x00010000
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/*
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* Max descriptors per Tx packet. We must limit the size of the
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* any TSO packets based on the number of segments.
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*/
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#define VMXNET3_TX_MAXSEGS 32
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#define VMXNET3_TX_MAXSIZE (VMXNET3_TX_MAXSEGS * MCLBYTES)
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/*
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* Maximum support Tx segments size. The length field in the
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* Tx descriptor is 14 bits.
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*/
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#define VMXNET3_TX_MAXSEGSIZE (1 << 14)
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/*
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* The maximum number of Rx segments we accept. When LRO is enabled,
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* this allows us to receive the maximum sized frame with one MCLBYTES
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* cluster followed by 16 MJUMPAGESIZE clusters.
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*/
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#define VMXNET3_MAX_RX_SEGS 17
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/*
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* Predetermined size of the multicast MACs filter table. If the
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* number of multicast addresses exceeds this size, then the
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* ALL_MULTI mode is use instead.
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*/
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#define VMXNET3_MULTICAST_MAX 32
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/*
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* Our Tx watchdog timeout.
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*/
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#define VMXNET3_WATCHDOG_TIMEOUT 5
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/*
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* Number of slots in the Tx bufrings. This value matches most other
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* multiqueue drivers.
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*/
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#define VMXNET3_DEF_BUFRING_SIZE 4096
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/*
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* IP protocols that we can perform Tx checksum offloading of.
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*/
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#define VMXNET3_CSUM_OFFLOAD (CSUM_TCP | CSUM_UDP)
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#define VMXNET3_CSUM_OFFLOAD_IPV6 (CSUM_TCP_IPV6 | CSUM_UDP_IPV6)
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#define VMXNET3_CSUM_ALL_OFFLOAD \
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(VMXNET3_CSUM_OFFLOAD | VMXNET3_CSUM_OFFLOAD_IPV6 | CSUM_TSO)
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/*
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* Compat macros to keep this driver compiling on old releases.
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*/
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#if !defined(SYSCTL_ADD_UQUAD)
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#define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD
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#endif
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#if !defined(IFCAP_TXCSUM_IPV6)
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#define IFCAP_TXCSUM_IPV6 0
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#endif
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#if !defined(IFCAP_RXCSUM_IPV6)
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#define IFCAP_RXCSUM_IPV6 0
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#endif
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#if !defined(CSUM_TCP_IPV6)
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#define CSUM_TCP_IPV6 0
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#endif
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#if !defined(CSUM_UDP_IPV6)
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#define CSUM_UDP_IPV6 0
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#endif
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#endif /* _IF_VMXVAR_H */
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