dc7717a863
It is working on IFC6410 board which has Qualcomm Snapdragon SoC. Approved by: stas (mentor)
230 lines
7.5 KiB
C
230 lines
7.5 KiB
C
/*-
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* Copyright (c) 2014 Ganbold Tsagaankhuu <ganbold@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _UART_DM_H_
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#define _UART_DM_H_
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#define UART_DM_EXTR_BITS(value, start_pos, end_pos) \
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((value << (32 - end_pos)) >> (32 - (end_pos - start_pos)))
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/* UART Parity Mode */
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enum UART_DM_PARITY_MODE {
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UART_DM_NO_PARITY,
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UART_DM_ODD_PARITY,
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UART_DM_EVEN_PARITY,
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UART_DM_SPACE_PARITY
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};
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/* UART Stop Bit Length */
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enum UART_DM_STOP_BIT_LEN {
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UART_DM_SBL_9_16,
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UART_DM_SBL_1,
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UART_DM_SBL_1_9_16,
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UART_DM_SBL_2
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};
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/* UART Bits per Char */
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enum UART_DM_BITS_PER_CHAR {
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UART_DM_5_BPS,
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UART_DM_6_BPS,
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UART_DM_7_BPS,
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UART_DM_8_BPS
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};
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/* 8-N-1 Configuration */
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#define UART_DM_8_N_1_MODE (UART_DM_NO_PARITY | \
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(UART_DM_SBL_1 << 2) | \
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(UART_DM_8_BPS << 4))
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/* UART_DM Registers */
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/* UART Operational Mode Registers (HSUART) */
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#define UART_DM_MR1 0x00
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#define UART_DM_MR1_AUTO_RFR_LEVEL1_BMSK 0xffffff00
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#define UART_DM_MR1_AUTO_RFR_LEVEL0_BMSK 0x3f
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#define UART_DM_MR1_CTS_CTL_BMSK 0x40
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#define UART_DM_MR1_RX_RDY_CTL_BMSK 0x80
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#define UART_DM_MR2 0x04
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#define UART_DM_MR2_ERROR_MODE_BMSK 0x40
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#define UART_DM_MR2_BITS_PER_CHAR_BMSK 0x30
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#define UART_DM_MR2_STOP_BIT_LEN_BMSK 0x0c
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#define UART_DM_MR2_PARITY_MODE_BMSK 0x03
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#define UART_DM_RXBRK_ZERO_CHAR_OFF (1 << 8)
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#define UART_DM_LOOPBACK (1 << 7)
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/* UART Clock Selection Register, write only */
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#define UART_DM_CSR 0x08
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#define UART_DM_CSR_115200 0xff
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#define UART_DM_CSR_57600 0xee
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#define UART_DM_CSR_38400 0xdd
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#define UART_DM_CSR_28800 0xcc
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#define UART_DM_CSR_19200 0xbb
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#define UART_DM_CSR_14400 0xaa
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#define UART_DM_CSR_9600 0x99
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#define UART_DM_CSR_7200 0x88
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#define UART_DM_CSR_4800 0x77
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#define UART_DM_CSR_3600 0x66
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#define UART_DM_CSR_2400 0x55
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#define UART_DM_CSR_1200 0x44
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#define UART_DM_CSR_600 0x33
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#define UART_DM_CSR_300 0x22
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#define UART_DM_CSR_150 0x11
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#define UART_DM_CSR_75 0x00
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/* UART DM TX FIFO Registers - 4, write only */
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#define UART_DM_TF(x) (0x70 + (4 * (x)))
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/* UART Command Register, write only */
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#define UART_DM_CR 0x10
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#define UART_DM_CR_RX_ENABLE (1 << 0)
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#define UART_DM_CR_RX_DISABLE (1 << 1)
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#define UART_DM_CR_TX_ENABLE (1 << 2)
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#define UART_DM_CR_TX_DISABLE (1 << 3)
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/* UART_DM_CR channel command bit value (register field is bits 8:4) */
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#define UART_DM_RESET_RX 0x10
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#define UART_DM_RESET_TX 0x20
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#define UART_DM_RESET_ERROR_STATUS 0x30
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#define UART_DM_RESET_BREAK_INT 0x40
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#define UART_DM_START_BREAK 0x50
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#define UART_DM_STOP_BREAK 0x60
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#define UART_DM_RESET_CTS 0x70
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#define UART_DM_RESET_STALE_INT 0x80
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#define UART_DM_RFR_LOW 0xD0
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#define UART_DM_RFR_HIGH 0xE0
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#define UART_DM_CR_PROTECTION_EN 0x100
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#define UART_DM_STALE_EVENT_ENABLE 0x500
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#define UART_DM_STALE_EVENT_DISABLE 0x600
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#define UART_DM_FORCE_STALE_EVENT 0x400
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#define UART_DM_CLEAR_TX_READY 0x300
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#define UART_DM_RESET_TX_ERROR 0x800
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#define UART_DM_RESET_TX_DONE 0x810
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/* UART Interrupt Mask Register */
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#define UART_DM_IMR 0x14
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/* these can be used for both ISR and IMR registers */
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#define UART_DM_TXLEV (1 << 0)
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#define UART_DM_RXHUNT (1 << 1)
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#define UART_DM_RXBRK_CHNG (1 << 2)
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#define UART_DM_RXSTALE (1 << 3)
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#define UART_DM_RXLEV (1 << 4)
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#define UART_DM_DELTA_CTS (1 << 5)
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#define UART_DM_CURRENT_CTS (1 << 6)
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#define UART_DM_TX_READY (1 << 7)
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#define UART_DM_TX_ERROR (1 << 8)
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#define UART_DM_TX_DONE (1 << 9)
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#define UART_DM_RXBREAK_START (1 << 10)
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#define UART_DM_RXBREAK_END (1 << 11)
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#define UART_DM_PAR_FRAME_ERR_IRQ (1 << 12)
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#define UART_DM_IMR_ENABLED (UART_DM_TX_READY | \
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UART_DM_TXLEV | \
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UART_DM_RXLEV | \
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UART_DM_RXSTALE)
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/* UART Interrupt Programming Register */
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#define UART_DM_IPR 0x18
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#define UART_DM_STALE_TIMEOUT_LSB 0x0f
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#define UART_DM_STALE_TIMEOUT_MSB 0x00
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#define UART_DM_IPR_STALE_TIMEOUT_MSB_BMSK 0xffffff80
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#define UART_DM_IPR_STALE_LSB_BMSK 0x1f
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/* UART Transmit/Receive FIFO Watermark Register */
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#define UART_DM_TFWR 0x1c
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/* Interrupt is generated when FIFO level is less than or equal to this value */
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#define UART_DM_TFW_VALUE 0
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#define UART_DM_RFWR 0x20
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/* Interrupt generated when no of words in RX FIFO is greater than this value */
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#define UART_DM_RFW_VALUE 0
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/* UART Hunt Character Register */
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#define UART_DM_HCR 0x24
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/* Used for RX transfer initialization */
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#define UART_DM_DMRX 0x34
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/* Default DMRX value - any value bigger than FIFO size would be fine */
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#define UART_DM_DMRX_DEF_VALUE 0x220
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/* Register to enable IRDA function */
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#define UART_DM_IRDA 0x38
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/* UART Data Mover Enable Register */
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#define UART_DM_DMEN 0x3c
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/* Number of characters for Transmission */
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#define UART_DM_NO_CHARS_FOR_TX 0x40
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/* UART RX FIFO Base Address */
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#define UART_DM_BADR 0x44
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#define UART_DM_SIM_CFG_ADDR 0x80
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/* Read only registers */
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/* UART Status Register */
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#define UART_DM_SR 0x08
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/* register field mask mapping */
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#define UART_DM_SR_RXRDY (1 << 0)
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#define UART_DM_SR_RXFULL (1 << 1)
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#define UART_DM_SR_TXRDY (1 << 2)
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#define UART_DM_SR_TXEMT (1 << 3)
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#define UART_DM_SR_UART_OVERRUN (1 << 4)
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#define UART_DM_SR_PAR_FRAME_ERR (1 << 5)
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#define UART_DM_RX_BREAK (1 << 6)
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#define UART_DM_HUNT_CHAR (1 << 7)
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#define UART_DM_RX_BRK_START_LAST (1 << 8)
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/* UART Receive FIFO Registers - 4 in numbers */
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#define UART_DM_RF(x) (0x70 + (4 * (x)))
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/* UART Masked Interrupt Status Register */
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#define UART_DM_MISR 0x10
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/* UART Interrupt Status Register */
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#define UART_DM_ISR 0x14
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/* Number of characters received since the end of last RX transfer */
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#define UART_DM_RX_TOTAL_SNAP 0x38
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/* UART TX FIFO Status Register */
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#define UART_DM_TXFS 0x4c
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#define UART_DM_TXFS_STATE_LSB(x) UART_DM_EXTR_BITS(x,0,6)
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#define UART_DM_TXFS_STATE_MSB(x) UART_DM_EXTR_BITS(x,14,31)
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#define UART_DM_TXFS_BUF_STATE(x) UART_DM_EXTR_BITS(x,7,9)
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#define UART_DM_TXFS_ASYNC_STATE(x) UART_DM_EXTR_BITS(x,10,13)
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/* UART RX FIFO Status Register */
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#define UART_DM_RXFS 0x50
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#define UART_DM_RXFS_STATE_LSB(x) UART_DM_EXTR_BITS(x,0,6)
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#define UART_DM_RXFS_STATE_MSB(x) UART_DM_EXTR_BITS(x,14,31)
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#define UART_DM_RXFS_BUF_STATE(x) UART_DM_EXTR_BITS(x,7,9)
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#define UART_DM_RXFS_ASYNC_STATE(x) UART_DM_EXTR_BITS(x,10,13)
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#endif /* _UART_DM_H_ */
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