968 lines
22 KiB
C
968 lines
22 KiB
C
/*-
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* Copyright (c) 1994 Gordon W. Ross
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This software was developed by the Computer Systems Engineering group
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* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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* contributed to Berkeley.
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*
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* All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Lawrence Berkeley Laboratory.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)zs.c 8.1 (Berkeley) 7/19/93
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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/*-
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* Copyright (c) 2003 Jake Burkholder.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/*
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* Zilog Z8530 Dual UART driver.
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*/
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#include "opt_ddb.h"
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#include "opt_comconsole.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/cons.h>
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#include <sys/fcntl.h>
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#include <sys/interrupt.h>
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#include <sys/kernel.h>
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#include <sys/ktr.h>
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#include <sys/mutex.h>
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#include <sys/proc.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <sys/rman.h>
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#include <sys/syslog.h>
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#include <sys/tty.h>
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#include <ddb/ddb.h>
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#include <dev/zs/z8530reg.h>
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#include <dev/zs/z8530var.h>
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#define ZS_READ(sc, r) \
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bus_space_read_1((sc)->sc_bt, (r), 0)
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#define ZS_WRITE(sc, r, v) \
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bus_space_write_1((sc)->sc_bt, (r), 0, (v))
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#define ZS_READ_REG(sc, r) ({ \
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ZS_WRITE((sc), (sc)->sc_csr, (r)); \
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ZS_READ((sc), (sc)->sc_csr); \
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})
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#define ZS_WRITE_REG(sc, r, v) ({ \
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ZS_WRITE((sc), (sc)->sc_csr, (r)); \
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ZS_WRITE((sc), (sc)->sc_csr, (v)); \
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})
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#define ZSTTY_LOCK(sz) mtx_lock_spin(&(sc)->sc_mtx)
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#define ZSTTY_UNLOCK(sz) mtx_unlock_spin(&(sc)->sc_mtx)
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static void zs_softintr(void *v);
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static void zs_shutdown(void *v);
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static int zstty_intr(struct zstty_softc *sc, uint8_t rr3);
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static void zstty_softintr(struct zstty_softc *sc) __unused;
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static int zstty_mdmctrl(struct zstty_softc *sc, int bits, int how);
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static int zstty_param(struct zstty_softc *sc, struct tty *tp,
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struct termios *t);
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static void zstty_flush(struct zstty_softc *sc) __unused;
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static int zstty_speed(struct zstty_softc *sc, int rate);
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static void zstty_load_regs(struct zstty_softc *sc);
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static cn_probe_t zs_cnprobe;
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static cn_init_t zs_cninit;
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static cn_term_t zs_cnterm;
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static cn_getc_t zs_cngetc;
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static cn_checkc_t zs_cncheckc;
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static cn_putc_t zs_cnputc;
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static cn_dbctl_t zs_cndbctl;
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static int zstty_cngetc(struct zstty_softc *sc);
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static int zstty_cncheckc(struct zstty_softc *sc);
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static void zstty_cnputc(struct zstty_softc *sc, int c);
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static d_open_t zsttyopen;
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static d_close_t zsttyclose;
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static d_ioctl_t zsttyioctl;
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static void zsttystart(struct tty *tp);
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static void zsttystop(struct tty *tp, int rw);
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static int zsttyparam(struct tty *tp, struct termios *t);
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static struct cdevsw zstty_cdevsw = {
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.d_open = zsttyopen,
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.d_close = zsttyclose,
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.d_read = ttyread,
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.d_write = ttywrite,
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.d_ioctl = zsttyioctl,
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.d_poll = ttypoll,
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.d_name = "zstty",
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.d_flags = D_TTY,
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.d_kqfilter = ttykqfilter,
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};
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static struct zstty_softc *zstty_cons;
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CONS_DRIVER(zs, zs_cnprobe, zs_cninit, zs_cnterm, zs_cngetc, zs_cncheckc,
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zs_cnputc, zs_cndbctl);
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int
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zs_probe(device_t dev)
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{
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device_set_desc(dev, "Zilog Z8530");
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return (0);
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}
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int
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zs_attach(device_t dev)
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{
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struct device *child[ZS_NCHAN];
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struct zs_softc *sc;
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int i;
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sc = device_get_softc(dev);
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sc->sc_dev = dev;
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for (i = 0; i < ZS_NCHAN; i++)
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child[i] = device_add_child(dev, "zstty", -1);
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bus_generic_attach(dev);
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for (i = 0; i < ZS_NCHAN; i++)
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sc->sc_child[i] = device_get_softc(child[i]);
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swi_add(&tty_ithd, "tty:zs", zs_softintr, sc, SWI_TTY,
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INTR_TYPE_TTY, &sc->sc_softih);
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ZS_WRITE_REG(sc->sc_child[0], 2, sc->sc_child[0]->sc_creg[2]);
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ZS_WRITE_REG(sc->sc_child[0], 9, sc->sc_child[0]->sc_creg[9]);
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if (zstty_cons != NULL) {
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DELAY(50000);
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cninit();
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}
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EVENTHANDLER_REGISTER(shutdown_final, zs_shutdown, sc,
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SHUTDOWN_PRI_DEFAULT);
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return (0);
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}
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void
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zs_intr(void *v)
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{
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struct zs_softc *sc = v;
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int needsoft;
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uint8_t rr3;
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/*
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* There is only one status register, which is on channel a. In order
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* to avoid needing to know which channel we're on in the tty interrupt
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* handler we shift the channel a status bits into the channel b
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* bit positions and always test the channel b bits.
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*/
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needsoft = 0;
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rr3 = ZS_READ_REG(sc->sc_child[0], 3);
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if ((rr3 & (ZSRR3_IP_A_RX | ZSRR3_IP_A_TX | ZSRR3_IP_A_STAT)) != 0)
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needsoft |= zstty_intr(sc->sc_child[0], rr3 >> 3);
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if ((rr3 & (ZSRR3_IP_B_RX | ZSRR3_IP_B_TX | ZSRR3_IP_B_STAT)) != 0)
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needsoft |= zstty_intr(sc->sc_child[1], rr3);
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if (needsoft)
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swi_sched(sc->sc_softih, 0);
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}
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static void
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zs_softintr(void *v)
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{
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struct zs_softc *sc = v;
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zstty_softintr(sc->sc_child[0]);
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zstty_softintr(sc->sc_child[1]);
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}
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static void
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zs_shutdown(void *v)
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{
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}
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int
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zstty_probe(device_t dev)
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{
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return (0);
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}
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int
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zstty_attach(device_t dev)
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{
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struct zstty_softc *sc;
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struct tty *tp;
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char mode[32];
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int reset;
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int baud;
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int clen;
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char parity;
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int stop;
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char c;
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sc = device_get_softc(dev);
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mtx_init(&sc->sc_mtx, "zstty", NULL, MTX_SPIN);
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sc->sc_dev = dev;
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sc->sc_iput = sc->sc_iget = sc->sc_ibuf;
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sc->sc_oget = sc->sc_obuf;
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tp = ttymalloc(NULL);
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sc->sc_si = make_dev(&zstty_cdevsw, device_get_unit(dev),
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UID_ROOT, GID_WHEEL, 0600, "%s", device_get_desc(dev));
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sc->sc_si->si_drv1 = sc;
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sc->sc_si->si_tty = tp;
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tp->t_dev = sc->sc_si;
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sc->sc_tty = tp;
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tp->t_oproc = zsttystart;
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tp->t_param = zsttyparam;
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tp->t_stop = zsttystop;
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tp->t_iflag = TTYDEF_IFLAG;
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tp->t_oflag = TTYDEF_OFLAG;
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tp->t_lflag = TTYDEF_LFLAG;
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tp->t_cflag = CREAD | CLOCAL | CS8;
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tp->t_ospeed = TTYDEF_SPEED;
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tp->t_ispeed = TTYDEF_SPEED;
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if (zstty_console(dev, mode, sizeof(mode))) {
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ttychars(tp);
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/* format: 9600,8,n,1,- */
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if (sscanf(mode, "%d,%d,%c,%d,%c", &baud, &clen, &parity,
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&stop, &c) == 5) {
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tp->t_ospeed = baud;
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tp->t_ispeed = baud;
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tp->t_cflag = CREAD | CLOCAL;
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switch (clen) {
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case 5:
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tp->t_cflag |= CS5;
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break;
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case 6:
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tp->t_cflag |= CS6;
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break;
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case 7:
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tp->t_cflag |= CS7;
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break;
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case 8:
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default:
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tp->t_cflag |= CS8;
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break;
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}
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if (parity == 'e')
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tp->t_cflag |= PARENB;
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else if (parity == 'o')
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tp->t_cflag |= PARENB | PARODD;
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if (stop == 2)
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tp->t_cflag |= CSTOPB;
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}
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device_printf(dev, "console %s\n", mode);
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sc->sc_console = 1;
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zstty_cons = sc;
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} else {
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if ((device_get_unit(dev) & 1) == 0)
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reset = ZSWR9_A_RESET;
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else
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reset = ZSWR9_B_RESET;
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ZS_WRITE_REG(sc, 9, reset);
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}
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return (0);
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}
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/*
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* Note that the rr3 value is shifted so the channel a status bits are in the
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* channel b bit positions, which makes the bit positions uniform for both
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* channels.
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*/
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static int
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zstty_intr(struct zstty_softc *sc, uint8_t rr3)
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{
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int needsoft;
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uint8_t rr0;
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uint8_t rr1;
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uint8_t c;
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int brk;
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ZSTTY_LOCK(sc);
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ZS_WRITE(sc, sc->sc_csr, ZSWR0_CLR_INTR);
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brk = 0;
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needsoft = 0;
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if ((rr3 & ZSRR3_IP_B_RX) != 0) {
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needsoft = 1;
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do {
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/*
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* First read the status, because reading the received
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* char destroys the status of this char.
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*/
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rr1 = ZS_READ_REG(sc, 1);
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c = ZS_READ(sc, sc->sc_data);
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if ((rr1 & (ZSRR1_FE | ZSRR1_DO | ZSRR1_PE)) != 0)
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ZS_WRITE(sc, sc->sc_csr, ZSWR0_RESET_ERRORS);
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#if defined(DDB) && defined(ALT_BREAK_TO_DEBUGGER)
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if (sc->sc_console != 0)
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brk = db_alt_break(c, &sc->sc_alt_break_state);
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#endif
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*sc->sc_iput++ = c;
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*sc->sc_iput++ = rr1;
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if (sc->sc_iput == sc->sc_ibuf + sizeof(sc->sc_ibuf))
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sc->sc_iput = sc->sc_ibuf;
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} while ((ZS_READ(sc, sc->sc_csr) & ZSRR0_RX_READY) != 0);
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}
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if ((rr3 & ZSRR3_IP_B_STAT) != 0) {
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rr0 = ZS_READ(sc, sc->sc_csr);
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ZS_WRITE(sc, sc->sc_csr, ZSWR0_RESET_STATUS);
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#if defined(DDB) && defined(BREAK_TO_DEBUGGER)
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if (sc->sc_console != 0 && (rr0 & ZSRR0_BREAK) != 0)
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brk = 1;
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#endif
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/* XXX do something about flow control */
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}
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if ((rr3 & ZSRR3_IP_B_TX) != 0) {
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/*
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* If we've delayed a paramter change, do it now.
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*/
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if (sc->sc_preg_held) {
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sc->sc_preg_held = 0;
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zstty_load_regs(sc);
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}
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if (sc->sc_ocnt > 0) {
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ZS_WRITE(sc, sc->sc_data, *sc->sc_oget++);
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sc->sc_ocnt--;
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} else {
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/*
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* Disable transmit completion interrupts if
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* necessary.
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*/
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if ((sc->sc_preg[1] & ZSWR1_TIE) != 0) {
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sc->sc_preg[1] &= ~ZSWR1_TIE;
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sc->sc_creg[1] = sc->sc_preg[1];
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ZS_WRITE_REG(sc, 1, sc->sc_creg[1]);
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}
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sc->sc_tx_done = 1;
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sc->sc_tx_busy = 0;
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needsoft = 1;
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}
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}
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ZSTTY_UNLOCK(sc);
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if (brk != 0)
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breakpoint();
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return (needsoft);
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}
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static void
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zstty_softintr(struct zstty_softc *sc)
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{
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struct tty *tp = sc->sc_tty;
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int data;
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int stat;
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if ((tp->t_state & TS_ISOPEN) == 0)
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return;
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while (sc->sc_iget != sc->sc_iput) {
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data = *sc->sc_iget++;
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stat = *sc->sc_iget++;
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if ((stat & ZSRR1_PE) != 0)
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data |= TTY_PE;
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if ((stat & ZSRR1_FE) != 0)
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data |= TTY_FE;
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if (sc->sc_iget == sc->sc_ibuf + sizeof(sc->sc_ibuf))
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sc->sc_iget = sc->sc_ibuf;
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(*linesw[tp->t_line].l_rint)(data, tp);
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}
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if (sc->sc_tx_done != 0) {
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sc->sc_tx_done = 0;
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tp->t_state &= ~TS_BUSY;
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(*linesw[tp->t_line].l_start)(tp);
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}
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}
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|
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static int
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zsttyopen(dev_t dev, int flags, int mode, struct thread *td)
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{
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struct zstty_softc *sc;
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struct tty *tp;
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int error;
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sc = dev->si_drv1;
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tp = dev->si_tty;
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if ((tp->t_state & TS_ISOPEN) != 0 &&
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(tp->t_state & TS_XCLUDE) != 0 &&
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!suser(td))
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return (EBUSY);
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if ((tp->t_state & TS_ISOPEN) == 0) {
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struct termios t;
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/*
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* Enable receive and status interrupts in zstty_param.
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*/
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sc->sc_preg[1] |= ZSWR1_RIE | ZSWR1_SIE;
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sc->sc_iput = sc->sc_iget = sc->sc_ibuf;
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/*
|
|
* Initialize the termios status to the defaults. Add in the
|
|
* sticky bits from TIOCSFLAGS.
|
|
*/
|
|
t.c_ispeed = 0;
|
|
t.c_ospeed = tp->t_ospeed;
|
|
t.c_cflag = TTYDEF_CFLAG;
|
|
/* Make sure zstty_param() will do something. */
|
|
tp->t_ospeed = 0;
|
|
(void)zstty_param(sc, tp, &t);
|
|
tp->t_iflag = TTYDEF_IFLAG;
|
|
tp->t_oflag = TTYDEF_OFLAG;
|
|
tp->t_lflag = TTYDEF_LFLAG;
|
|
ttychars(tp);
|
|
ttsetwater(tp);
|
|
|
|
/* XXX turn on DTR */
|
|
|
|
/* XXX handle initial DCD */
|
|
}
|
|
|
|
error = ttyopen(dev, tp);
|
|
if (error != 0)
|
|
return (error);
|
|
|
|
error = (*linesw[tp->t_line].l_open)(dev, tp);
|
|
if (error != 0)
|
|
return (error);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
zsttyclose(dev_t dev, int flags, int mode, struct thread *td)
|
|
{
|
|
struct tty *tp;
|
|
|
|
tp = dev->si_tty;
|
|
|
|
if ((tp->t_state & TS_ISOPEN) == 0)
|
|
return (0);
|
|
|
|
(*linesw[tp->t_line].l_close)(tp, flags);
|
|
ttyclose(tp);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
zsttyioctl(dev_t dev, u_long cmd, caddr_t data, int flags, struct thread *td)
|
|
{
|
|
struct zstty_softc *sc;
|
|
struct tty *tp;
|
|
int error;
|
|
|
|
sc = dev->si_drv1;
|
|
tp = dev->si_tty;
|
|
|
|
error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flags, td);
|
|
if (error != ENOIOCTL)
|
|
return (error);
|
|
|
|
error = ttioctl(tp, cmd, data, flags);
|
|
if (error != ENOIOCTL)
|
|
return (error);
|
|
|
|
error = 0;
|
|
switch (cmd) {
|
|
case TIOCSBRK:
|
|
ZS_WRITE_REG(sc, 5, ZS_READ_REG(sc, 5) | ZSWR5_BREAK);
|
|
break;
|
|
case TIOCCBRK:
|
|
ZS_WRITE_REG(sc, 5, ZS_READ_REG(sc, 5) & ~ZSWR5_BREAK);
|
|
break;
|
|
case TIOCSDTR:
|
|
zstty_mdmctrl(sc, TIOCM_DTR, DMBIS);
|
|
break;
|
|
case TIOCCDTR:
|
|
zstty_mdmctrl(sc, TIOCM_DTR, DMBIC);
|
|
break;
|
|
case TIOCMBIS:
|
|
zstty_mdmctrl(sc, *((int *)data), DMBIS);
|
|
break;
|
|
case TIOCMBIC:
|
|
zstty_mdmctrl(sc, *((int *)data), DMBIC);
|
|
break;
|
|
case TIOCMGET:
|
|
*((int *)data) = zstty_mdmctrl(sc, 0, DMGET);
|
|
break;
|
|
case TIOCMSET:
|
|
zstty_mdmctrl(sc, *((int *)data), DMSET);
|
|
break;
|
|
default:
|
|
error = ENOTTY;
|
|
break;
|
|
}
|
|
|
|
return (error);
|
|
}
|
|
|
|
static void
|
|
zsttystart(struct tty *tp)
|
|
{
|
|
struct zstty_softc *sc;
|
|
uint8_t c;
|
|
|
|
sc = tp->t_dev->si_drv1;
|
|
|
|
if ((tp->t_state & TS_TBLOCK) != 0)
|
|
/* XXX clear RTS */;
|
|
else
|
|
/* XXX set RTS */;
|
|
|
|
if ((tp->t_state & (TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) != 0) {
|
|
ttwwakeup(tp);
|
|
return;
|
|
}
|
|
|
|
if (tp->t_outq.c_cc <= tp->t_olowat) {
|
|
if ((tp->t_state & TS_SO_OLOWAT) != 0) {
|
|
tp->t_state &= ~TS_SO_OLOWAT;
|
|
wakeup(TSA_OLOWAT(tp));
|
|
}
|
|
selwakeup(&tp->t_wsel);
|
|
if (tp->t_outq.c_cc == 0) {
|
|
if ((tp->t_state & (TS_BUSY | TS_SO_OCOMPLETE)) ==
|
|
TS_SO_OCOMPLETE && tp->t_outq.c_cc == 0) {
|
|
tp->t_state &= ~TS_SO_OCOMPLETE;
|
|
wakeup(TSA_OCOMPLETE(tp));
|
|
}
|
|
return;
|
|
}
|
|
}
|
|
|
|
sc->sc_ocnt = q_to_b(&tp->t_outq, sc->sc_obuf, sizeof(sc->sc_obuf));
|
|
if (sc->sc_ocnt == 0)
|
|
return;
|
|
c = sc->sc_obuf[0];
|
|
sc->sc_oget = sc->sc_obuf + 1;
|
|
sc->sc_ocnt--;
|
|
|
|
tp->t_state |= TS_BUSY;
|
|
sc->sc_tx_busy = 1;
|
|
|
|
/*
|
|
* Enable transmit interrupts if necessary and send the first
|
|
* character to start up the transmitter.
|
|
*/
|
|
if ((sc->sc_preg[1] & ZSWR1_TIE) == 0) {
|
|
sc->sc_preg[1] |= ZSWR1_TIE;
|
|
sc->sc_creg[1] = sc->sc_preg[1];
|
|
ZS_WRITE_REG(sc, 1, sc->sc_creg[1]);
|
|
}
|
|
ZS_WRITE(sc, sc->sc_data, c);
|
|
|
|
ttwwakeup(tp);
|
|
}
|
|
|
|
static void
|
|
zsttystop(struct tty *tp, int flag)
|
|
{
|
|
struct zstty_softc *sc;
|
|
|
|
sc = tp->t_dev->si_drv1;
|
|
|
|
if ((flag & FREAD) != 0) {
|
|
/* XXX stop reading, anything to do? */;
|
|
}
|
|
|
|
if ((flag & FWRITE) != 0) {
|
|
if ((tp->t_state & TS_BUSY) != 0) {
|
|
/* XXX do what? */
|
|
if ((tp->t_state & TS_TTSTOP) == 0)
|
|
tp->t_state |= TS_FLUSH;
|
|
}
|
|
}
|
|
}
|
|
|
|
static int
|
|
zsttyparam(struct tty *tp, struct termios *t)
|
|
{
|
|
struct zstty_softc *sc;
|
|
|
|
sc = tp->t_dev->si_drv1;
|
|
return (zstty_param(sc, tp, t));
|
|
}
|
|
|
|
static int
|
|
zstty_mdmctrl(struct zstty_softc *sc, int bits, int how)
|
|
{
|
|
/* XXX implement! */
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
zstty_param(struct zstty_softc *sc, struct tty *tp, struct termios *t)
|
|
{
|
|
tcflag_t cflag;
|
|
uint8_t wr3;
|
|
uint8_t wr4;
|
|
uint8_t wr5;
|
|
int ospeed;
|
|
|
|
ospeed = zstty_speed(sc, t->c_ospeed);
|
|
if (ospeed < 0 || (t->c_ispeed && t->c_ispeed != t->c_ospeed))
|
|
return (EINVAL);
|
|
|
|
/*
|
|
* If there were no changes, don't do anything. This avoids dropping
|
|
* input and improves performance when all we did was frob things like
|
|
* VMIN and VTIME.
|
|
*/
|
|
if (tp->t_ospeed == t->c_ospeed &&
|
|
tp->t_cflag == t->c_cflag)
|
|
return (0);
|
|
|
|
zstty_mdmctrl(sc, TIOCM_DTR,
|
|
(t->c_ospeed == 0) ? DMBIC : DMBIS);
|
|
|
|
cflag = t->c_cflag;
|
|
|
|
if (sc->sc_console != 0) {
|
|
cflag |= CLOCAL;
|
|
cflag &= ~HUPCL;
|
|
}
|
|
|
|
wr3 = ZSWR3_RX_ENABLE;
|
|
wr5 = ZSWR5_TX_ENABLE | ZSWR5_DTR | ZSWR5_RTS;
|
|
|
|
switch (cflag & CSIZE) {
|
|
case CS5:
|
|
wr3 |= ZSWR3_RX_5;
|
|
wr5 |= ZSWR5_TX_5;
|
|
break;
|
|
case CS6:
|
|
wr3 |= ZSWR3_RX_6;
|
|
wr5 |= ZSWR5_TX_6;
|
|
break;
|
|
case CS7:
|
|
wr3 |= ZSWR3_RX_7;
|
|
wr5 |= ZSWR5_TX_7;
|
|
break;
|
|
case CS8:
|
|
default:
|
|
wr3 |= ZSWR3_RX_8;
|
|
wr5 |= ZSWR5_TX_8;
|
|
break;
|
|
}
|
|
|
|
wr4 = ZSWR4_CLK_X16 | (cflag & CSTOPB ? ZSWR4_TWOSB : ZSWR4_ONESB);
|
|
if ((cflag & PARODD) == 0)
|
|
wr4 |= ZSWR4_EVENP;
|
|
if (cflag & PARENB)
|
|
wr4 |= ZSWR4_PARENB;
|
|
|
|
tp->t_ispeed = 0;
|
|
tp->t_ospeed = t->c_ospeed;
|
|
tp->t_cflag = cflag;
|
|
|
|
ttsetwater(tp);
|
|
|
|
ZSTTY_LOCK(sc);
|
|
|
|
sc->sc_preg[3] = wr3;
|
|
sc->sc_preg[4] = wr4;
|
|
sc->sc_preg[5] = wr5;
|
|
|
|
zstty_set_speed(sc, ospeed);
|
|
|
|
if (cflag & CRTSCTS)
|
|
sc->sc_preg[15] |= ZSWR15_CTS_IE;
|
|
else
|
|
sc->sc_preg[15] &= ~ZSWR15_CTS_IE;
|
|
|
|
zstty_load_regs(sc);
|
|
|
|
ZSTTY_UNLOCK(sc);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static void
|
|
zstty_flush(struct zstty_softc *sc)
|
|
{
|
|
uint8_t rr0;
|
|
uint8_t rr1;
|
|
uint8_t c;
|
|
|
|
for (;;) {
|
|
rr0 = ZS_READ(sc, sc->sc_csr);
|
|
if ((rr0 & ZSRR0_RX_READY) == 0)
|
|
break;
|
|
|
|
rr1 = ZS_READ_REG(sc, 1);
|
|
c = ZS_READ(sc, sc->sc_data);
|
|
|
|
if (rr1 & (ZSRR1_FE | ZSRR1_DO | ZSRR1_PE))
|
|
ZS_WRITE(sc, sc->sc_data, ZSWR0_RESET_ERRORS);
|
|
}
|
|
}
|
|
|
|
static void
|
|
zstty_load_regs(struct zstty_softc *sc)
|
|
{
|
|
|
|
/*
|
|
* If the transmitter may be active, just hold the change and do it
|
|
* in the tx interrupt handler. Changing the registers while tx is
|
|
* active may hang the chip.
|
|
*/
|
|
if (sc->sc_tx_busy != 0) {
|
|
sc->sc_preg_held = 1;
|
|
return;
|
|
}
|
|
|
|
/* If the regs are the same do nothing. */
|
|
if (bcmp(sc->sc_preg, sc->sc_creg, 16) == 0)
|
|
return;
|
|
|
|
bcopy(sc->sc_preg, sc->sc_creg, 16);
|
|
|
|
/* XXX: reset error condition */
|
|
ZS_WRITE(sc, sc->sc_csr, ZSM_RESET_ERR);
|
|
|
|
/* disable interrupts */
|
|
ZS_WRITE_REG(sc, 1, sc->sc_creg[1] & ~ZSWR1_IMASK);
|
|
|
|
/* baud clock divisor, stop bits, parity */
|
|
ZS_WRITE_REG(sc, 4, sc->sc_creg[4]);
|
|
|
|
/* misc. TX/RX control bits */
|
|
ZS_WRITE_REG(sc, 10, sc->sc_creg[10]);
|
|
|
|
/* char size, enable (RX/TX) */
|
|
ZS_WRITE_REG(sc, 3, sc->sc_creg[3] & ~ZSWR3_RX_ENABLE);
|
|
ZS_WRITE_REG(sc, 5, sc->sc_creg[5] & ~ZSWR5_TX_ENABLE);
|
|
|
|
/* Shut down the BRG */
|
|
ZS_WRITE_REG(sc, 14, sc->sc_creg[14] & ~ZSWR14_BAUD_ENA);
|
|
|
|
/* clock mode control */
|
|
ZS_WRITE_REG(sc, 11, sc->sc_creg[11]);
|
|
|
|
/* baud rate (lo/hi) */
|
|
ZS_WRITE_REG(sc, 12, sc->sc_creg[12]);
|
|
ZS_WRITE_REG(sc, 13, sc->sc_creg[13]);
|
|
|
|
/* Misc. control bits */
|
|
ZS_WRITE_REG(sc, 14, sc->sc_creg[14]);
|
|
|
|
/* which lines cause status interrupts */
|
|
ZS_WRITE_REG(sc, 15, sc->sc_creg[15]);
|
|
|
|
/*
|
|
* Zilog docs recommend resetting external status twice at this
|
|
* point. Mainly as the status bits are latched, and the first
|
|
* interrupt clear might unlatch them to new values, generating
|
|
* a second interrupt request.
|
|
*/
|
|
ZS_WRITE(sc, sc->sc_csr, ZSM_RESET_STINT);
|
|
ZS_WRITE(sc, sc->sc_csr, ZSM_RESET_STINT);
|
|
|
|
/* char size, enable (RX/TX)*/
|
|
ZS_WRITE_REG(sc, 3, sc->sc_creg[3]);
|
|
ZS_WRITE_REG(sc, 5, sc->sc_creg[5]);
|
|
|
|
/* interrupt enables: RX, TX, STATUS */
|
|
ZS_WRITE_REG(sc, 1, sc->sc_creg[1]);
|
|
}
|
|
|
|
static int
|
|
zstty_speed(struct zstty_softc *sc, int rate)
|
|
{
|
|
int tconst;
|
|
|
|
if (rate == 0)
|
|
return (0);
|
|
tconst = BPS_TO_TCONST(sc->sc_brg_clk, rate);
|
|
if (tconst < 0 || TCONST_TO_BPS(sc->sc_brg_clk, tconst) != rate)
|
|
return (-1);
|
|
return (tconst);
|
|
}
|
|
|
|
static void
|
|
zs_cnprobe(struct consdev *cn)
|
|
{
|
|
struct zstty_softc *sc = zstty_cons;
|
|
|
|
if (sc == NULL)
|
|
cn->cn_pri = CN_DEAD;
|
|
else {
|
|
cn->cn_pri = CN_REMOTE;
|
|
strcpy(cn->cn_name, devtoname(sc->sc_si));
|
|
cn->cn_tp = sc->sc_tty;
|
|
}
|
|
}
|
|
|
|
static void
|
|
zs_cninit(struct consdev *cn)
|
|
{
|
|
}
|
|
|
|
static void
|
|
zs_cnterm(struct consdev *cn)
|
|
{
|
|
}
|
|
|
|
static int
|
|
zs_cngetc(struct consdev *cn)
|
|
{
|
|
struct zstty_softc *sc = zstty_cons;
|
|
|
|
if (sc == NULL)
|
|
return (-1);
|
|
return (zstty_cngetc(sc));
|
|
}
|
|
|
|
static int
|
|
zs_cncheckc(struct consdev *cn)
|
|
{
|
|
struct zstty_softc *sc = zstty_cons;
|
|
|
|
if (sc == NULL)
|
|
return (-1);
|
|
return (zstty_cncheckc(sc));
|
|
}
|
|
|
|
static void
|
|
zs_cnputc(struct consdev *cn, int c)
|
|
{
|
|
struct zstty_softc *sc = zstty_cons;
|
|
|
|
if (sc == NULL)
|
|
return;
|
|
zstty_cnputc(sc, c);
|
|
}
|
|
|
|
static void
|
|
zs_cndbctl(struct consdev *cn, int c)
|
|
{
|
|
}
|
|
|
|
static void
|
|
zstty_cnopen(struct zstty_softc *sc)
|
|
{
|
|
}
|
|
|
|
static void
|
|
zstty_cnclose(struct zstty_softc *sc)
|
|
{
|
|
}
|
|
|
|
static int
|
|
zstty_cngetc(struct zstty_softc *sc)
|
|
{
|
|
uint8_t c;
|
|
|
|
zstty_cnopen(sc);
|
|
while ((ZS_READ(sc, sc->sc_csr) & ZSRR0_RX_READY) == 0)
|
|
;
|
|
c = ZS_READ(sc, sc->sc_data);
|
|
zstty_cnclose(sc);
|
|
return (c);
|
|
}
|
|
|
|
static int
|
|
zstty_cncheckc(struct zstty_softc *sc)
|
|
{
|
|
int c;
|
|
|
|
c = -1;
|
|
zstty_cnopen(sc);
|
|
if ((ZS_READ(sc, sc->sc_csr) & ZSRR0_RX_READY) != 0)
|
|
c = ZS_READ(sc, sc->sc_data);
|
|
zstty_cnclose(sc);
|
|
return (c);
|
|
}
|
|
|
|
static void
|
|
zstty_cnputc(struct zstty_softc *sc, int c)
|
|
{
|
|
|
|
zstty_cnopen(sc);
|
|
while ((ZS_READ(sc, sc->sc_csr) & ZSRR0_TX_READY) == 0)
|
|
;
|
|
ZS_WRITE(sc, sc->sc_data, c);
|
|
zstty_cnclose(sc);
|
|
}
|