156 lines
5.1 KiB
C
156 lines
5.1 KiB
C
/*-
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* Copyright (c) 1995, 1996 Carnegie-Mellon University.
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* All rights reserved.
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*
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* Author: Chris G. Demetriou
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*
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* Permission to use, copy, modify and distribute this software and
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* its documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
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* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie the
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* rights to redistribute these changes.
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*
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* Copyright (c) 2000 Andrew Miklic
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*
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* $FreeBSD$
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*/
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#ifndef _FB_TGA_H_
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#define _FB_TGA_H_
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/* TGA-specific FB stuff */
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struct gfb_softc;
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struct video_adapter;
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/*
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* Register definitions for the Brooktree Bt463 135MHz Monolithic
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* CMOS TrueVu RAMDAC.
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*/
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/*
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* Directly-accessible registers. Note the address register is
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* auto-incrementing.
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*/
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#define BT463_REG_ADDR_LOW 0x00 /* C1,C0 == 0,0 */
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#define BT463_REG_ADDR_HIGH 0x01 /* C1,C0 == 0,1 */
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#define BT463_REG_IREG_DATA 0x02 /* C1,C0 == 1,0 */
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#define BT463_REG_CMAP_DATA 0x03 /* C1,C0 == 1,1 */
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#define BT463_REG_MAX BT463_REG_CMAP_DATA
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/*
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* All internal register access to the Bt463 is done indirectly via the
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* Address Register (mapped into the host bus in a device-specific
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* fashion). The following register definitions are in terms of
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* their address register address values.
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*/
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/* C1,C0 must be 1,0 */
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#define BT463_IREG_CURSOR_COLOR_0 0x0100 /* 3 r/w cycles */
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#define BT463_IREG_CURSOR_COLOR_1 0x0101 /* 3 r/w cycles */
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#define BT463_IREG_ID 0x0200
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#define BT463_IREG_COMMAND_0 0x0201
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#define BT463_IREG_COMMAND_1 0x0202
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#define BT463_IREG_COMMAND_2 0x0203
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#define BT463_IREG_READ_MASK_P0_P7 0x0205
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#define BT463_IREG_READ_MASK_P8_P15 0x0206
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#define BT463_IREG_READ_MASK_P16_P23 0x0207
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#define BT463_IREG_READ_MASK_P24_P27 0x0208
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#define BT463_IREG_BLINK_MASK_P0_P7 0x0209
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#define BT463_IREG_BLINK_MASK_P8_P15 0x020a
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#define BT463_IREG_BLINK_MASK_P16_P23 0x020b
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#define BT463_IREG_BLINK_MASK_P24_P27 0x020c
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#define BT463_IREG_TEST 0x020d
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#define BT463_IREG_INPUT_SIG 0x020e /* 2 of 3 r/w cycles */
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#define BT463_IREG_OUTPUT_SIG 0x020f /* 3 r/w cycles */
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#define BT463_IREG_REVISION 0x0220
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#define BT463_IREG_WINDOW_TYPE_TABLE 0x0300 /* 3 r/w cycles */
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#define BT463_NWTYPE_ENTRIES 0x10 /* 16 window type entries */
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/* C1,C0 must be 1,1 */
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#define BT463_IREG_CPALETTE_RAM 0x0000 /* 3 r/w cycles */
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#define BT463_NCMAP_ENTRIES 0x210 /* 528 CMAP entries */
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#define BT463_DATA_CURCMAP_CHANGED 0x01 /* cursor colormap changed */
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#define BT463_DATA_CMAP_CHANGED 0x02 /* colormap changed */
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#define BT463_DATA_WTYPE_CHANGED 0x04 /* window type table changed */
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#define BT463_DATA_ALL_CHANGED 0x07
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/*
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* Register definitions for the Brooktree Bt485A 170MHz Monolithic
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* CMOS True-Color RAMDAC.
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*/
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/*
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* Directly-addressed registers.
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*/
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#define BT485_REG_PCRAM_WRADDR 0x00
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#define BT485_REG_PALETTE 0x01
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#define BT485_REG_PIXMASK 0x02
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#define BT485_REG_PCRAM_RDADDR 0x03
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#define BT485_REG_COC_WRADDR 0x04
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#define BT485_REG_COCDATA 0x05
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#define BT485_REG_COMMAND_0 0x06
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#define BT485_REG_COC_RDADDR 0x07
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#define BT485_REG_COMMAND_1 0x08
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#define BT485_REG_COMMAND_2 0x09
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#define BT485_REG_STATUS 0x0a
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#define BT485_REG_EXTENDED BT485_REG_STATUS
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#define BT485_REG_CURSOR_RAM 0x0b
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#define BT485_REG_CURSOR_X_LOW 0x0c
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#define BT485_REG_CURSOR_X_HIGH 0x0d
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#define BT485_REG_CURSOR_Y_LOW 0x0e
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#define BT485_REG_CURSOR_Y_HIGH 0x0f
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#define BT485_REG_MAX 0x0f
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#define BT485_IREG_STATUS 0x00
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#define BT485_IREG_COMMAND_3 0x01
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#define BT485_IREG_COMMAND_4 0x02
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#define BT485_IREG_RSA 0x20
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#define BT485_IREG_GSA 0x21
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#define BT485_IREG_BSA 0x22
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#define BT485_DATA_ENB_CHANGED 0x01 /* cursor enable changed */
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#define BT485_DATA_CURCMAP_CHANGED 0x02 /* cursor colormap changed */
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#define BT485_DATA_CURSHAPE_CHANGED 0x04 /* cursor size, image, mask changed */
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#define BT485_DATA_CMAP_CHANGED 0x08 /* colormap changed */
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#define BT485_DATA_ALL_CHANGED 0x0f
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#define CURSOR_MAX_SIZE 64
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#define TGA_DRIVER_NAME "tga"
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#define TGA2_DRIVER_NAME "tga2"
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#define BTWREG(sc, addr, val) \
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sc->gfbc->ramdac_wr((sc), BT463_REG_ADDR_LOW, (addr) & 0xff); \
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sc->gfbc->ramdac_wr((sc), BT463_REG_ADDR_HIGH, ((addr) >> 8) & 0xff);\
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(sc)->gfbc->ramdac_wr((sc), BT463_REG_IREG_DATA, (val))
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#define BTWNREG(sc, val) \
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(sc)->gfbc->ramdac_wr((sc), BT463_REG_IREG_DATA, (val))
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#define BTRREG(sc, addr) \
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sc->gfbc->ramdac_wr((sc), BT463_REG_ADDR_LOW, (addr) & 0xff); \
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sc->gfbc->ramdac_wr((sc), BT463_REG_ADDR_HIGH, ((addr) >> 8) & 0xff);\
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(sc)->gfbc->ramdac_rd((sc), BT463_REG_IREG_DATA)
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#define BTRNREG(sc) \
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(sc)->gfbc->ramdac_rd((sc), BT463_REG_IREG_DATA)
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#endif /* _FB_TGA_H_ */
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