512071de53
On e500v2 SoCs it will now print: cpu0: Features 84e08000<PPC32,MMU,SPE,EFPS,EFPD,BOOKE> at bootup.
674 lines
19 KiB
C
674 lines
19 KiB
C
/*-
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* Copyright (c) 2001 Matt Thomas.
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* Copyright (c) 2001 Tsubai Masanari.
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* Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by
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* Internet Research Institute, Inc.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*-
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* Copyright (C) 2003 Benno Rice.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* from $NetBSD: cpu_subr.c,v 1.1 2003/02/03 17:10:09 matt Exp $
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* $FreeBSD$
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/cpu.h>
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#include <sys/kernel.h>
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#include <sys/proc.h>
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#include <sys/sysctl.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/hid.h>
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#include <machine/md_var.h>
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#include <machine/smp.h>
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#include <machine/spr.h>
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#include <dev/ofw/openfirm.h>
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static void cpu_6xx_setup(int cpuid, uint16_t vers);
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static void cpu_970_setup(int cpuid, uint16_t vers);
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static void cpu_booke_setup(int cpuid, uint16_t vers);
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int powerpc_pow_enabled;
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void (*cpu_idle_hook)(sbintime_t) = NULL;
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static void cpu_idle_60x(sbintime_t);
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static void cpu_idle_booke(sbintime_t);
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struct cputab {
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const char *name;
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uint16_t version;
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uint16_t revfmt;
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int features; /* Do not include PPC_FEATURE_32 or
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* PPC_FEATURE_HAS_MMU */
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int features2;
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void (*cpu_setup)(int cpuid, uint16_t vers);
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};
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#define REVFMT_MAJMIN 1 /* %u.%u */
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#define REVFMT_HEX 2 /* 0x%04x */
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#define REVFMT_DEC 3 /* %u */
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static const struct cputab models[] = {
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{ "Motorola PowerPC 601", MPC601, REVFMT_DEC,
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PPC_FEATURE_HAS_FPU | PPC_FEATURE_UNIFIED_CACHE, 0, cpu_6xx_setup },
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{ "Motorola PowerPC 602", MPC602, REVFMT_DEC,
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PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
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{ "Motorola PowerPC 603", MPC603, REVFMT_MAJMIN,
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PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
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{ "Motorola PowerPC 603e", MPC603e, REVFMT_MAJMIN,
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PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
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{ "Motorola PowerPC 603ev", MPC603ev, REVFMT_MAJMIN,
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PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
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{ "Motorola PowerPC 604", MPC604, REVFMT_MAJMIN,
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PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
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{ "Motorola PowerPC 604ev", MPC604ev, REVFMT_MAJMIN,
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PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
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{ "Motorola PowerPC 620", MPC620, REVFMT_HEX,
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PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU, 0, NULL },
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{ "Motorola PowerPC 750", MPC750, REVFMT_MAJMIN,
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PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
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{ "IBM PowerPC 750FX", IBM750FX, REVFMT_MAJMIN,
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PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
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{ "IBM PowerPC 970", IBM970, REVFMT_MAJMIN,
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PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU,
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0, cpu_970_setup },
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{ "IBM PowerPC 970FX", IBM970FX, REVFMT_MAJMIN,
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PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU,
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0, cpu_970_setup },
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{ "IBM PowerPC 970GX", IBM970GX, REVFMT_MAJMIN,
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PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU,
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0, cpu_970_setup },
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{ "IBM PowerPC 970MP", IBM970MP, REVFMT_MAJMIN,
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PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU,
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0, cpu_970_setup },
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{ "IBM POWER4", IBMPOWER4, REVFMT_MAJMIN,
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PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU, 0, NULL },
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{ "IBM POWER4+", IBMPOWER4PLUS, REVFMT_MAJMIN,
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PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU, 0, NULL },
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{ "IBM POWER5", IBMPOWER5, REVFMT_MAJMIN,
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PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU | PPC_FEATURE_SMT, 0, NULL },
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{ "IBM POWER5+", IBMPOWER5PLUS, REVFMT_MAJMIN,
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PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU | PPC_FEATURE_SMT, 0, NULL },
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{ "IBM POWER6", IBMPOWER6, REVFMT_MAJMIN,
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PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
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PPC_FEATURE_SMT | PPC_FEATURE_ARCH_2_05, 0, NULL },
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{ "IBM POWER7", IBMPOWER7, REVFMT_MAJMIN,
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PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
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PPC_FEATURE_SMT | PPC_FEATURE_ARCH_2_05 | PPC_FEATURE_ARCH_2_06 |
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PPC_FEATURE_HAS_VSX, 0, NULL },
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{ "IBM POWER7+", IBMPOWER7PLUS, REVFMT_MAJMIN,
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PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
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PPC_FEATURE_SMT | PPC_FEATURE_ARCH_2_05 | PPC_FEATURE_ARCH_2_06 |
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PPC_FEATURE_HAS_VSX, 0, NULL },
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{ "IBM POWER8E", IBMPOWER8E, REVFMT_MAJMIN,
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PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
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PPC_FEATURE_SMT | PPC_FEATURE_ARCH_2_05 | PPC_FEATURE_ARCH_2_06 |
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PPC_FEATURE_HAS_VSX,
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PPC_FEATURE2_ARCH_2_07 | PPC_FEATURE2_HAS_HTM |
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PPC_FEATURE2_HAS_VCRYPTO, NULL },
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{ "IBM POWER8", IBMPOWER8, REVFMT_MAJMIN,
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PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
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PPC_FEATURE_SMT | PPC_FEATURE_ARCH_2_05 | PPC_FEATURE_ARCH_2_06 |
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PPC_FEATURE_HAS_VSX,
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PPC_FEATURE2_ARCH_2_07 | PPC_FEATURE2_HAS_HTM |
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PPC_FEATURE2_HAS_VCRYPTO, NULL },
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{ "Motorola PowerPC 7400", MPC7400, REVFMT_MAJMIN,
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PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
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{ "Motorola PowerPC 7410", MPC7410, REVFMT_MAJMIN,
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PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
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{ "Motorola PowerPC 7450", MPC7450, REVFMT_MAJMIN,
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PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
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{ "Motorola PowerPC 7455", MPC7455, REVFMT_MAJMIN,
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PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
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{ "Motorola PowerPC 7457", MPC7457, REVFMT_MAJMIN,
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PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
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{ "Motorola PowerPC 7447A", MPC7447A, REVFMT_MAJMIN,
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PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
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{ "Motorola PowerPC 7448", MPC7448, REVFMT_MAJMIN,
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PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
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{ "Motorola PowerPC 8240", MPC8240, REVFMT_MAJMIN,
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PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
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{ "Motorola PowerPC 8245", MPC8245, REVFMT_MAJMIN,
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PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup },
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{ "Freescale e500v1 core", FSL_E500v1, REVFMT_MAJMIN,
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PPC_FEATURE_BOOKE | PPC_FEATURE_HAS_SPE | PPC_FEATURE_HAS_EFP_SINGLE,
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0, cpu_booke_setup },
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{ "Freescale e500v2 core", FSL_E500v2, REVFMT_MAJMIN,
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PPC_FEATURE_BOOKE | PPC_FEATURE_HAS_SPE |
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PPC_FEATURE_HAS_EFP_SINGLE | PPC_FEATURE_HAS_EFP_DOUBLE, 0,
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cpu_booke_setup },
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{ "Freescale e500mc core", FSL_E500mc, REVFMT_MAJMIN,
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PPC_FEATURE_BOOKE | PPC_FEATURE_HAS_FPU, 0, cpu_booke_setup },
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{ "Freescale e5500 core", FSL_E5500, REVFMT_MAJMIN,
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PPC_FEATURE_BOOKE | PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU, 0,
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cpu_booke_setup },
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{ "Freescale e6500 core", FSL_E6500, REVFMT_MAJMIN,
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PPC_FEATURE_BOOKE | PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC |
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PPC_FEATURE_HAS_FPU, 0, cpu_booke_setup },
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{ "IBM Cell Broadband Engine", IBMCELLBE, REVFMT_MAJMIN,
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PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU |
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PPC_FEATURE_SMT, 0, NULL},
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{ "Unknown PowerPC CPU", 0, REVFMT_HEX, 0, 0, NULL },
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};
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static void cpu_6xx_print_cacheinfo(u_int, uint16_t);
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static int cpu_feature_bit(SYSCTL_HANDLER_ARGS);
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static char model[64];
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SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, model, 0, "");
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int cpu_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU;
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int cpu_features2 = 0;
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SYSCTL_OPAQUE(_hw, OID_AUTO, cpu_features, CTLFLAG_RD,
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&cpu_features, sizeof(cpu_features), "IX", "PowerPC CPU features");
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SYSCTL_OPAQUE(_hw, OID_AUTO, cpu_features2, CTLFLAG_RD,
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&cpu_features2, sizeof(cpu_features2), "IX", "PowerPC CPU features 2");
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/* Provide some user-friendly aliases for bits in cpu_features */
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SYSCTL_PROC(_hw, OID_AUTO, floatingpoint, CTLTYPE_INT | CTLFLAG_RD,
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0, PPC_FEATURE_HAS_FPU, cpu_feature_bit, "I",
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"Floating point instructions executed in hardware");
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SYSCTL_PROC(_hw, OID_AUTO, altivec, CTLTYPE_INT | CTLFLAG_RD,
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0, PPC_FEATURE_HAS_ALTIVEC, cpu_feature_bit, "I", "CPU supports Altivec");
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void
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cpu_setup(u_int cpuid)
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{
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u_int pvr, maj, min;
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uint16_t vers, rev, revfmt;
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uint64_t cps;
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const struct cputab *cp;
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const char *name;
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pvr = mfpvr();
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vers = pvr >> 16;
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rev = pvr;
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switch (vers) {
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case MPC7410:
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min = (pvr >> 0) & 0xff;
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maj = min <= 4 ? 1 : 2;
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break;
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case FSL_E500v1:
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case FSL_E500v2:
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case FSL_E500mc:
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case FSL_E5500:
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maj = (pvr >> 4) & 0xf;
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min = (pvr >> 0) & 0xf;
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break;
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default:
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maj = (pvr >> 8) & 0xf;
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min = (pvr >> 0) & 0xf;
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}
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for (cp = models; cp->version != 0; cp++) {
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if (cp->version == vers)
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break;
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}
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revfmt = cp->revfmt;
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name = cp->name;
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if (rev == MPC750 && pvr == 15) {
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name = "Motorola MPC755";
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revfmt = REVFMT_HEX;
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}
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strncpy(model, name, sizeof(model) - 1);
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printf("cpu%d: %s revision ", cpuid, name);
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switch (revfmt) {
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case REVFMT_MAJMIN:
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printf("%u.%u", maj, min);
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break;
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case REVFMT_HEX:
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printf("0x%04x", rev);
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break;
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case REVFMT_DEC:
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printf("%u", rev);
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break;
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}
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if (cpu_est_clockrate(0, &cps) == 0)
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printf(", %jd.%02jd MHz", cps / 1000000, (cps / 10000) % 100);
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printf("\n");
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cpu_features |= cp->features;
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cpu_features2 |= cp->features2;
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printf("cpu%d: Features %b\n", cpuid, cpu_features,
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PPC_FEATURE_BITMASK);
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if (cpu_features2 != 0)
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printf("cpu%d: Features2 %b\n", cpuid, cpu_features2,
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PPC_FEATURE2_BITMASK);
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/*
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* Configure CPU
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*/
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if (cp->cpu_setup != NULL)
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cp->cpu_setup(cpuid, vers);
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}
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/* Get current clock frequency for the given cpu id. */
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int
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cpu_est_clockrate(int cpu_id, uint64_t *cps)
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{
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uint16_t vers;
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register_t msr;
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phandle_t cpu, dev, root;
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int res = 0;
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char buf[8];
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vers = mfpvr() >> 16;
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msr = mfmsr();
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mtmsr(msr & ~PSL_EE);
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switch (vers) {
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case MPC7450:
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case MPC7455:
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case MPC7457:
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case MPC750:
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case IBM750FX:
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case MPC7400:
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case MPC7410:
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case MPC7447A:
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case MPC7448:
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mtspr(SPR_MMCR0, SPR_MMCR0_FC);
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mtspr(SPR_PMC1, 0);
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mtspr(SPR_MMCR0, SPR_MMCR0_PMC1SEL(PMCN_CYCLES));
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DELAY(1000);
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*cps = (mfspr(SPR_PMC1) * 1000) + 4999;
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mtspr(SPR_MMCR0, SPR_MMCR0_FC);
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mtmsr(msr);
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return (0);
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case IBM970:
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case IBM970FX:
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case IBM970MP:
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isync();
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mtspr(SPR_970MMCR0, SPR_MMCR0_FC);
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isync();
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mtspr(SPR_970MMCR1, 0);
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mtspr(SPR_970MMCRA, 0);
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mtspr(SPR_970PMC1, 0);
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mtspr(SPR_970MMCR0,
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SPR_970MMCR0_PMC1SEL(PMC970N_CYCLES));
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isync();
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DELAY(1000);
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powerpc_sync();
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mtspr(SPR_970MMCR0, SPR_MMCR0_FC);
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*cps = (mfspr(SPR_970PMC1) * 1000) + 4999;
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mtmsr(msr);
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return (0);
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default:
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root = OF_peer(0);
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if (root == 0)
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return (ENXIO);
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dev = OF_child(root);
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while (dev != 0) {
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res = OF_getprop(dev, "name", buf, sizeof(buf));
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if (res > 0 && strcmp(buf, "cpus") == 0)
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break;
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dev = OF_peer(dev);
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}
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cpu = OF_child(dev);
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while (cpu != 0) {
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res = OF_getprop(cpu, "device_type", buf,
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sizeof(buf));
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if (res > 0 && strcmp(buf, "cpu") == 0)
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break;
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cpu = OF_peer(cpu);
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}
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if (cpu == 0)
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return (ENOENT);
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if (OF_getprop(cpu, "ibm,extended-clock-frequency",
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cps, sizeof(*cps)) >= 0) {
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return (0);
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} else if (OF_getprop(cpu, "clock-frequency", cps,
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sizeof(cell_t)) >= 0) {
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*cps >>= 32;
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return (0);
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} else {
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return (ENOENT);
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}
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}
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}
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void
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cpu_6xx_setup(int cpuid, uint16_t vers)
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{
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register_t hid0, pvr;
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const char *bitmask;
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hid0 = mfspr(SPR_HID0);
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pvr = mfpvr();
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/*
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* Configure power-saving mode.
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*/
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switch (vers) {
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case MPC603:
|
|
case MPC603e:
|
|
case MPC603ev:
|
|
case MPC604ev:
|
|
case MPC750:
|
|
case IBM750FX:
|
|
case MPC7400:
|
|
case MPC7410:
|
|
case MPC8240:
|
|
case MPC8245:
|
|
/* Select DOZE mode. */
|
|
hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP);
|
|
hid0 |= HID0_DOZE | HID0_DPM;
|
|
powerpc_pow_enabled = 1;
|
|
break;
|
|
|
|
case MPC7448:
|
|
case MPC7447A:
|
|
case MPC7457:
|
|
case MPC7455:
|
|
case MPC7450:
|
|
/* Enable the 7450 branch caches */
|
|
hid0 |= HID0_SGE | HID0_BTIC;
|
|
hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT;
|
|
/* Disable BTIC on 7450 Rev 2.0 or earlier and on 7457 */
|
|
if (((pvr >> 16) == MPC7450 && (pvr & 0xFFFF) <= 0x0200)
|
|
|| (pvr >> 16) == MPC7457)
|
|
hid0 &= ~HID0_BTIC;
|
|
/* Select NAP mode. */
|
|
hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP);
|
|
hid0 |= HID0_NAP | HID0_DPM;
|
|
powerpc_pow_enabled = 1;
|
|
break;
|
|
|
|
default:
|
|
/* No power-saving mode is available. */ ;
|
|
}
|
|
|
|
switch (vers) {
|
|
case IBM750FX:
|
|
case MPC750:
|
|
hid0 &= ~HID0_DBP; /* XXX correct? */
|
|
hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT;
|
|
break;
|
|
|
|
case MPC7400:
|
|
case MPC7410:
|
|
hid0 &= ~HID0_SPD;
|
|
hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT;
|
|
hid0 |= HID0_EIEC;
|
|
break;
|
|
|
|
}
|
|
|
|
mtspr(SPR_HID0, hid0);
|
|
|
|
if (bootverbose)
|
|
cpu_6xx_print_cacheinfo(cpuid, vers);
|
|
|
|
switch (vers) {
|
|
case MPC7447A:
|
|
case MPC7448:
|
|
case MPC7450:
|
|
case MPC7455:
|
|
case MPC7457:
|
|
bitmask = HID0_7450_BITMASK;
|
|
break;
|
|
default:
|
|
bitmask = HID0_BITMASK;
|
|
break;
|
|
}
|
|
|
|
printf("cpu%d: HID0 %b\n", cpuid, (int)hid0, bitmask);
|
|
|
|
if (cpu_idle_hook == NULL)
|
|
cpu_idle_hook = cpu_idle_60x;
|
|
}
|
|
|
|
|
|
static void
|
|
cpu_6xx_print_cacheinfo(u_int cpuid, uint16_t vers)
|
|
{
|
|
register_t hid;
|
|
|
|
hid = mfspr(SPR_HID0);
|
|
printf("cpu%u: ", cpuid);
|
|
printf("L1 I-cache %sabled, ", (hid & HID0_ICE) ? "en" : "dis");
|
|
printf("L1 D-cache %sabled\n", (hid & HID0_DCE) ? "en" : "dis");
|
|
|
|
printf("cpu%u: ", cpuid);
|
|
if (mfspr(SPR_L2CR) & L2CR_L2E) {
|
|
switch (vers) {
|
|
case MPC7450:
|
|
case MPC7455:
|
|
case MPC7457:
|
|
printf("256KB L2 cache, ");
|
|
if (mfspr(SPR_L3CR) & L3CR_L3E)
|
|
printf("%cMB L3 backside cache",
|
|
mfspr(SPR_L3CR) & L3CR_L3SIZ ? '2' : '1');
|
|
else
|
|
printf("L3 cache disabled");
|
|
printf("\n");
|
|
break;
|
|
case IBM750FX:
|
|
printf("512KB L2 cache\n");
|
|
break;
|
|
default:
|
|
switch (mfspr(SPR_L2CR) & L2CR_L2SIZ) {
|
|
case L2SIZ_256K:
|
|
printf("256KB ");
|
|
break;
|
|
case L2SIZ_512K:
|
|
printf("512KB ");
|
|
break;
|
|
case L2SIZ_1M:
|
|
printf("1MB ");
|
|
break;
|
|
}
|
|
printf("write-%s", (mfspr(SPR_L2CR) & L2CR_L2WT)
|
|
? "through" : "back");
|
|
if (mfspr(SPR_L2CR) & L2CR_L2PE)
|
|
printf(", with parity");
|
|
printf(" backside cache\n");
|
|
break;
|
|
}
|
|
} else
|
|
printf("L2 cache disabled\n");
|
|
}
|
|
|
|
static void
|
|
cpu_booke_setup(int cpuid, uint16_t vers)
|
|
{
|
|
#ifdef BOOKE_E500
|
|
register_t hid0;
|
|
|
|
hid0 = mfspr(SPR_HID0);
|
|
|
|
/* Programe power-management mode. */
|
|
hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP);
|
|
hid0 |= HID0_DOZE;
|
|
|
|
mtspr(SPR_HID0, hid0);
|
|
|
|
printf("cpu%d: HID0 %b\n", cpuid, (int)hid0, HID0_E500_BITMASK);
|
|
#endif
|
|
|
|
if (cpu_idle_hook == NULL)
|
|
cpu_idle_hook = cpu_idle_booke;
|
|
}
|
|
|
|
static void
|
|
cpu_970_setup(int cpuid, uint16_t vers)
|
|
{
|
|
#ifdef AIM
|
|
uint32_t hid0_hi, hid0_lo;
|
|
|
|
__asm __volatile ("mfspr %0,%2; clrldi %1,%0,32; srdi %0,%0,32;"
|
|
: "=r" (hid0_hi), "=r" (hid0_lo) : "K" (SPR_HID0));
|
|
|
|
/* Configure power-saving mode */
|
|
switch (vers) {
|
|
case IBM970MP:
|
|
hid0_hi |= (HID0_DEEPNAP | HID0_NAP | HID0_DPM);
|
|
hid0_hi &= ~HID0_DOZE;
|
|
break;
|
|
default:
|
|
hid0_hi |= (HID0_NAP | HID0_DPM);
|
|
hid0_hi &= ~(HID0_DOZE | HID0_DEEPNAP);
|
|
break;
|
|
}
|
|
powerpc_pow_enabled = 1;
|
|
|
|
__asm __volatile (" \
|
|
sync; isync; \
|
|
sldi %0,%0,32; or %0,%0,%1; \
|
|
mtspr %2, %0; \
|
|
mfspr %0, %2; mfspr %0, %2; mfspr %0, %2; \
|
|
mfspr %0, %2; mfspr %0, %2; mfspr %0, %2; \
|
|
sync; isync"
|
|
:: "r" (hid0_hi), "r"(hid0_lo), "K" (SPR_HID0));
|
|
|
|
__asm __volatile ("mfspr %0,%1; srdi %0,%0,32;"
|
|
: "=r" (hid0_hi) : "K" (SPR_HID0));
|
|
printf("cpu%d: HID0 %b\n", cpuid, (int)(hid0_hi), HID0_970_BITMASK);
|
|
#endif
|
|
|
|
cpu_idle_hook = cpu_idle_60x;
|
|
}
|
|
|
|
static int
|
|
cpu_feature_bit(SYSCTL_HANDLER_ARGS)
|
|
{
|
|
int result;
|
|
|
|
result = (cpu_features & arg2) ? 1 : 0;
|
|
|
|
return (sysctl_handle_int(oidp, &result, 0, req));
|
|
}
|
|
|
|
void
|
|
cpu_idle(int busy)
|
|
{
|
|
sbintime_t sbt = -1;
|
|
|
|
#ifdef INVARIANTS
|
|
if ((mfmsr() & PSL_EE) != PSL_EE) {
|
|
struct thread *td = curthread;
|
|
printf("td msr %#lx\n", (u_long)td->td_md.md_saved_msr);
|
|
panic("ints disabled in idleproc!");
|
|
}
|
|
#endif
|
|
|
|
CTR2(KTR_SPARE2, "cpu_idle(%d) at %d",
|
|
busy, curcpu);
|
|
|
|
if (cpu_idle_hook != NULL) {
|
|
if (!busy) {
|
|
critical_enter();
|
|
sbt = cpu_idleclock();
|
|
}
|
|
cpu_idle_hook(sbt);
|
|
if (!busy) {
|
|
cpu_activeclock();
|
|
critical_exit();
|
|
}
|
|
}
|
|
|
|
CTR2(KTR_SPARE2, "cpu_idle(%d) at %d done",
|
|
busy, curcpu);
|
|
}
|
|
|
|
static void
|
|
cpu_idle_60x(sbintime_t sbt)
|
|
{
|
|
register_t msr;
|
|
uint16_t vers;
|
|
|
|
if (!powerpc_pow_enabled)
|
|
return;
|
|
|
|
msr = mfmsr();
|
|
vers = mfpvr() >> 16;
|
|
|
|
#ifdef AIM
|
|
switch (vers) {
|
|
case IBM970:
|
|
case IBM970FX:
|
|
case IBM970MP:
|
|
case MPC7447A:
|
|
case MPC7448:
|
|
case MPC7450:
|
|
case MPC7455:
|
|
case MPC7457:
|
|
__asm __volatile("\
|
|
dssall; sync; mtmsr %0; isync"
|
|
:: "r"(msr | PSL_POW));
|
|
break;
|
|
default:
|
|
powerpc_sync();
|
|
mtmsr(msr | PSL_POW);
|
|
isync();
|
|
break;
|
|
}
|
|
#endif
|
|
}
|
|
|
|
static void
|
|
cpu_idle_booke(sbintime_t sbt)
|
|
{
|
|
|
|
#ifdef BOOKE_E500
|
|
platform_cpu_idle(PCPU_GET(cpuid));
|
|
#endif
|
|
}
|
|
|