a27e66e8f5
o) Mask off PAGE_MASK bits in pmap_update_page, etc., rather than modifying the badvaddr in trapframe. Some nearby interfaces already did this. o) Make PTEs "unsigned int" for now, not "unsigned long" -- we are only ready for them to be 32-bit on 64-bit platforms. o) Rather than using pmap_segmap and calculating the offset into the page table by hand in trap.c, use pmap_pte(). o) Remove unused quad_syscall variable in trap.c. o) Log things for illegal instructions like we do for bad page faults. o) Various cast cleanups related to how to print registers. o) When logging page faults, show the page table information not just for the program counter, but for the fault address. o) Modify support.S to use ABI-neutral macros for operating on pointers. o) Consistently use CALLFRAME_SIZ rather than STAND_FRAME_SIZE, etc. o) Remove unused insque/remque functions. o) Remove some coprocessor 0 accessor functions implemented in assembly that are unused and have inline assembly counterparts.
154 lines
5.3 KiB
C
154 lines
5.3 KiB
C
/* $OpenBSD: pte.h,v 1.4 1998/01/28 13:46:25 pefo Exp $ */
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/*-
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* Copyright (c) 1988 University of Utah.
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* the Systems Programming Group of the University of Utah Computer
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* Science Department and Ralph Campbell.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: Utah Hdr: pte.h 1.11 89/09/03
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* from: @(#)pte.h 8.1 (Berkeley) 6/10/93
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* JNPR: pte.h,v 1.1.4.1 2007/09/10 06:20:19 girish
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* $FreeBSD$
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*/
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#ifndef _MACHINE_PTE_H_
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#define _MACHINE_PTE_H_
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#include <machine/endian.h>
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/*
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* MIPS hardware page table entry
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*/
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#ifndef _LOCORE
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struct pte {
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#if BYTE_ORDER == BIG_ENDIAN
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unsigned int pg_prot:2, /* SW: access control */
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pg_pfnum:24, /* HW: core page frame number or 0 */
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pg_attr:3, /* HW: cache attribute */
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pg_m:1, /* HW: modified (dirty) bit */
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pg_v:1, /* HW: valid bit */
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pg_g:1; /* HW: ignore pid bit */
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#endif
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#if BYTE_ORDER == LITTLE_ENDIAN
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unsigned int pg_g:1, /* HW: ignore pid bit */
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pg_v:1, /* HW: valid bit */
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pg_m:1, /* HW: modified (dirty) bit */
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pg_attr:3, /* HW: cache attribute */
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pg_pfnum:24, /* HW: core page frame number or 0 */
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pg_prot:2; /* SW: access control */
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#endif
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};
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/*
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* Structure defining an tlb entry data set.
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*/
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struct tlb {
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int tlb_mask;
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int tlb_hi;
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int tlb_lo0;
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int tlb_lo1;
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};
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typedef unsigned int pt_entry_t;
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typedef pt_entry_t *pd_entry_t;
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#define PDESIZE sizeof(pd_entry_t) /* for assembly files */
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#define PTESIZE sizeof(pt_entry_t) /* for assembly files */
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#endif /* _LOCORE */
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#define PT_ENTRY_NULL ((pt_entry_t *) 0)
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#define PTE_WIRED 0x80000000 /* SW */
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#define PTE_W PTE_WIRED
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#define PTE_RO 0x40000000 /* SW */
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#define PTE_G 0x00000001 /* HW */
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#define PTE_V 0x00000002
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/*#define PTE_NV 0x00000000 Not Used */
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#define PTE_M 0x00000004
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#define PTE_RW PTE_M
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#define PTE_ODDPG 0x00001000
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/*#define PG_ATTR 0x0000003f Not Used */
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#define PTE_UNCACHED 0x00000010
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#ifdef CPU_SB1
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#define PTE_CACHE 0x00000028 /* cacheable coherent */
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#else
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#define PTE_CACHE 0x00000018
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#endif
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/*#define PG_CACHEMODE 0x00000038 Not Used*/
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#define PTE_ROPAGE (PTE_V | PTE_RO | PTE_CACHE) /* Write protected */
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#define PTE_RWPAGE (PTE_V | PTE_M | PTE_CACHE) /* Not wr-prot not clean */
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#define PTE_CWPAGE (PTE_V | PTE_CACHE) /* Not wr-prot but clean */
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#define PTE_IOPAGE (PTE_G | PTE_V | PTE_M | PTE_UNCACHED)
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#define PTE_FRAME 0x3fffffc0
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#define PTE_HVPN 0xffffe000 /* Hardware page no mask */
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#define PTE_ASID 0x000000ff /* Address space ID */
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#define PTE_SHIFT 6
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#define pfn_is_ext(x) ((x) & 0x3c000000)
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#define vad_to_pfn(x) (((unsigned)(x) >> PTE_SHIFT) & PTE_FRAME)
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#define vad_to_pfn64(x) ((quad_t)(x) >> PTE_SHIFT) & PTE_FRAME)
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#define pfn_to_vad(x) (((x) & PTE_FRAME) << PTE_SHIFT)
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/* User virtual to pte offset in page table */
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#define vad_to_pte_offset(adr) (((adr) >> PAGE_SHIFT) & (NPTEPG -1))
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#define mips_pg_v(entry) ((entry) & PTE_V)
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#define mips_pg_wired(entry) ((entry) & PTE_WIRED)
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#define mips_pg_m_bit() (PTE_M)
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#define mips_pg_rw_bit() (PTE_M)
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#define mips_pg_ro_bit() (PTE_RO)
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#define mips_pg_ropage_bit() (PTE_ROPAGE)
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#define mips_pg_rwpage_bit() (PTE_RWPAGE)
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#define mips_pg_cwpage_bit() (PTE_CWPAGE)
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#define mips_pg_global_bit() (PTE_G)
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#define mips_pg_wired_bit() (PTE_WIRED)
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#define mips_tlbpfn_to_paddr(x) pfn_to_vad((x))
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#define mips_paddr_to_tlbpfn(x) vad_to_pfn((x))
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/* These are not used */
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#define PTE_SIZE_4K 0x00000000
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#define PTE_SIZE_16K 0x00006000
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#define PTE_SIZE_64K 0x0001e000
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#define PTE_SIZE_256K 0x0007e000
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#define PTE_SIZE_1M 0x001fe000
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#define PTE_SIZE_4M 0x007fe000
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#define PTE_SIZE_16M 0x01ffe000
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#endif /* !_MACHINE_PTE_H_ */
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