2019-03-05 23:59:55 +00:00
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/*-
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* Copyright (c) 2015 John H. Baldwin <jhb@FreeBSD.org>
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2019-03-06 16:50:14 +00:00
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* Copyright (c) 2019 Mitchell Horne
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2019-03-05 23:59:55 +00:00
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef __KVM_RISCV_H__
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#define __KVM_RISCV_H__
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#ifdef __riscv
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#include <machine/pte.h>
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#endif
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typedef uint64_t riscv_physaddr_t;
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typedef uint64_t riscv_pt_entry_t;
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#define RISCV_PAGE_SHIFT 12
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#define RISCV_PAGE_SIZE (1 << RISCV_PAGE_SHIFT)
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#define RISCV_PAGE_MASK (RISCV_PAGE_SIZE - 1)
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/* Source: sys/riscv/include/pte.h */
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#define RISCV_L3_SHIFT 12
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#define RISCV_L3_SIZE (1 << L3_SHIFT)
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#define RISCV_L3_OFFSET (L3_SIZE - 1)
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#define RISCV_PTE_SW_MANAGED (1 << 9)
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#define RISCV_PTE_SW_WIRED (1 << 8)
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#define RISCV_PTE_D (1 << 7) /* Dirty */
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#define RISCV_PTE_A (1 << 6) /* Accessed */
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#define RISCV_PTE_G (1 << 5) /* Global */
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#define RISCV_PTE_U (1 << 4) /* User */
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#define RISCV_PTE_X (1 << 3) /* Execute */
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#define RISCV_PTE_W (1 << 2) /* Write */
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#define RISCV_PTE_R (1 << 1) /* Read */
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#define RISCV_PTE_V (1 << 0) /* Valid */
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#define RISCV_PTE_RWX (RISCV_PTE_R | RISCV_PTE_W | RISCV_PTE_X)
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#define RISCV_PTE_PPN0_S 10
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#ifdef __riscv
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_Static_assert(sizeof(pt_entry_t) == sizeof(riscv_pt_entry_t),
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"pt_entry_t size mismatch");
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_Static_assert(PAGE_SHIFT == RISCV_PAGE_SHIFT, "PAGE_SHIFT mismatch");
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_Static_assert(PAGE_SIZE == RISCV_PAGE_SIZE, "PAGE_SIZE mismatch");
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_Static_assert(PAGE_MASK == RISCV_PAGE_MASK, "PAGE_MASK mismatch");
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_Static_assert(L3_SHIFT == RISCV_L3_SHIFT, "L3_SHIFT mismatch");
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_Static_assert(L3_SIZE == RISCV_L3_SIZE, "L3_SIZE mismatch");
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_Static_assert(L3_OFFSET == RISCV_L3_OFFSET, "L3_OFFSET mismatch");
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_Static_assert(PTE_PPN0_S == RISCV_PTE_PPN0_S, "PTE_PPN0_S mismatch");
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_Static_assert(PTE_SW_MANAGED == RISCV_PTE_SW_MANAGED,
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"PTE_SW_MANAGED mismatch");
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_Static_assert(PTE_SW_WIRED == RISCV_PTE_SW_WIRED, "PTE_SW_WIRED mismatch");
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_Static_assert(PTE_D == RISCV_PTE_D, "PTE_D mismatch");
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_Static_assert(PTE_A == RISCV_PTE_A, "PTE_A mismatch");
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_Static_assert(PTE_G == RISCV_PTE_G, "PTE_G mismatch");
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_Static_assert(PTE_U == RISCV_PTE_U, "PTE_U mismatch");
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_Static_assert(PTE_X == RISCV_PTE_X, "PTE_X mismatch");
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_Static_assert(PTE_W == RISCV_PTE_W, "PTE_W mismatch");
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_Static_assert(PTE_R == RISCV_PTE_R, "PTE_R mismatch");
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_Static_assert(PTE_V == RISCV_PTE_V, "PTE_V mismatch");
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_Static_assert(PTE_RWX == RISCV_PTE_RWX, "PTE_RWX mismatch");
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#endif
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#endif /* !__KVM_RISCV_H__ */
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