145 lines
4.1 KiB
C
145 lines
4.1 KiB
C
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/* $FreeBSD$ */
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/* $NecBSD: tmc18c30reg.h,v 1.4 1998/03/14 07:05:23 kmatsuda Exp $ */
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/* $NetBSD$ */
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/*
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* [NetBSD for NEC PC-98 series]
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* Copyright (c) 1996, 1997, 1998
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* NetBSD/pc98 porting staff. All rights reserved.
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* Copyright (c) 1996, 1997, 1998
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* Kouichi Matsuda. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _TMC18C30REG_H_
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#define _TMC18C30REG_H_
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#define tmc_wdata 0x00
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#define tmc_rdata 0x00
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#define tmc_bctl 0x01
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#define BCTL_BUSFREE 0x00
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#define BCTL_RST 0x01
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#define BCTL_SEL 0x02
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#define BCTL_BSY 0x04
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#define BCTL_ATN 0x08
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#define BCTL_IO 0x10
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#define BCTL_CD 0x20
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#define BCTL_MSG 0x40
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#define BCTL_BUSEN 0x80
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#define tmc_bstat 0x01
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#define BSTAT_BSY 0x01
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#define BSTAT_MSG 0x02
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#define BSTAT_IO 0x04
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#define BSTAT_CMD 0x08
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#define BSTAT_REQ 0x10
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#define BSTAT_SEL 0x20
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#define BSTAT_ACK 0x40
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#define BSTAT_PHMASK (BSTAT_MSG | BSTAT_IO | BSTAT_CMD)
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#define tmc_ictl 0x02
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#define ICTL_FIFO 0x10
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#define ICTL_ARBIT 0x20
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#define ICTL_SEL 0x40
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#define ICTL_CD 0x80
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#define ICTL_ALLINT (ICTL_ARBIT | ICTL_CD | ICTL_SEL)
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#define tmc_astat 0x02
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#define ASTAT_INT 0x01
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#define ASTAT_ARBIT 0x02
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#define ASTAT_PARERR 0x04
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#define ASTAT_SCSIRST 0x08
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#define ASTAT_STATMASK 0x0f
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#define ASTAT_FIFODIR 0x10
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#define ASTAT_FIFOEN 0x20
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#define ASTAT_PARENB 0x40
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#define ASTAT_BUSEN 0x80
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#define tmc_ssctl 0x03
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#define SSCTL_FSYNCHEN 0x40
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#define SSCTL_SYNCHEN 0x80
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#define tmc_fstat 0x03
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#define tmc_fctl 0x04
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#define FCTL_CLRFIFO 0x01
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#define FCTL_ARBIT 0x04
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#define FCTL_PARENB 0x08
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#define FCTL_INTEN 0x10
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#define FCTL_CLRINT 0x20
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#define FCTL_FIFOW 0x40
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#define FCTL_FIFOEN 0x80
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#define tmc_icnd 0x04
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#define tmc_mctl 0x05
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#define tmc_idlsb 0x05
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#define tmc_idmsb 0x06
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#define tmc_wlb 0x07
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#define tmc_rlb 0x07
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#define tmc_scsiid 0x08
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#define tmc_sdna 0x08
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#define tmc_istat 0x09
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#define ISTAT_INTEN 0x08
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#define ISTAT_FIFO 0x10
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#define ISTAT_ARBIT 0x20
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#define ISTAT_SEL 0x40
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#define ISTAT_CD 0x80
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#define tmc_cfg1 0x0a
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#define tmc_ioctl 0x0b
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#define tmc_cfg2 0x0b
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#define tmc_wfifo 0x0c
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#define tmc_rfifo 0x0c
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#define tmc_fdcnt 0x0e
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/* Information transfer phases */
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#define BUSFREE_PHASE 0x00
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#define DATA_OUT_PHASE (BSTAT_BSY)
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#define DATA_IN_PHASE (BSTAT_BSY|BSTAT_IO)
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#define COMMAND_PHASE (BSTAT_CMD|BSTAT_BSY)
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#define STATUS_PHASE (BSTAT_CMD|BSTAT_BSY|BSTAT_IO)
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#define MESSAGE_OUT_PHASE (BSTAT_CMD|BSTAT_MSG|BSTAT_BSY)
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#define MESSAGE_IN_PHASE (BSTAT_CMD|BSTAT_MSG|BSTAT_BSY|BSTAT_IO)
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#define PHASE_RESELECTED (BSTAT_SEL|BSTAT_IO)
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#define PHASE_MASK 0x2f
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#define RESEL_PHASE_MASK 0x2e
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/* chip type */
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#define TMCCHIP_UNK 0x00
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#define TMCCHIP_1800 0x01
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#define TMCCHIP_18C50 0x02
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#define TMCCHIP_18C30 0x03
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#define STGIOSZ 0x10
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#endif /* !_TMC18C30REG_H_ */
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