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freebsd-skq/share/man/man4/est.4

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Document support for Intel Enhanced Speedstep Tech interface of cpufreq(4) via a new man page est(4) Document the two exposed tuneables of est(4). I'd appreciate more reviews of content if possible. I gleaned the information contained herein from sys/x86/cpufreq/est.c and the Intel reference documentation Reviewed by: wblock hrs gjb MFC after: 2 weeks
2012-06-18 23:18:49 +00:00
.\"
.\" Copyright (c) 2012 Sean Bruno <sbruno@freebsd.org>
.\" All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
.\" modification, are permitted provided that the following conditions
.\" are met:
.\" 1. Redistributions of source code must retain the above copyright
.\" notice, this list of conditions and the following disclaimer.
.\" 2. Redistributions in binary form must reproduce the above copyright
.\" notice, this list of conditions and the following disclaimer in the
.\" documentation and/or other materials provided with the distribution.
.\"
.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
.\" $FreeBSD$
.\"
Also update est(4) as r360162 and r360164 MFC after: 3 days
2020-04-21 17:17:32 +00:00
.Dd April 21, 2020
Document support for Intel Enhanced Speedstep Tech interface of cpufreq(4) via a new man page est(4) Document the two exposed tuneables of est(4). I'd appreciate more reviews of content if possible. I gleaned the information contained herein from sys/x86/cpufreq/est.c and the Intel reference documentation Reviewed by: wblock hrs gjb MFC after: 2 weeks
2012-06-18 23:18:49 +00:00
.Dt EST 4
.Os
.Sh NAME
.Nm est
.Nd Enhanced Speedstep Technology
.Sh SYNOPSIS
To compile this capability into your kernel
place the following line in your kernel
configuration file:
.Bd -ragged -offset indent
.Cd "device cpufreq"
.Ed
.Sh DESCRIPTION
The
.Nm
interface provides support for the Intel Enhanced Speedstep Technology.
.Pp
Note that
.Nm
capabilities are automatically loaded by the
.Xr cpufreq 4
driver.
.Sh LOADER TUNABLES
The
.Nm
interface is intended to allow
.Xr cpufreq 4
to access and implement Intel Enhanced SpeedStep Technology via
.Xr acpi 4
and the acpi_perf interface accessors.
If the default settings are not optimal, the following sysctls can be
used to modify or monitor
.Nm
behavior.
.Bl -tag -width indent
.It hw.est.msr_info
Attempt to infer information from direct probing of the msr.
est(4) man page update to document the exposed sysctl r/o variables available to the user. Should be applicable to all branches and versions where est(4) exists. thanks to gjb for reviewing and suggesting nits Reviewed by: gjb@ MFC after: 2 weeks
2012-10-18 22:22:01 +00:00
Should only be used in diagnostic cases.
Document support for Intel Enhanced Speedstep Tech interface of cpufreq(4) via a new man page est(4) Document the two exposed tuneables of est(4). I'd appreciate more reviews of content if possible. I gleaned the information contained herein from sys/x86/cpufreq/est.c and the Intel reference documentation Reviewed by: wblock hrs gjb MFC after: 2 weeks
2012-06-18 23:18:49 +00:00
.Pq default 0
.It hw.est.strict
Also update est(4) as r360162 and r360164 MFC after: 3 days
2020-04-21 17:17:32 +00:00
Validate frequency requested is accepted by the CPU when set.
Correct misunderstanding of hw.est.strict Setting strict causes a validation of the requested value vs the value currently running after a frequency change is requested. Change applicability to be single core not i386. Thanks to mav@ for reviewing and commenting on my lack of understanding. MFC after: 2 weeks
2012-06-19 17:13:14 +00:00
It appears that this will only work on single core cpus.
Document support for Intel Enhanced Speedstep Tech interface of cpufreq(4) via a new man page est(4) Document the two exposed tuneables of est(4). I'd appreciate more reviews of content if possible. I gleaned the information contained herein from sys/x86/cpufreq/est.c and the Intel reference documentation Reviewed by: wblock hrs gjb MFC after: 2 weeks
2012-06-18 23:18:49 +00:00
.Pq default 0
.El
est(4) man page update to document the exposed sysctl r/o variables available to the user. Should be applicable to all branches and versions where est(4) exists. thanks to gjb for reviewing and suggesting nits Reviewed by: gjb@ MFC after: 2 weeks
2012-10-18 22:22:01 +00:00
.Sh SYSCTL VARIABLES
The following
.Xr sysctl 8
values are available
.Bl -tag -width indent
Also update est(4) as r360162 and r360164 MFC after: 3 days
2020-04-21 17:17:32 +00:00
.It Va dev.est.%d.%desc
est(4) man page update to document the exposed sysctl r/o variables available to the user. Should be applicable to all branches and versions where est(4) exists. thanks to gjb for reviewing and suggesting nits Reviewed by: gjb@ MFC after: 2 weeks
2012-10-18 22:22:01 +00:00
Description of support, almost always Enhanced SpeedStep Frequency Control.
.It dev.est.0.%desc: Enhanced SpeedStep Frequency Control
Also update est(4) as r360162 and r360164 MFC after: 3 days
2020-04-21 17:17:32 +00:00
.It Va dev.est.%d.%driver
est(4) man page update to document the exposed sysctl r/o variables available to the user. Should be applicable to all branches and versions where est(4) exists. thanks to gjb for reviewing and suggesting nits Reviewed by: gjb@ MFC after: 2 weeks
2012-10-18 22:22:01 +00:00
Driver in use, always est.
.It dev.est.0.%driver: est
Also update est(4) as r360162 and r360164 MFC after: 3 days
2020-04-21 17:17:32 +00:00
.It Va dev.est.%d.%parent
The CPU that is exposing these frequencies.
est(4) man page update to document the exposed sysctl r/o variables available to the user. Should be applicable to all branches and versions where est(4) exists. thanks to gjb for reviewing and suggesting nits Reviewed by: gjb@ MFC after: 2 weeks
2012-10-18 22:22:01 +00:00
For example
.Va cpu0 .
Also update est(4) as r360162 and r360164 MFC after: 3 days
2020-04-21 17:17:32 +00:00
.It dev.est.0.%parent: cpu0
est(4) man page update to document the exposed sysctl r/o variables available to the user. Should be applicable to all branches and versions where est(4) exists. thanks to gjb for reviewing and suggesting nits Reviewed by: gjb@ MFC after: 2 weeks
2012-10-18 22:22:01 +00:00
.It Va dev.est.%d.freq_settings .
The valid frequencies that are allowed by this CPU and their step values.
Fix minor whitespace issues.
2012-10-19 10:38:32 +00:00
.It dev.est.0.freq_settings: 2201/45000 2200/45000 2000/39581 1900/37387
1800/34806 1700/32703 1600/30227 1500/28212 1400/25828 1300/23900 1200/21613
est(4) man page update to document the exposed sysctl r/o variables available to the user. Should be applicable to all branches and versions where est(4) exists. thanks to gjb for reviewing and suggesting nits Reviewed by: gjb@ MFC after: 2 weeks
2012-10-18 22:22:01 +00:00
1100/19775 1000/17582 900/15437 800/13723
.El
Document support for Intel Enhanced Speedstep Tech interface of cpufreq(4) via a new man page est(4) Document the two exposed tuneables of est(4). I'd appreciate more reviews of content if possible. I gleaned the information contained herein from sys/x86/cpufreq/est.c and the Intel reference documentation Reviewed by: wblock hrs gjb MFC after: 2 weeks
2012-06-18 23:18:49 +00:00
.Sh DIAGNOSTICS
.Bl -diag
.It "est%d: <Enhanced SpeedStep Frequency Control> on cpu%d"
.Pp
Indicates normal startup of this interface.
.It "est: CPU supports Enhanced Speedstep, but is not recognized."
.It "est: cpu_vendor GenuineIntel, msr 471c471c0600471c"
.It "device_attach: est%d attach returned 6"
.Pp
Indicates all attempts to attach to this interface have failed.
This usually indicates an improper BIOS setting restricting O/S
control of the CPU speeds.
Consult your BIOS documentation for more details.
.El
.Sh COMPATIBILITY
.Nm
is only found on supported Intel CPUs.
.Sh SEE ALSO
.Xr cpufreq 4
Minor mdoc fixes.
2012-06-19 05:53:47 +00:00
.Rs
.%T "Intel 64 and IA-32 Architectures Software Developer Manuals"
.%U "http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html"
.Re
Document support for Intel Enhanced Speedstep Tech interface of cpufreq(4) via a new man page est(4) Document the two exposed tuneables of est(4). I'd appreciate more reviews of content if possible. I gleaned the information contained herein from sys/x86/cpufreq/est.c and the Intel reference documentation Reviewed by: wblock hrs gjb MFC after: 2 weeks
2012-06-18 23:18:49 +00:00
.Sh AUTHORS
This manual page was written by
use .Mt to mark up email addresses consistently (final part) PR: 191174 Submitted by: Franco Fichtner <franco at lastsummer.de>
2014-06-26 21:46:14 +00:00
.An Sean Bruno Aq Mt sbruno@FreeBSD.org .
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