2005-01-06 01:43:34 +00:00
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/*-
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2003-04-13 06:27:13 +00:00
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* Granch SBNI16 G.SHDSL Modem driver definitions
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* Written by Denis I. Timofeev, 2002-2003.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/* SBNI16 controller chip definitions */
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/* CR bits */
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#define TXEN 0x01 /* transmitter enable */
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#define RXEN 0x02 /* receiver enable */
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#define NCRC 0x04 /* ignore received CRC */
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#define DLBK 0x08 /* digital loopback */
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#define CMOD 0x10 /* 0 - use CRC-32, 1 - CRC-16 */
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#define FMOD 0x20 /* interframe fill: 0 - all ones, 1 - 0xfe */
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#define PMOD 0x40 /* data polarity: 0 - normal, 1 - invert */
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#define XRST 0x80 /* reset the transceiver */
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/* CRB bits */
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#define RDBE 0x01 /* read burst enable */
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#define WTBE 0x02 /* write burst enable */
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#define RODD 0x04 /* receive 2-byte alignment */
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#define RXDE 0x08 /* receive data enable */
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/* SR and IMR bits */
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#define TXS 0x01 /* transmit success */
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#define RXS 0x02 /* receive success */
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/* SR only */
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#define CRC 0x04 /* CRC error */
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#define OFL 0x08 /* fifo overflow error */
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#define UFL 0x10 /* fifo underflow error */
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#define EXT 0x20 /* interrupt from sk70725 */
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/* IMR only */
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#define TSI 0x80 /* generate test interrupt */
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#define LAST_FRAG 0x00008000
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#define SBNI16_MAX_FRAME (1536 + 16)
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/* We don't have official vendor id yet... */
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#define SBNI16_VENDOR 0x55
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#define SBNI16_DEVICE 0x9d
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#define SBNI16_SUBDEV 3
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/* transceiver chip set definitions */
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enum CX28975_API_commands {
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_DSL_RESET_SYSTEM = 0x00,
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_DSL_SYSTEM_ENABLE = 0x01,
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_DSL_AFE_CONFIG = 0x02,
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_DSL_TRAINING_MODE = 0x03,
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_DSL_CLOCK_CONFIG = 0x04,
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_DSL_PCM_MF_LEN = 0x05,
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_DSL_SYSTEM_CONFIG = 0x06,
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_DSL_LOOPBACK = 0x09,
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_DSL_ACTIVATION = 0x0b,
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_DSL_FORCE_DEACTIVATE = 0x0c,
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_DSL_TEST_MODE = 0x0d,
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_DSL_DATA_RATE = 0x0e,
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_DSL_PREACTIVATION_CFG = 0x0f,
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_DSL_FR_PCM_CONFIG = 0x10,
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_DSL_FR_HDSL_CONFIG = 0x11,
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_DSL_PCM_CLK_CONF = 0x12,
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_AFE_TX_GAIN = 0x13,
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_DSL_PREACT_USER_INFO = 0x14,
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_DSL_PREACT_RATE_LIST = 0x15,
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_DSL_TX_ISO_PULSE = 0x16,
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_BP_ERLE_TEST_MODE = 0x18,
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_DSL_MULTI_PAIR_CONFIG = 0x19,
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_DSL_NB_MULTI_RATE_CONFIG = 0x1a,
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_DSL_MULTI_RATE_CONFIG = 0x1b,
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_ATM_PHY_MODE = 0x1c,
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_ATM_PHY_UTOPIA_CONFIG = 0x1d,
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_ATM_PHY_IF_MODE = 0x1e,
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_ATM_PHY_INJECT_HEC_ERROR = 0x1f,
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_ATM_PHY_CONFIG = 0x20,
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_DSL_TNB_BER_STATE = 0x21,
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_DSL_RNB_BER_STATE = 0x22,
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_DSL_TP_BER_STATE = 0x23,
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_DSL_RP_BER_STATE = 0x24,
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_DSL_PRBS_CONFIGURE = 0x25,
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_DSL_CONST_FILL = 0x26,
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_DSL_DBANK = 0x27,
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_DSL_NB_CONFIG = 0x28,
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_DSL_TNB_FRM_OFST = 0x29,
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_DSL_RNB_FRM_OFST = 0x2a,
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_DSL_TP_FRM_OFST = 0x2e,
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_DSL_RP_FRM_OFST = 0x2f,
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_DSL_TP_MAPPER_VALUE = 0x30,
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_DSL_TP_MAPPER_WRITE = 0x31,
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_DSL_RP_MAPPER_VALUE = 0x32,
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_DSL_RP_MAPPER_WRITE = 0x33,
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_DSL_TH_MAPPER_VALUE = 0x34,
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_DSL_TH_MAPPER_WRITE = 0x35,
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_DSL_RH_MAPPER_VALUE = 0x36,
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_DSL_RH_MAPPER_WRITE = 0x37,
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_DSL_TNB_MAPPER_VALUE = 0x38,
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_DSL_TNB_MAPPER_WRITE = 0x39,
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_DSL_RNB_MAPPER_VALUE = 0x3a,
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_DSL_RNB_MAPPER_WRITE = 0x3b,
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_DSL_CLEAR_ERROR_CTRS = 0x40,
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_DSL_INJECT_CRC_ERROR = 0x41,
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_DSL_THRESHOLDS = 0x43,
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_DSL_FR_SET_STATE_MACHINE = 0x4a,
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_DSL_FR_TNB_RESET = 0x4b,
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_DSL_FR_RNB_RESET = 0x4c,
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_EOC_RESET = 0x4d,
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_DSL_FR_TX_RESET = 0x4e,
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_DSL_FR_RX_RESET = 0x4f,
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_DSL_INTR_HOST_MASK = 0x50,
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_DSL_INTR_API_SUBMASK = 0x51,
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_DSL_DOWNLOAD_START = 0x53,
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_DSL_DOWNLOAD_DATA = 0x54,
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_DSL_DOWNLOAD_END = 0x55,
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_DSL_DPLL_CLOCK_GEN = 0x58,
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_DSL_NB_DPLL_CLOCK_GEN = 0x59,
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_DSL_WRITE_REG = 0x75,
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_DSL_WRITE_AFE = 0x76
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};
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enum CX28975_status_commands {
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_DSL_READ_CONTROL = 0x80,
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_DSL_FAR_END_ATTEN = 0x82,
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_DSL_NOISE_MARGIN = 0x83,
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_DSL_STATUS = 0x85,
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_DSL_PREACT_GET_FE_CAPS = 0x88,
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_DSL_PREACT_GET_OPT_DATA_RATE = 0x89,
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_DSL_VERSIONS = 0x8a,
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_DSL_TP_BER_RESULTS = 0x8c,
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_DSL_RP_BER_RESULTS = 0x8d,
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_DSL_STAGE_NUMBER = 0x8f,
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_DSL_AFE_SETTING = 0x90,
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_DSL_TNB_BER_RESULTS = 0x91,
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_DSL_RNB_BER_RESULTS = 0x92,
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_BP_ERLE_RESULTS = 0x93,
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_DSL_POWER_BACK_OFF_RESULT = 0x94,
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_DSL_OPER_ERR_CTRS = 0x9c,
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_DSL_TIME = 0x9d,
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_DSL_HDSL_PERF_ERR_CTRS = 0x9e,
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_DSL_READ_REG = 0xa0,
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_DSL_READ_AFE = 0xa1,
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_DSL_SYSTEM_PERF_ERR_CTRS = 0xa2,
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_DSL_TP_MAPPER_READ = 0xa3,
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_DSL_RP_MAPPER_READ = 0xa4,
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_DSL_TH_MAPPER_READ = 0xa5,
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_DSL_RH_MAPPER_READ = 0xa6,
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_DSL_TNB_MAPPER_READ = 0xa7,
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_DSL_RNB_MAPPER_READ = 0xa8,
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_EOC_RX_GET_STATS = 0xae,
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_EOC_TX_SEND_COMMAND = 0xb0,
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_EOC_RX_GET_MSG = 0xb1,
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_EOC_TX_GET_MSG_STATUS = 0xb2,
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_EOC_TX_DELETE_MSG = 0xb3,
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_ATM_PHY_OPER_ERR_CTRS = 0xb8,
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_ATM_PHY_PERF_ERR_CTRS = 0xb9,
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_ATM_PHY_CELL_CTRS = 0xba
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};
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enum CX28975_acknoledge_status_codes {
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_ACK_NOT_COMPLETE = 0x00,
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_ACK_PASS = 0x01,
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_ACK_BUSY = 0x02,
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_ACK_NOT_APPLICABLE = 0x03,
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_ACK_INVALID_DEST = 0x04,
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_ACK_INVALID_OPCODE = 0x05,
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_ACK_INVALID_LENGTH = 0x06,
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_ACK_INVALID_DATA = 0x07,
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_ACK_INVALID_CHKSUM = 0x08,
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_ACK_NO_RESULT = 0x09,
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_ACK_NOT_AVAILABLE = 0x0a,
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_ACK_BOOT_WAKE_UP = 0x0d,
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_ACK_OPER_WAKE_UP = 0x0e
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};
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