1998-06-11 07:15:55 +00:00
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/* $Id$ */
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1998-06-10 10:57:29 +00:00
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/* $NetBSD: dwlpxreg.h,v 1.9 1998/03/21 22:02:42 mjacob Exp $ */
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/*
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* Copyright (c) 1997 by Matthew Jacob
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* NASA AMES Research Center.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice immediately at the beginning of the file, without modification,
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* this list of conditions, and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Taken from combinations of:
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*
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* ``DWLPA and DWLPB PCI Adapter Technical Manual,
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* Order Number: EK-DWLPX-TM.A01''
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*
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* and
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*
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* ``AlphaServer 8200/8400 System Technical Manual,
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* Order Number EK-T8030-TM. A01''
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*/
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#define REGVAL(r) (*(volatile int32_t *)ALPHA_PHYS_TO_K0SEG(r))
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/*
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* There are (potentially) 4 I/O hoses, and there are three
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* (electrically distinct) PCI busses per DWLPX (which appear
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* as one logical PCI bus).
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*
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* A CPU to PCI Address Mapping looks (roughly) like this:
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*
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* 39 38........36 35.34 33.....32 31....................5 4.........3 2...0
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* --------------------------------------------------------------------------
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* |1| I/O NodeID |Hose#|PCI Space|Byte Aligned I/O <26:0>|Byte Length|0 0 0|
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* --------------------------------------------------------------------------
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*
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* I/O Node is the TLSB Node ID minus 4. Don't ask.
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*/
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#define NHPC 3
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/*
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* Address Space Cookies
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*
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* (lacking I/O Node ID and Hose Numbers)
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*/
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#define DWLPX_PCI_DENSE 0x000000000LL
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#define DWLPX_PCI_SPARSE 0x100000000LL
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#define DWLPX_PCI_IOSPACE 0x200000000LL
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#define DWLPX_PCI_CONF 0x300000000LL
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/*
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* PCIA Interface Adapter Register Addresses (Offsets from Node Address)
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*
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*
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* Addresses are for Hose #0, PCI bus #0. Macros below will offset
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* per bus. I/O Hose and TLSB Node I/D offsets must be added separately.
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*/
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#define _PCIA_CTL 0x380000000LL /* PCI 0 Bus Control */
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#define _PCIA_MRETRY 0x380000080LL /* PCI 0 Master Retry Limit */
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#define _PCIA_GPR 0x380000100LL /* PCI 0 General Purpose */
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#define _PCIA_ERR 0x380000180LL /* PCI 0 Error Summary */
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#define _PCIA_FADR 0x380000200LL /* PCI 0 Failing Address */
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#define _PCIA_IMASK 0x380000280LL /* PCI 0 Interrupt Mask */
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#define _PCIA_DIAG 0x380000300LL /* PCI 0 Diagnostic */
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#define _PCIA_IPEND 0x380000380LL /* PCI 0 Interrupt Pending */
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#define _PCIA_IPROG 0x380000400LL /* PCI 0 Interrupt in Progress */
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#define _PCIA_WMASK_A 0x380000480LL /* PCI 0 Window Mask A */
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#define _PCIA_WBASE_A 0x380000500LL /* PCI 0 Window Base A */
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#define _PCIA_TBASE_A 0x380000580LL /* PCI 0 Window Translated Base A */
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#define _PCIA_WMASK_B 0x380000600LL /* PCI 0 Window Mask B */
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#define _PCIA_WBASE_B 0x380000680LL /* PCI 0 Window Base B */
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#define _PCIA_TBASE_B 0x380000700LL /* PCI 0 Window Translated Base B */
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#define _PCIA_WMASK_C 0x380000780LL /* PCI 0 Window Mask C */
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#define _PCIA_WBASE_C 0x380000800LL /* PCI 0 Window Base C */
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#define _PCIA_TBASE_C 0x380000880LL /* PCI 0 Window Translated Base C */
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#define _PCIA_ERRVEC 0x380000900LL /* PCI 0 Error Interrupt Vector */
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#define _PCIA_DEVVEC 0x380001000LL /* PCI 0 Device Interrupt Vector */
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#define PCIA_CTL(hpc) (_PCIA_CTL + (0x200000 * (hpc)))
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#define PCIA_MRETRY(hpc) (_PCIA_MRETRY + (0x200000 * (hpc)))
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#define PCIA_GPR(hpc) (_PCIA_GPR + (0x200000 * (hpc)))
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#define PCIA_ERR(hpc) (_PCIA_ERR + (0x200000 * (hpc)))
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#define PCIA_FADR(hpc) (_PCIA_FADR + (0x200000 * (hpc)))
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#define PCIA_IMASK(hpc) (_PCIA_IMASK + (0x200000 * (hpc)))
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#define PCIA_DIAG(hpc) (_PCIA_DIAG + (0x200000 * (hpc)))
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#define PCIA_IPEND(hpc) (_PCIA_IPEND + (0x200000 * (hpc)))
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#define PCIA_IPROG(hpc) (_PCIA_IPROG + (0x200000 * (hpc)))
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#define PCIA_WMASK_A(hpc) (_PCIA_WMASK_A + (0x200000 * (hpc)))
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#define PCIA_WBASE_A(hpc) (_PCIA_WBASE_A + (0x200000 * (hpc)))
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#define PCIA_TBASE_A(hpc) (_PCIA_TBASE_A + (0x200000 * (hpc)))
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#define PCIA_WMASK_B(hpc) (_PCIA_WMASK_B + (0x200000 * (hpc)))
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#define PCIA_WBASE_B(hpc) (_PCIA_WBASE_B + (0x200000 * (hpc)))
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#define PCIA_TBASE_B(hpc) (_PCIA_TBASE_B + (0x200000 * (hpc)))
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#define PCIA_WMASK_C(hpc) (_PCIA_WMASK_C + (0x200000 * (hpc)))
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#define PCIA_WBASE_C(hpc) (_PCIA_WBASE_C + (0x200000 * (hpc)))
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#define PCIA_TBASE_C(hpc) (_PCIA_TBASE_C + (0x200000 * (hpc)))
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#define PCIA_ERRVEC(hpc) (_PCIA_ERRVEC + (0x200000 * (hpc)))
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#define PCIA_DEVVEC(hpc, subslot, ipin) \
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(_PCIA_DEVVEC + (0x200000 * (hpc)) + ((subslot) * 0x200) + ((ipin-1) * 0x80))
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#define PCIA_SCYCLE 0x380002000LL /* PCI Special Cycle */
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#define PCIA_IACK 0x380002080LL /* PCI Interrupt Acknowledge */
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#define PCIA_PRESENT 0x380800000LL /* PCI Slot Present */
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#define PCIA_TBIT 0x380A00000LL /* PCI TBIT */
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#define PCIA_MCTL 0x380C00000LL /* PCI Module Control */
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#define PCIA_IBR 0x380E00000LL /* PCI Information Base Repair */
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/*
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* Bits in PCIA_CTL register
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*/
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#define PCIA_CTL_SG32K (0<<25) /* 32K SGMAP entries */
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#define PCIA_CTL_SG64K (1<<25) /* 64K SGMAP entries */
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#define PCIA_CTL_SG128K (3<<25) /* 128K SGMAP entries */
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#define PCIA_CTL_SG0K (2<<25) /* disable SGMAP in HPC */
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#define PCIA_CTL_4UP (0<<23) /* 4 Up Hose buffers */
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#define PCIA_CTL_1UP (1<<23) /* 1 "" */
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#define PCIA_CTL_2UP (2<<23) /* 2 "" */
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#define PCIA_CTL_3UP (3<<23) /* 3 "" (normal) */
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#define PCIA_CTL_RMM4X (1<<22) /* Read Multiple 2X -> 4X */
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#define PCIA_CTL_RMMENA (1<<21) /* Read Multiple Enable */
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#define PCIA_CTL_RMMARB (1<<20) /* RMM Multiple Arb */
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#define PCIA_CTL_HAEDIS (1<<19) /* Hardware Address Ext. Disable */
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#define PCIA_CTL_MHAE(x) ((x&0x1f)<<14) /* Memory Hardware Address Extension */
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#define PCIA_CTL_IHAE(x) ((x&0x1f)<<9) /* I/O Hardware Address Extension */
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#define PCIA_CTL_CUTENA (1<<8) /* PCI Cut Through */
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#define PCIA_CTL_CUT(x) ((x&0x7)<<4) /* PCI Cut Through Size */
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#define PCIA_CTL_PRESET (1<<3) /* PCI Reset */
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#define PCIA_CTL_DTHROT (1<<2) /* DMA downthrottle */
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#define PCIA_CTL_T1CYC (1<<0) /* Type 1 Configuration Cycle */
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/*
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* Bits in PCIA_ERR. All are "Write 1 to clear".
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*/
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#define PCIA_ERR_SERR_L (1<<18) /* PCI device asserted SERR_L */
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#define PCIA_ERR_ILAT (1<<17) /* Incremental Latency Exceeded */
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#define PCIA_ERR_SGPRTY (1<<16) /* CPU access of SG RAM Parity Error */
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#define PCIA_ERR_ILLCSR (1<<15) /* Illegal CSR Address Error */
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#define PCIA_ERR_PCINXM (1<<14) /* Nonexistent PCI Address Error */
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#define PCIA_ERR_DSCERR (1<<13) /* PCI Target Disconnect Error */
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#define PCIA_ERR_ABRT (1<<12) /* PCI Target Abort Error */
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#define PCIA_ERR_WPRTY (1<<11) /* PCI Write Parity Error */
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#define PCIA_ERR_DPERR (1<<10) /* PCI Data Parity Error */
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#define PCIA_ERR_APERR (1<<9) /* PCI Address Parity Error */
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#define PCIA_ERR_DFLT (1<<8) /* SG Map RAM Invalid Entry Error */
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#define PCIA_ERR_DPRTY (1<<7) /* DMA access of SG RAM Parity Error */
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#define PCIA_ERR_DRPERR (1<<6) /* DMA Read Return Parity Error */
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#define PCIA_ERR_MABRT (1<<5) /* PCI Master Abort Error */
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#define PCIA_ERR_CPRTY (1<<4) /* CSR Parity Error */
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#define PCIA_ERR_COVR (1<<3) /* CSR Overrun Error */
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#define PCIA_ERR_MBPERR (1<<2) /* Mailbox Parity Error */
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#define PCIA_ERR_MBILI (1<<1) /* Mailbox Illegal Length Error */
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#define PCIA_ERR_ERROR (1<<0) /* Summary Error */
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#define PCIA_ERR_ALLERR ((1<<19) - 1)
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/*
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* Bits in PCIA_PRESENT.
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*/
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#define PCIA_PRESENT_REVSHIFT 25 /* shift by this to get revision */
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#define PCIA_PRESENT_REVMASK 0xf
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#define PCIA_PRESENT_STDIO 0x01000000 /* STD I/O bridge present */
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#define PCIA_PRESENT_SLOTSHIFT(hpc, slot) \
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(((hpc) << 3) + ((slot) << 1))
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#define PCIA_PRESENT_SLOT_MASK 0x3
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#define PCIA_PRESENT_SLOT_NONE 0x0
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#define PCIA_PRESENT_SLOT_25W 0x1
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#define PCIA_PRESENT_SLOT_15W 0x2
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#define PCIA_PRESENT_SLOW_7W 0x3
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/*
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* Location of the DWLPx SGMAP page table SRAM.
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*/
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#define PCIA_SGMAP_PT 0x381000000UL
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/*
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* Values for PCIA_WMASK_x
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*/
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#define PCIA_WMASK_MASK 0xffff0000 /* mask of valid bits */
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#define PCIA_WMASK_64K 0x00000000
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#define PCIA_WMASK_128K 0x00010000
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#define PCIA_WMASK_256K 0x00030000
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#define PCIA_WMASK_512K 0x00070000
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#define PCIA_WMASK_1M 0x000f0000
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#define PCIA_WMASK_2M 0x001f0000
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#define PCIA_WMASK_4M 0x003f0000
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#define PCIA_WMASK_8M 0x007f0000
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#define PCIA_WMASK_16M 0x00ff0000
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#define PCIA_WMASK_32M 0x01ff0000
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#define PCIA_WMASK_64M 0x03ff0000
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#define PCIA_WMASK_128M 0x07ff0000
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#define PCIA_WMASK_256M 0x0fff0000
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#define PCIA_WMASK_512M 0x1fff0000
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#define PCIA_WMASK_1G 0x3fff0000
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#define PCIA_WMASK_2G 0x7fff0000
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#define PCIA_WMASK_4G 0xffff0000
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/*
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* Values for PCIA_WBASE_x
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*/
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#define PCIA_WBASE_MASK 0xffff0000 /* mask of valid bits in address */
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#define PCIA_WBASE_W_EN 0x00000002 /* window enable */
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#define PCIA_WBASE_SG_EN 0x00000001 /* SGMAP enable */
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/*
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* Values for PCIA_TBASE_x
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*
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* NOTE: Translated Base is only used on direct-mapped DMA on the DWLPx!!
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*/
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#define PCIA_TBASE_MASK 0x00fffffe
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#define PCIA_TBASE_SHIFT 15
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