2017-02-15 13:37:32 +00:00
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/*
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* AMD 10Gb Ethernet driver
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*
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* This file is available to you under your choice of the following two
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* licenses:
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*
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* License 1: GPLv2
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*
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* Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
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*
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* This file is free software; you may copy, redistribute and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or (at
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* your option) any later version.
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*
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* This file is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* This file incorporates work covered by the following copyright and
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* permission notice:
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* The Synopsys DWC ETHER XGMAC Software Driver and documentation
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* (hereinafter "Software") is an unsupported proprietary work of Synopsys,
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* Inc. unless otherwise expressly agreed to in writing between Synopsys
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* and you.
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*
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* The Software IS NOT an item of Licensed Software or Licensed Product
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* under any End User Software License Agreement or Agreement for Licensed
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* Product with Synopsys or any supplement thereto. Permission is hereby
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* granted, free of charge, to any person obtaining a copy of this software
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* annotated with this license and the Software, to deal in the Software
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* without restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is furnished
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* to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
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* BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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* PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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*
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* License 2: Modified BSD
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*
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* Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Advanced Micro Devices, Inc. nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* This file incorporates work covered by the following copyright and
|
|
|
|
* permission notice:
|
|
|
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* The Synopsys DWC ETHER XGMAC Software Driver and documentation
|
|
|
|
* (hereinafter "Software") is an unsupported proprietary work of Synopsys,
|
|
|
|
* Inc. unless otherwise expressly agreed to in writing between Synopsys
|
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|
|
* and you.
|
|
|
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*
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* The Software IS NOT an item of Licensed Software or Licensed Product
|
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|
|
* under any End User Software License Agreement or Agreement for Licensed
|
|
|
|
* Product with Synopsys or any supplement thereto. Permission is hereby
|
|
|
|
* granted, free of charge, to any person obtaining a copy of this software
|
|
|
|
* annotated with this license and the Software, to deal in the Software
|
|
|
|
* without restriction, including without limitation the rights to use,
|
|
|
|
* copy, modify, merge, publish, distribute, sublicense, and/or sell copies
|
|
|
|
* of the Software, and to permit persons to whom the Software is furnished
|
|
|
|
* to do so, subject to the following conditions:
|
|
|
|
*
|
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|
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* The above copyright notice and this permission notice shall be included
|
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|
|
* in all copies or substantial portions of the Software.
|
|
|
|
*
|
|
|
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* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
|
|
|
|
* BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
|
|
|
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
|
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|
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* PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
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|
|
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
|
|
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
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|
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*/
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2017-02-15 13:56:04 +00:00
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/kernel.h>
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2017-02-15 13:37:32 +00:00
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#include "xgbe.h"
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#include "xgbe-common.h"
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2017-02-15 13:56:04 +00:00
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static int xgbe_one_poll(struct xgbe_channel *channel, int budget);
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static int xgbe_all_poll(struct xgbe_prv_data *pdata, int budget);
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2017-02-15 13:37:32 +00:00
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static int xgbe_alloc_channels(struct xgbe_prv_data *pdata)
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{
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struct xgbe_channel *channel_mem, *channel;
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struct xgbe_ring *tx_ring, *rx_ring;
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unsigned int count, i;
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int ret = -ENOMEM;
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count = max_t(unsigned int, pdata->tx_ring_count, pdata->rx_ring_count);
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2017-02-15 13:56:04 +00:00
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channel_mem = malloc(count * sizeof(struct xgbe_channel), M_AXGBE,
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M_WAITOK | M_ZERO);
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tx_ring = malloc(pdata->tx_ring_count * sizeof(struct xgbe_ring),
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M_AXGBE, M_WAITOK | M_ZERO);
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rx_ring = malloc(pdata->rx_ring_count * sizeof(struct xgbe_ring),
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M_AXGBE, M_WAITOK | M_ZERO);
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2017-02-15 13:37:32 +00:00
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for (i = 0, channel = channel_mem; i < count; i++, channel++) {
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snprintf(channel->name, sizeof(channel->name), "channel-%d", i);
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channel->pdata = pdata;
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channel->queue_index = i;
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2017-02-15 13:56:04 +00:00
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channel->dma_tag = rman_get_bustag(pdata->xgmac_res);
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bus_space_subregion(channel->dma_tag,
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rman_get_bushandle(pdata->xgmac_res),
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DMA_CH_BASE + (DMA_CH_INC * i), DMA_CH_INC,
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&channel->dma_handle);
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2017-02-15 13:37:32 +00:00
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if (pdata->per_channel_irq) {
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2017-02-15 13:56:04 +00:00
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if (pdata->chan_irq_res[i] == NULL)
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2017-02-15 13:37:32 +00:00
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goto err_irq;
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2017-02-15 13:56:04 +00:00
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channel->dma_irq_res = pdata->chan_irq_res[i];
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2017-02-15 13:37:32 +00:00
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}
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if (i < pdata->tx_ring_count) {
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spin_lock_init(&tx_ring->lock);
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channel->tx_ring = tx_ring++;
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}
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if (i < pdata->rx_ring_count) {
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spin_lock_init(&rx_ring->lock);
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channel->rx_ring = rx_ring++;
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}
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}
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pdata->channel = channel_mem;
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pdata->channel_count = count;
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return 0;
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err_irq:
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2017-02-15 13:56:04 +00:00
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free(rx_ring, M_AXGBE);
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free(tx_ring, M_AXGBE);
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free(channel_mem, M_AXGBE);
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2017-02-15 13:37:32 +00:00
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return ret;
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}
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static void xgbe_free_channels(struct xgbe_prv_data *pdata)
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{
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if (!pdata->channel)
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return;
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2017-02-15 13:56:04 +00:00
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free(pdata->channel->rx_ring, M_AXGBE);
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free(pdata->channel->tx_ring, M_AXGBE);
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free(pdata->channel, M_AXGBE);
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2017-02-15 13:37:32 +00:00
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pdata->channel = NULL;
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pdata->channel_count = 0;
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}
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static inline unsigned int xgbe_tx_avail_desc(struct xgbe_ring *ring)
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{
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return (ring->rdesc_count - (ring->cur - ring->dirty));
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}
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static inline unsigned int xgbe_rx_dirty_desc(struct xgbe_ring *ring)
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{
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return (ring->cur - ring->dirty);
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}
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static int xgbe_maybe_stop_tx_queue(struct xgbe_channel *channel,
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struct xgbe_ring *ring, unsigned int count)
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{
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struct xgbe_prv_data *pdata = channel->pdata;
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if (count > xgbe_tx_avail_desc(ring)) {
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/* If we haven't notified the hardware because of xmit_more
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* support, tell it now
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*/
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if (ring->tx.xmit_more)
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pdata->hw_if.tx_start_xmit(channel, ring);
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2017-02-15 13:56:04 +00:00
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return EFBIG;
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2017-02-15 13:37:32 +00:00
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}
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return 0;
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}
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2017-02-15 13:56:04 +00:00
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static int xgbe_calc_rx_buf_size(struct ifnet *netdev, unsigned int mtu)
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2017-02-15 13:37:32 +00:00
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{
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unsigned int rx_buf_size;
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if (mtu > XGMAC_JUMBO_PACKET_MTU) {
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return -EINVAL;
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}
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rx_buf_size = mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
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2017-02-15 13:56:04 +00:00
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rx_buf_size = MIN(XGBE_RX_MIN_BUF_SIZE, PAGE_SIZE);
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2017-02-15 13:37:32 +00:00
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rx_buf_size = (rx_buf_size + XGBE_RX_BUF_ALIGN - 1) &
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~(XGBE_RX_BUF_ALIGN - 1);
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return rx_buf_size;
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}
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static void xgbe_enable_rx_tx_ints(struct xgbe_prv_data *pdata)
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{
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struct xgbe_hw_if *hw_if = &pdata->hw_if;
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struct xgbe_channel *channel;
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enum xgbe_int int_id;
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unsigned int i;
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channel = pdata->channel;
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for (i = 0; i < pdata->channel_count; i++, channel++) {
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if (channel->tx_ring && channel->rx_ring)
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int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
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else if (channel->tx_ring)
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int_id = XGMAC_INT_DMA_CH_SR_TI;
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else if (channel->rx_ring)
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int_id = XGMAC_INT_DMA_CH_SR_RI;
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else
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continue;
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hw_if->enable_int(channel, int_id);
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}
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}
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2017-02-15 13:56:04 +00:00
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static void xgbe_isr(void *data)
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2017-02-15 13:37:32 +00:00
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{
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struct xgbe_prv_data *pdata = data;
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struct xgbe_hw_if *hw_if = &pdata->hw_if;
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struct xgbe_channel *channel;
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unsigned int dma_isr, dma_ch_isr;
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2017-02-15 13:56:04 +00:00
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unsigned int mac_isr;
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2017-02-15 13:37:32 +00:00
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unsigned int i;
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/* The DMA interrupt status register also reports MAC and MTL
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* interrupts. So for polling mode, we just need to check for
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* this register to be non-zero
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*/
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dma_isr = XGMAC_IOREAD(pdata, DMA_ISR);
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if (!dma_isr)
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2017-02-15 13:56:04 +00:00
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return;
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2017-02-15 13:37:32 +00:00
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for (i = 0; i < pdata->channel_count; i++) {
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if (!(dma_isr & (1 << i)))
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continue;
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channel = pdata->channel + i;
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dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR);
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/* The TI or RI interrupt bits may still be set even if using
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* per channel DMA interrupts. Check to be sure those are not
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* enabled before using the private data napi structure.
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*/
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if (!pdata->per_channel_irq &&
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(XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, TI) ||
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XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RI))) {
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2017-02-15 13:56:04 +00:00
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xgbe_all_poll(pdata, 16);
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2017-02-15 13:37:32 +00:00
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}
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if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RBU))
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pdata->ext_stats.rx_buffer_unavailable++;
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/* Restart the device on a Fatal Bus Error */
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if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, FBE))
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2017-02-15 13:56:04 +00:00
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taskqueue_enqueue(taskqueue_thread,
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&pdata->restart_work);
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2017-02-15 13:37:32 +00:00
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/* Clear all interrupt signals */
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XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr);
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}
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if (XGMAC_GET_BITS(dma_isr, DMA_ISR, MACIS)) {
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mac_isr = XGMAC_IOREAD(pdata, MAC_ISR);
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if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCTXIS))
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hw_if->tx_mmc_int(pdata);
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if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCRXIS))
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hw_if->rx_mmc_int(pdata);
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}
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}
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2017-02-15 13:56:04 +00:00
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|
|
static void xgbe_dma_isr(void *data)
|
2017-02-15 13:37:32 +00:00
|
|
|
{
|
|
|
|
struct xgbe_channel *channel = data;
|
|
|
|
|
2017-02-15 13:56:04 +00:00
|
|
|
xgbe_one_poll(channel, 16);
|
2017-02-15 13:37:32 +00:00
|
|
|
}
|
|
|
|
|
2017-02-15 13:56:04 +00:00
|
|
|
static void xgbe_service(void *ctx, int pending)
|
2017-02-15 13:37:32 +00:00
|
|
|
{
|
2017-02-15 13:56:04 +00:00
|
|
|
struct xgbe_prv_data *pdata = ctx;
|
2017-02-15 13:37:32 +00:00
|
|
|
|
|
|
|
pdata->phy_if.phy_status(pdata);
|
|
|
|
}
|
|
|
|
|
2017-02-15 13:56:04 +00:00
|
|
|
static void xgbe_service_timer(void *data)
|
2017-02-15 13:37:32 +00:00
|
|
|
{
|
2017-02-15 13:56:04 +00:00
|
|
|
struct xgbe_prv_data *pdata = data;
|
2017-02-15 13:37:32 +00:00
|
|
|
|
2017-02-15 13:56:04 +00:00
|
|
|
DBGPR("--> xgbe_service_timer\n");
|
|
|
|
taskqueue_enqueue(pdata->dev_workqueue, &pdata->service_work);
|
2017-02-15 13:37:32 +00:00
|
|
|
|
2017-02-15 13:56:04 +00:00
|
|
|
callout_reset(&pdata->service_timer, hz, xgbe_service_timer, pdata);
|
|
|
|
DBGPR("<-- xgbe_service_timer\n");
|
2017-02-15 13:37:32 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void xgbe_init_timers(struct xgbe_prv_data *pdata)
|
|
|
|
{
|
|
|
|
|
2017-02-15 13:56:04 +00:00
|
|
|
callout_init(&pdata->service_timer, 1);
|
2017-02-15 13:37:32 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void xgbe_start_timers(struct xgbe_prv_data *pdata)
|
|
|
|
{
|
2017-02-15 13:56:04 +00:00
|
|
|
callout_reset(&pdata->service_timer, hz, xgbe_service_timer, pdata);
|
2017-02-15 13:37:32 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void xgbe_stop_timers(struct xgbe_prv_data *pdata)
|
|
|
|
{
|
|
|
|
|
2017-02-15 13:56:04 +00:00
|
|
|
callout_drain(&pdata->service_timer);
|
2017-02-15 13:37:32 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void xgbe_get_all_hw_features(struct xgbe_prv_data *pdata)
|
|
|
|
{
|
|
|
|
unsigned int mac_hfr0, mac_hfr1, mac_hfr2;
|
|
|
|
struct xgbe_hw_features *hw_feat = &pdata->hw_feat;
|
|
|
|
|
|
|
|
DBGPR("-->xgbe_get_all_hw_features\n");
|
|
|
|
|
|
|
|
mac_hfr0 = XGMAC_IOREAD(pdata, MAC_HWF0R);
|
|
|
|
mac_hfr1 = XGMAC_IOREAD(pdata, MAC_HWF1R);
|
|
|
|
mac_hfr2 = XGMAC_IOREAD(pdata, MAC_HWF2R);
|
|
|
|
|
|
|
|
memset(hw_feat, 0, sizeof(*hw_feat));
|
|
|
|
|
|
|
|
hw_feat->version = XGMAC_IOREAD(pdata, MAC_VR);
|
|
|
|
|
|
|
|
/* Hardware feature register 0 */
|
|
|
|
hw_feat->gmii = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL);
|
|
|
|
hw_feat->vlhash = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH);
|
|
|
|
hw_feat->sma = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL);
|
|
|
|
hw_feat->rwk = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL);
|
|
|
|
hw_feat->mgk = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL);
|
|
|
|
hw_feat->mmc = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL);
|
|
|
|
hw_feat->aoe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL);
|
|
|
|
hw_feat->ts = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL);
|
|
|
|
hw_feat->eee = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL);
|
|
|
|
hw_feat->tx_coe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL);
|
|
|
|
hw_feat->rx_coe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL);
|
|
|
|
hw_feat->addn_mac = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R,
|
|
|
|
ADDMACADRSEL);
|
|
|
|
hw_feat->ts_src = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL);
|
|
|
|
hw_feat->sa_vlan_ins = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS);
|
|
|
|
|
|
|
|
/* Hardware feature register 1 */
|
|
|
|
hw_feat->rx_fifo_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
|
|
|
|
RXFIFOSIZE);
|
|
|
|
hw_feat->tx_fifo_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
|
|
|
|
TXFIFOSIZE);
|
|
|
|
hw_feat->adv_ts_hi = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADVTHWORD);
|
|
|
|
hw_feat->dma_width = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADDR64);
|
|
|
|
hw_feat->dcb = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN);
|
|
|
|
hw_feat->sph = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN);
|
|
|
|
hw_feat->tso = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN);
|
|
|
|
hw_feat->dma_debug = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA);
|
|
|
|
hw_feat->rss = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, RSSEN);
|
|
|
|
hw_feat->tc_cnt = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC);
|
|
|
|
hw_feat->hash_table_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
|
|
|
|
HASHTBLSZ);
|
|
|
|
hw_feat->l3l4_filter_num = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
|
|
|
|
L3L4FNUM);
|
|
|
|
|
|
|
|
/* Hardware feature register 2 */
|
|
|
|
hw_feat->rx_q_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT);
|
|
|
|
hw_feat->tx_q_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT);
|
|
|
|
hw_feat->rx_ch_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT);
|
|
|
|
hw_feat->tx_ch_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT);
|
|
|
|
hw_feat->pps_out_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM);
|
|
|
|
hw_feat->aux_snap_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, AUXSNAPNUM);
|
|
|
|
|
|
|
|
/* Translate the Hash Table size into actual number */
|
|
|
|
switch (hw_feat->hash_table_size) {
|
|
|
|
case 0:
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
hw_feat->hash_table_size = 64;
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
hw_feat->hash_table_size = 128;
|
|
|
|
break;
|
|
|
|
case 3:
|
|
|
|
hw_feat->hash_table_size = 256;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Translate the address width setting into actual number */
|
|
|
|
switch (hw_feat->dma_width) {
|
|
|
|
case 0:
|
|
|
|
hw_feat->dma_width = 32;
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
hw_feat->dma_width = 40;
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
hw_feat->dma_width = 48;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
hw_feat->dma_width = 32;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* The Queue, Channel and TC counts are zero based so increment them
|
|
|
|
* to get the actual number
|
|
|
|
*/
|
|
|
|
hw_feat->rx_q_cnt++;
|
|
|
|
hw_feat->tx_q_cnt++;
|
|
|
|
hw_feat->rx_ch_cnt++;
|
|
|
|
hw_feat->tx_ch_cnt++;
|
|
|
|
hw_feat->tc_cnt++;
|
|
|
|
|
|
|
|
DBGPR("<--xgbe_get_all_hw_features\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
static int xgbe_request_irqs(struct xgbe_prv_data *pdata)
|
|
|
|
{
|
|
|
|
struct xgbe_channel *channel;
|
|
|
|
unsigned int i;
|
|
|
|
int ret;
|
|
|
|
|
2017-02-15 13:56:04 +00:00
|
|
|
ret = bus_setup_intr(pdata->dev, pdata->dev_irq_res,
|
|
|
|
INTR_MPSAFE | INTR_TYPE_NET, NULL, xgbe_isr, pdata,
|
|
|
|
&pdata->dev_irq_tag);
|
2017-02-15 13:37:32 +00:00
|
|
|
if (ret) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!pdata->per_channel_irq)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
channel = pdata->channel;
|
|
|
|
for (i = 0; i < pdata->channel_count; i++, channel++) {
|
2017-02-15 13:56:04 +00:00
|
|
|
ret = bus_setup_intr(pdata->dev, channel->dma_irq_res,
|
|
|
|
INTR_MPSAFE | INTR_TYPE_NET, NULL, xgbe_dma_isr, channel,
|
|
|
|
&channel->dma_irq_tag);
|
|
|
|
if (ret != 0) {
|
2017-02-15 13:37:32 +00:00
|
|
|
goto err_irq;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_irq:
|
|
|
|
/* Using an unsigned int, 'i' will go to UINT_MAX and exit */
|
|
|
|
for (i--, channel--; i < pdata->channel_count; i--, channel--)
|
2017-02-15 13:56:04 +00:00
|
|
|
bus_teardown_intr(pdata->dev, channel->dma_irq_res,
|
|
|
|
channel->dma_irq_tag);
|
2017-02-15 13:37:32 +00:00
|
|
|
|
2017-02-15 13:56:04 +00:00
|
|
|
bus_teardown_intr(pdata->dev, pdata->dev_irq_res, pdata->dev_irq_tag);
|
2017-02-15 13:37:32 +00:00
|
|
|
|
2017-02-15 13:56:04 +00:00
|
|
|
return -ret;
|
2017-02-15 13:37:32 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void xgbe_free_irqs(struct xgbe_prv_data *pdata)
|
|
|
|
{
|
|
|
|
struct xgbe_channel *channel;
|
|
|
|
unsigned int i;
|
|
|
|
|
2017-02-15 13:56:04 +00:00
|
|
|
bus_teardown_intr(pdata->dev, pdata->dev_irq_res, pdata->dev_irq_tag);
|
2017-02-15 13:37:32 +00:00
|
|
|
|
|
|
|
if (!pdata->per_channel_irq)
|
|
|
|
return;
|
|
|
|
|
|
|
|
channel = pdata->channel;
|
|
|
|
for (i = 0; i < pdata->channel_count; i++, channel++)
|
2017-02-15 13:56:04 +00:00
|
|
|
bus_teardown_intr(pdata->dev, channel->dma_irq_res,
|
|
|
|
channel->dma_irq_tag);
|
2017-02-15 13:37:32 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void xgbe_init_tx_coalesce(struct xgbe_prv_data *pdata)
|
|
|
|
{
|
|
|
|
struct xgbe_hw_if *hw_if = &pdata->hw_if;
|
|
|
|
|
|
|
|
DBGPR("-->xgbe_init_tx_coalesce\n");
|
|
|
|
|
|
|
|
pdata->tx_usecs = XGMAC_INIT_DMA_TX_USECS;
|
|
|
|
pdata->tx_frames = XGMAC_INIT_DMA_TX_FRAMES;
|
|
|
|
|
|
|
|
hw_if->config_tx_coalesce(pdata);
|
|
|
|
|
|
|
|
DBGPR("<--xgbe_init_tx_coalesce\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
void xgbe_init_rx_coalesce(struct xgbe_prv_data *pdata)
|
|
|
|
{
|
|
|
|
struct xgbe_hw_if *hw_if = &pdata->hw_if;
|
|
|
|
|
|
|
|
DBGPR("-->xgbe_init_rx_coalesce\n");
|
|
|
|
|
|
|
|
pdata->rx_riwt = hw_if->usec_to_riwt(pdata, XGMAC_INIT_DMA_RX_USECS);
|
|
|
|
pdata->rx_usecs = XGMAC_INIT_DMA_RX_USECS;
|
|
|
|
pdata->rx_frames = XGMAC_INIT_DMA_RX_FRAMES;
|
|
|
|
|
|
|
|
hw_if->config_rx_coalesce(pdata);
|
|
|
|
|
|
|
|
DBGPR("<--xgbe_init_rx_coalesce\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
static void xgbe_free_tx_data(struct xgbe_prv_data *pdata)
|
|
|
|
{
|
|
|
|
struct xgbe_desc_if *desc_if = &pdata->desc_if;
|
|
|
|
struct xgbe_channel *channel;
|
|
|
|
struct xgbe_ring *ring;
|
|
|
|
struct xgbe_ring_data *rdata;
|
|
|
|
unsigned int i, j;
|
|
|
|
|
|
|
|
DBGPR("-->xgbe_free_tx_data\n");
|
|
|
|
|
|
|
|
channel = pdata->channel;
|
|
|
|
for (i = 0; i < pdata->channel_count; i++, channel++) {
|
|
|
|
ring = channel->tx_ring;
|
|
|
|
if (!ring)
|
|
|
|
break;
|
|
|
|
|
|
|
|
for (j = 0; j < ring->rdesc_count; j++) {
|
|
|
|
rdata = XGBE_GET_DESC_DATA(ring, j);
|
|
|
|
desc_if->unmap_rdata(pdata, rdata);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
DBGPR("<--xgbe_free_tx_data\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
static void xgbe_free_rx_data(struct xgbe_prv_data *pdata)
|
|
|
|
{
|
|
|
|
struct xgbe_desc_if *desc_if = &pdata->desc_if;
|
|
|
|
struct xgbe_channel *channel;
|
|
|
|
struct xgbe_ring *ring;
|
|
|
|
struct xgbe_ring_data *rdata;
|
|
|
|
unsigned int i, j;
|
|
|
|
|
|
|
|
DBGPR("-->xgbe_free_rx_data\n");
|
|
|
|
|
|
|
|
channel = pdata->channel;
|
|
|
|
for (i = 0; i < pdata->channel_count; i++, channel++) {
|
|
|
|
ring = channel->rx_ring;
|
|
|
|
if (!ring)
|
|
|
|
break;
|
|
|
|
|
|
|
|
for (j = 0; j < ring->rdesc_count; j++) {
|
|
|
|
rdata = XGBE_GET_DESC_DATA(ring, j);
|
|
|
|
desc_if->unmap_rdata(pdata, rdata);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
DBGPR("<--xgbe_free_rx_data\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
static int xgbe_phy_init(struct xgbe_prv_data *pdata)
|
|
|
|
{
|
|
|
|
pdata->phy_link = -1;
|
|
|
|
pdata->phy_speed = SPEED_UNKNOWN;
|
|
|
|
|
|
|
|
return pdata->phy_if.phy_reset(pdata);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int xgbe_start(struct xgbe_prv_data *pdata)
|
|
|
|
{
|
|
|
|
struct xgbe_hw_if *hw_if = &pdata->hw_if;
|
|
|
|
struct xgbe_phy_if *phy_if = &pdata->phy_if;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
DBGPR("-->xgbe_start\n");
|
|
|
|
|
|
|
|
hw_if->init(pdata);
|
|
|
|
|
|
|
|
ret = phy_if->phy_start(pdata);
|
|
|
|
if (ret)
|
|
|
|
goto err_phy;
|
|
|
|
|
|
|
|
ret = xgbe_request_irqs(pdata);
|
|
|
|
if (ret)
|
|
|
|
goto err_napi;
|
|
|
|
|
|
|
|
hw_if->enable_tx(pdata);
|
|
|
|
hw_if->enable_rx(pdata);
|
|
|
|
|
2017-02-15 13:56:04 +00:00
|
|
|
xgbe_enable_rx_tx_ints(pdata);
|
2017-02-15 13:37:32 +00:00
|
|
|
|
|
|
|
xgbe_start_timers(pdata);
|
2017-02-15 13:56:04 +00:00
|
|
|
taskqueue_enqueue(pdata->dev_workqueue, &pdata->service_work);
|
2017-02-15 13:37:32 +00:00
|
|
|
|
|
|
|
DBGPR("<--xgbe_start\n");
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_napi:
|
|
|
|
phy_if->phy_stop(pdata);
|
|
|
|
|
|
|
|
err_phy:
|
|
|
|
hw_if->exit(pdata);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void xgbe_stop(struct xgbe_prv_data *pdata)
|
|
|
|
{
|
|
|
|
struct xgbe_hw_if *hw_if = &pdata->hw_if;
|
|
|
|
struct xgbe_phy_if *phy_if = &pdata->phy_if;
|
|
|
|
|
|
|
|
DBGPR("-->xgbe_stop\n");
|
|
|
|
|
|
|
|
xgbe_stop_timers(pdata);
|
2017-02-15 13:56:04 +00:00
|
|
|
taskqueue_drain_all(pdata->dev_workqueue);
|
2017-02-15 13:37:32 +00:00
|
|
|
|
|
|
|
hw_if->disable_tx(pdata);
|
|
|
|
hw_if->disable_rx(pdata);
|
|
|
|
|
|
|
|
xgbe_free_irqs(pdata);
|
|
|
|
|
|
|
|
phy_if->phy_stop(pdata);
|
|
|
|
|
|
|
|
hw_if->exit(pdata);
|
|
|
|
|
|
|
|
DBGPR("<--xgbe_stop\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
static void xgbe_restart_dev(struct xgbe_prv_data *pdata)
|
|
|
|
{
|
|
|
|
DBGPR("-->xgbe_restart_dev\n");
|
|
|
|
|
|
|
|
/* If not running, "restart" will happen on open */
|
2017-02-15 13:56:04 +00:00
|
|
|
if ((pdata->netdev->if_drv_flags & IFF_DRV_RUNNING) == 0)
|
2017-02-15 13:37:32 +00:00
|
|
|
return;
|
|
|
|
|
|
|
|
xgbe_stop(pdata);
|
|
|
|
|
|
|
|
xgbe_free_tx_data(pdata);
|
|
|
|
xgbe_free_rx_data(pdata);
|
|
|
|
|
|
|
|
xgbe_start(pdata);
|
|
|
|
|
|
|
|
DBGPR("<--xgbe_restart_dev\n");
|
|
|
|
}
|
|
|
|
|
2017-02-15 13:56:04 +00:00
|
|
|
static void xgbe_restart(void *ctx, int pending)
|
2017-02-15 13:37:32 +00:00
|
|
|
{
|
2017-02-15 13:56:04 +00:00
|
|
|
struct xgbe_prv_data *pdata = ctx;
|
2017-02-15 13:37:32 +00:00
|
|
|
|
|
|
|
xgbe_restart_dev(pdata);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void xgbe_packet_info(struct xgbe_prv_data *pdata,
|
2017-02-15 13:56:04 +00:00
|
|
|
struct xgbe_ring *ring, struct mbuf *m0,
|
2017-02-15 13:37:32 +00:00
|
|
|
struct xgbe_packet_data *packet)
|
|
|
|
{
|
2017-02-15 13:56:04 +00:00
|
|
|
struct mbuf *m;
|
2017-02-15 13:37:32 +00:00
|
|
|
unsigned int len;
|
|
|
|
|
2017-02-15 13:56:04 +00:00
|
|
|
packet->m = m0;
|
2017-02-15 13:37:32 +00:00
|
|
|
|
|
|
|
packet->rdesc_count = 0;
|
|
|
|
|
|
|
|
packet->tx_packets = 1;
|
2017-02-15 13:56:04 +00:00
|
|
|
packet->tx_bytes = m_length(m0, NULL);
|
2017-02-15 13:37:32 +00:00
|
|
|
|
2017-02-15 13:56:04 +00:00
|
|
|
for (m = m0; m != NULL; m = m->m_next) {
|
|
|
|
for (len = m->m_len; len != 0;) {
|
2017-02-15 13:37:32 +00:00
|
|
|
packet->rdesc_count++;
|
2017-02-15 13:56:04 +00:00
|
|
|
len -= MIN(len, XGBE_TX_MAX_BUF_SIZE);
|
2017-02-15 13:37:32 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-02-15 13:56:04 +00:00
|
|
|
int xgbe_open(struct ifnet *netdev)
|
2017-02-15 13:37:32 +00:00
|
|
|
{
|
2017-02-15 13:56:04 +00:00
|
|
|
struct xgbe_prv_data *pdata = netdev->if_softc;
|
2017-02-15 13:37:32 +00:00
|
|
|
struct xgbe_desc_if *desc_if = &pdata->desc_if;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
DBGPR("-->xgbe_open\n");
|
|
|
|
|
|
|
|
/* Initialize the phy */
|
|
|
|
ret = xgbe_phy_init(pdata);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
/* Calculate the Rx buffer size before allocating rings */
|
2017-02-15 13:56:04 +00:00
|
|
|
ret = xgbe_calc_rx_buf_size(netdev, if_getmtu(netdev));
|
|
|
|
if (ret < 0) {
|
2017-02-15 13:37:32 +00:00
|
|
|
goto err_ptpclk;
|
2017-02-15 13:56:04 +00:00
|
|
|
}
|
2017-02-15 13:37:32 +00:00
|
|
|
pdata->rx_buf_size = ret;
|
|
|
|
|
|
|
|
/* Allocate the channel and ring structures */
|
|
|
|
ret = xgbe_alloc_channels(pdata);
|
2017-02-15 13:56:04 +00:00
|
|
|
if (ret) {
|
|
|
|
printf("xgbe_alloc_channels failed\n");
|
2017-02-15 13:37:32 +00:00
|
|
|
goto err_ptpclk;
|
2017-02-15 13:56:04 +00:00
|
|
|
}
|
2017-02-15 13:37:32 +00:00
|
|
|
|
|
|
|
/* Allocate the ring descriptors and buffers */
|
|
|
|
ret = desc_if->alloc_ring_resources(pdata);
|
2017-02-15 13:56:04 +00:00
|
|
|
if (ret) {
|
|
|
|
printf("desc_if->alloc_ring_resources failed\n");
|
2017-02-15 13:37:32 +00:00
|
|
|
goto err_channels;
|
2017-02-15 13:56:04 +00:00
|
|
|
}
|
2017-02-15 13:37:32 +00:00
|
|
|
|
2017-02-15 13:56:04 +00:00
|
|
|
TASK_INIT(&pdata->service_work, 0, xgbe_service, pdata);
|
|
|
|
TASK_INIT(&pdata->restart_work, 0, xgbe_restart, pdata);
|
2017-02-15 13:37:32 +00:00
|
|
|
xgbe_init_timers(pdata);
|
|
|
|
|
|
|
|
ret = xgbe_start(pdata);
|
|
|
|
if (ret)
|
|
|
|
goto err_rings;
|
|
|
|
|
|
|
|
clear_bit(XGBE_DOWN, &pdata->dev_state);
|
|
|
|
|
|
|
|
DBGPR("<--xgbe_open\n");
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_rings:
|
|
|
|
desc_if->free_ring_resources(pdata);
|
|
|
|
|
|
|
|
err_channels:
|
|
|
|
xgbe_free_channels(pdata);
|
|
|
|
|
|
|
|
err_ptpclk:
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2017-02-15 13:56:04 +00:00
|
|
|
int xgbe_close(struct ifnet *netdev)
|
2017-02-15 13:37:32 +00:00
|
|
|
{
|
2017-02-15 13:56:04 +00:00
|
|
|
struct xgbe_prv_data *pdata = netdev->if_softc;
|
2017-02-15 13:37:32 +00:00
|
|
|
struct xgbe_desc_if *desc_if = &pdata->desc_if;
|
|
|
|
|
|
|
|
DBGPR("-->xgbe_close\n");
|
|
|
|
|
|
|
|
/* Stop the device */
|
|
|
|
xgbe_stop(pdata);
|
|
|
|
|
|
|
|
/* Free the ring descriptors and buffers */
|
|
|
|
desc_if->free_ring_resources(pdata);
|
|
|
|
|
|
|
|
/* Free the channel and ring structures */
|
|
|
|
xgbe_free_channels(pdata);
|
|
|
|
|
|
|
|
set_bit(XGBE_DOWN, &pdata->dev_state);
|
|
|
|
|
|
|
|
DBGPR("<--xgbe_close\n");
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-02-15 13:56:04 +00:00
|
|
|
int xgbe_xmit(struct ifnet *ifp, struct mbuf *m)
|
2017-02-15 13:37:32 +00:00
|
|
|
{
|
2017-02-15 13:56:04 +00:00
|
|
|
struct xgbe_prv_data *pdata = ifp->if_softc;
|
2017-02-15 13:37:32 +00:00
|
|
|
struct xgbe_hw_if *hw_if = &pdata->hw_if;
|
|
|
|
struct xgbe_desc_if *desc_if = &pdata->desc_if;
|
|
|
|
struct xgbe_channel *channel;
|
|
|
|
struct xgbe_ring *ring;
|
|
|
|
struct xgbe_packet_data *packet;
|
|
|
|
int ret;
|
|
|
|
|
2017-02-15 13:56:04 +00:00
|
|
|
M_ASSERTPKTHDR(m);
|
|
|
|
MPASS(m->m_nextpkt == NULL);
|
2017-02-15 13:37:32 +00:00
|
|
|
|
2017-02-15 13:56:04 +00:00
|
|
|
if (__predict_false(test_bit(XGBE_DOWN, &pdata->dev_state) ||
|
|
|
|
!pdata->phy.link)) {
|
|
|
|
m_freem(m);
|
|
|
|
return (ENETDOWN);
|
|
|
|
}
|
|
|
|
|
|
|
|
channel = pdata->channel;
|
2017-02-15 13:37:32 +00:00
|
|
|
ring = channel->tx_ring;
|
|
|
|
packet = &ring->packet_data;
|
|
|
|
|
|
|
|
/* Calculate preliminary packet info */
|
|
|
|
memset(packet, 0, sizeof(*packet));
|
2017-02-15 13:56:04 +00:00
|
|
|
xgbe_packet_info(pdata, ring, m, packet);
|
2017-02-15 13:37:32 +00:00
|
|
|
|
|
|
|
/* Check that there are enough descriptors available */
|
|
|
|
ret = xgbe_maybe_stop_tx_queue(channel, ring, packet->rdesc_count);
|
|
|
|
if (ret)
|
|
|
|
goto tx_netdev_return;
|
|
|
|
|
2017-02-15 13:56:04 +00:00
|
|
|
if (!desc_if->map_tx_skb(channel, m)) {
|
2017-02-15 13:37:32 +00:00
|
|
|
goto tx_netdev_return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Configure required descriptor fields for transmission */
|
|
|
|
hw_if->dev_xmit(channel);
|
|
|
|
|
2017-02-15 13:56:04 +00:00
|
|
|
return 0;
|
2017-02-15 13:37:32 +00:00
|
|
|
|
|
|
|
tx_netdev_return:
|
2017-02-15 13:56:04 +00:00
|
|
|
m_free(m);
|
2017-02-15 13:37:32 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-02-15 13:56:04 +00:00
|
|
|
int xgbe_change_mtu(struct ifnet *netdev, int mtu)
|
2017-02-15 13:37:32 +00:00
|
|
|
{
|
2017-02-15 13:56:04 +00:00
|
|
|
struct xgbe_prv_data *pdata = netdev->if_softc;
|
2017-02-15 13:37:32 +00:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
DBGPR("-->xgbe_change_mtu\n");
|
|
|
|
|
|
|
|
ret = xgbe_calc_rx_buf_size(netdev, mtu);
|
|
|
|
if (ret < 0)
|
2017-02-15 13:56:04 +00:00
|
|
|
return -ret;
|
2017-02-15 13:37:32 +00:00
|
|
|
|
|
|
|
pdata->rx_buf_size = ret;
|
2017-02-15 13:56:04 +00:00
|
|
|
netdev->if_mtu = mtu;
|
2017-02-15 13:37:32 +00:00
|
|
|
|
|
|
|
xgbe_restart_dev(pdata);
|
|
|
|
|
|
|
|
DBGPR("<--xgbe_change_mtu\n");
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void xgbe_rx_refresh(struct xgbe_channel *channel)
|
|
|
|
{
|
|
|
|
struct xgbe_prv_data *pdata = channel->pdata;
|
|
|
|
struct xgbe_hw_if *hw_if = &pdata->hw_if;
|
|
|
|
struct xgbe_desc_if *desc_if = &pdata->desc_if;
|
|
|
|
struct xgbe_ring *ring = channel->rx_ring;
|
|
|
|
struct xgbe_ring_data *rdata;
|
|
|
|
|
|
|
|
while (ring->dirty != ring->cur) {
|
|
|
|
rdata = XGBE_GET_DESC_DATA(ring, ring->dirty);
|
|
|
|
|
|
|
|
/* Reset rdata values */
|
|
|
|
desc_if->unmap_rdata(pdata, rdata);
|
|
|
|
|
|
|
|
if (desc_if->map_rx_buffer(pdata, ring, rdata))
|
|
|
|
break;
|
|
|
|
|
|
|
|
hw_if->rx_desc_reset(pdata, rdata, ring->dirty);
|
|
|
|
|
|
|
|
ring->dirty++;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Make sure everything is written before the register write */
|
2017-02-15 13:56:04 +00:00
|
|
|
dsb(sy);
|
2017-02-15 13:37:32 +00:00
|
|
|
|
|
|
|
/* Update the Rx Tail Pointer Register with address of
|
|
|
|
* the last cleaned entry */
|
|
|
|
rdata = XGBE_GET_DESC_DATA(ring, ring->dirty - 1);
|
|
|
|
XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO,
|
2017-02-15 13:56:04 +00:00
|
|
|
lower_32_bits(rdata->rdata_paddr));
|
2017-02-15 13:37:32 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int xgbe_tx_poll(struct xgbe_channel *channel)
|
|
|
|
{
|
|
|
|
struct xgbe_prv_data *pdata = channel->pdata;
|
|
|
|
struct xgbe_hw_if *hw_if = &pdata->hw_if;
|
|
|
|
struct xgbe_desc_if *desc_if = &pdata->desc_if;
|
|
|
|
struct xgbe_ring *ring = channel->tx_ring;
|
|
|
|
struct xgbe_ring_data *rdata;
|
|
|
|
struct xgbe_ring_desc *rdesc;
|
|
|
|
int processed = 0;
|
|
|
|
unsigned int cur;
|
|
|
|
|
|
|
|
DBGPR("-->xgbe_tx_poll\n");
|
|
|
|
|
|
|
|
/* Nothing to do if there isn't a Tx ring for this channel */
|
|
|
|
if (!ring)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
cur = ring->cur;
|
|
|
|
|
|
|
|
/* Be sure we get ring->cur before accessing descriptor data */
|
2017-02-15 13:56:04 +00:00
|
|
|
dsb(sy);
|
2017-02-15 13:37:32 +00:00
|
|
|
|
|
|
|
while ((processed < XGBE_TX_DESC_MAX_PROC) &&
|
|
|
|
(ring->dirty != cur)) {
|
|
|
|
rdata = XGBE_GET_DESC_DATA(ring, ring->dirty);
|
|
|
|
rdesc = rdata->rdesc;
|
|
|
|
|
|
|
|
if (!hw_if->tx_complete(rdesc))
|
|
|
|
break;
|
|
|
|
|
|
|
|
/* Make sure descriptor fields are read after reading the OWN
|
|
|
|
* bit */
|
2017-02-15 13:56:04 +00:00
|
|
|
dsb(sy);
|
2017-02-15 13:37:32 +00:00
|
|
|
|
|
|
|
/* Free the SKB and reset the descriptor for re-use */
|
|
|
|
desc_if->unmap_rdata(pdata, rdata);
|
|
|
|
hw_if->tx_desc_reset(rdata);
|
|
|
|
|
|
|
|
processed++;
|
|
|
|
ring->dirty++;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!processed)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
DBGPR("<--xgbe_tx_poll: processed=%d\n", processed);
|
|
|
|
|
|
|
|
return processed;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int xgbe_rx_poll(struct xgbe_channel *channel, int budget)
|
|
|
|
{
|
|
|
|
struct xgbe_prv_data *pdata = channel->pdata;
|
|
|
|
struct xgbe_hw_if *hw_if = &pdata->hw_if;
|
|
|
|
struct xgbe_ring *ring = channel->rx_ring;
|
|
|
|
struct xgbe_ring_data *rdata;
|
|
|
|
struct xgbe_packet_data *packet;
|
2017-02-15 13:56:04 +00:00
|
|
|
struct ifnet *ifp = pdata->netdev;
|
|
|
|
struct mbuf *m;
|
|
|
|
unsigned int incomplete, context_next, context;
|
2017-02-15 13:37:32 +00:00
|
|
|
unsigned int received = 0;
|
|
|
|
int packet_count = 0;
|
|
|
|
|
|
|
|
DBGPR("-->xgbe_rx_poll: budget=%d\n", budget);
|
|
|
|
|
|
|
|
/* Nothing to do if there isn't a Rx ring for this channel */
|
|
|
|
if (!ring)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
incomplete = 0;
|
|
|
|
context_next = 0;
|
|
|
|
|
|
|
|
rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
|
|
|
|
packet = &ring->packet_data;
|
|
|
|
while (packet_count < budget) {
|
|
|
|
DBGPR(" cur = %d\n", ring->cur);
|
|
|
|
|
|
|
|
read_again:
|
|
|
|
rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
|
|
|
|
|
|
|
|
if (xgbe_rx_dirty_desc(ring) > (XGBE_RX_DESC_CNT >> 3))
|
|
|
|
xgbe_rx_refresh(channel);
|
|
|
|
|
|
|
|
if (hw_if->dev_read(channel))
|
|
|
|
break;
|
|
|
|
|
2017-02-15 13:56:04 +00:00
|
|
|
m = rdata->mb;
|
|
|
|
|
2017-02-15 13:37:32 +00:00
|
|
|
received++;
|
|
|
|
ring->cur++;
|
|
|
|
|
|
|
|
incomplete = XGMAC_GET_BITS(packet->attributes,
|
|
|
|
RX_PACKET_ATTRIBUTES,
|
|
|
|
INCOMPLETE);
|
|
|
|
context_next = XGMAC_GET_BITS(packet->attributes,
|
|
|
|
RX_PACKET_ATTRIBUTES,
|
|
|
|
CONTEXT_NEXT);
|
|
|
|
context = XGMAC_GET_BITS(packet->attributes,
|
|
|
|
RX_PACKET_ATTRIBUTES,
|
|
|
|
CONTEXT);
|
|
|
|
|
|
|
|
/* Earlier error, just drain the remaining data */
|
2017-02-15 13:56:04 +00:00
|
|
|
if (incomplete || context_next) {
|
2017-02-15 13:37:32 +00:00
|
|
|
goto read_again;
|
|
|
|
}
|
|
|
|
|
2017-02-15 13:56:04 +00:00
|
|
|
if (packet->errors) {
|
|
|
|
rdata->mbuf_free = 1;
|
2017-02-15 13:37:32 +00:00
|
|
|
goto next_packet;
|
|
|
|
}
|
2017-02-15 13:56:04 +00:00
|
|
|
rdata->mb = NULL;
|
2017-02-15 13:37:32 +00:00
|
|
|
|
2017-02-15 13:56:04 +00:00
|
|
|
m->m_pkthdr.len = rdata->rx.hdr_len + rdata->rx.len;
|
|
|
|
if (rdata->rx.hdr_len != 0) {
|
|
|
|
m->m_len = rdata->rx.hdr_len;
|
|
|
|
m->m_next->m_len = rdata->rx.len;
|
|
|
|
} else {
|
|
|
|
m->m_len = rdata->rx.len;
|
|
|
|
m_freem(m->m_next);
|
|
|
|
m->m_next = NULL;
|
2017-02-15 13:37:32 +00:00
|
|
|
}
|
2017-02-15 13:56:04 +00:00
|
|
|
if_setrcvif(m, ifp);
|
|
|
|
if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
|
2017-02-15 13:37:32 +00:00
|
|
|
|
2017-02-15 13:56:04 +00:00
|
|
|
ifp->if_input(ifp, m);
|
2017-02-15 13:37:32 +00:00
|
|
|
|
|
|
|
next_packet:
|
|
|
|
packet_count++;
|
|
|
|
}
|
|
|
|
|
|
|
|
DBGPR("<--xgbe_rx_poll: packet_count = %d\n", packet_count);
|
|
|
|
|
|
|
|
return packet_count;
|
|
|
|
}
|
|
|
|
|
2017-02-15 13:56:04 +00:00
|
|
|
static int xgbe_one_poll(struct xgbe_channel *channel, int budget)
|
2017-02-15 13:37:32 +00:00
|
|
|
{
|
|
|
|
int processed = 0;
|
|
|
|
|
|
|
|
DBGPR("-->xgbe_one_poll: budget=%d\n", budget);
|
|
|
|
|
|
|
|
/* Cleanup Tx ring first */
|
|
|
|
xgbe_tx_poll(channel);
|
|
|
|
|
|
|
|
/* Process Rx ring next */
|
|
|
|
processed = xgbe_rx_poll(channel, budget);
|
|
|
|
|
|
|
|
DBGPR("<--xgbe_one_poll: received = %d\n", processed);
|
|
|
|
|
|
|
|
return processed;
|
|
|
|
}
|
|
|
|
|
2017-02-15 13:56:04 +00:00
|
|
|
static int xgbe_all_poll(struct xgbe_prv_data *pdata, int budget)
|
2017-02-15 13:37:32 +00:00
|
|
|
{
|
|
|
|
struct xgbe_channel *channel;
|
|
|
|
int ring_budget;
|
|
|
|
int processed, last_processed;
|
|
|
|
unsigned int i;
|
|
|
|
|
|
|
|
DBGPR("-->xgbe_all_poll: budget=%d\n", budget);
|
|
|
|
|
|
|
|
processed = 0;
|
|
|
|
ring_budget = budget / pdata->rx_ring_count;
|
|
|
|
do {
|
|
|
|
last_processed = processed;
|
|
|
|
|
|
|
|
channel = pdata->channel;
|
|
|
|
for (i = 0; i < pdata->channel_count; i++, channel++) {
|
|
|
|
/* Cleanup Tx ring first */
|
|
|
|
xgbe_tx_poll(channel);
|
|
|
|
|
|
|
|
/* Process Rx ring next */
|
|
|
|
if (ring_budget > (budget - processed))
|
|
|
|
ring_budget = budget - processed;
|
|
|
|
processed += xgbe_rx_poll(channel, ring_budget);
|
|
|
|
}
|
|
|
|
} while ((processed < budget) && (processed != last_processed));
|
|
|
|
|
|
|
|
DBGPR("<--xgbe_all_poll: received = %d\n", processed);
|
|
|
|
|
|
|
|
return processed;
|
|
|
|
}
|