2005-01-06 01:43:34 +00:00
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/*-
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2002-02-27 05:09:14 +00:00
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* Copyright (c) 1997, Stefan Esser <se@freebsd.org>
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* Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
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* Copyright (c) 2000, BSDi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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#ifndef _PCI_PRIVATE_H_
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2006-12-14 16:53:48 +00:00
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#define _PCI_PRIVATE_H_
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2002-02-27 05:09:14 +00:00
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/*
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* Export definitions of the pci bus so that we can more easily share
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2006-01-20 22:00:50 +00:00
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* it with "subclass" busses.
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2002-02-27 05:09:14 +00:00
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*/
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2006-01-20 22:00:50 +00:00
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DECLARE_CLASS(pci_driver);
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2002-08-26 15:23:52 +00:00
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2012-03-02 20:38:04 +00:00
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struct pci_softc {
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bus_dma_tag_t sc_dma_tag;
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2014-02-12 04:30:37 +00:00
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#ifdef PCI_RES_BUS
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struct resource *sc_bus;
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#endif
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2012-03-02 20:38:04 +00:00
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};
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2010-08-17 15:44:52 +00:00
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extern int pci_do_power_resume;
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2010-10-20 16:47:09 +00:00
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extern int pci_do_power_suspend;
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2010-08-17 15:44:52 +00:00
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2007-09-30 11:05:18 +00:00
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void pci_add_children(device_t dev, int domain, int busno,
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size_t dinfo_size);
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2002-08-26 15:23:52 +00:00
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void pci_add_child(device_t bus, struct pci_devinfo *dinfo);
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2015-03-01 00:40:09 +00:00
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device_t pci_add_iov_child(device_t bus, device_t pf, size_t dinfo_size,
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uint16_t rid, uint16_t vid, uint16_t did);
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2005-12-30 19:28:26 +00:00
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void pci_add_resources(device_t bus, device_t dev, int force,
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uint32_t prefetchmask);
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2012-03-02 20:38:04 +00:00
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int pci_attach_common(device_t dev);
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2010-01-05 20:42:25 +00:00
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void pci_delete_child(device_t dev, device_t child);
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2004-04-09 15:44:34 +00:00
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void pci_driver_added(device_t dev, driver_t *driver);
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2002-02-27 05:09:14 +00:00
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int pci_print_child(device_t dev, device_t child);
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void pci_probe_nomatch(device_t dev, device_t child);
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int pci_read_ivar(device_t dev, device_t child, int which,
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uintptr_t *result);
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int pci_write_ivar(device_t dev, device_t child, int which,
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uintptr_t value);
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2007-05-02 17:50:36 +00:00
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int pci_setup_intr(device_t dev, device_t child,
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struct resource *irq, int flags, driver_filter_t *filter,
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driver_intr_t *intr, void *arg, void **cookiep);
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int pci_teardown_intr(device_t dev, device_t child,
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struct resource *irq, void *cookie);
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2006-10-09 16:15:56 +00:00
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int pci_get_vpd_ident_method(device_t dev, device_t child,
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const char **identptr);
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int pci_get_vpd_readonly_method(device_t dev, device_t child,
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const char *kw, const char **vptr);
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2002-02-27 05:09:14 +00:00
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int pci_set_powerstate_method(device_t dev, device_t child,
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int state);
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int pci_get_powerstate_method(device_t dev, device_t child);
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2003-08-22 03:11:53 +00:00
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uint32_t pci_read_config_method(device_t dev, device_t child,
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2002-02-27 05:09:14 +00:00
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int reg, int width);
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void pci_write_config_method(device_t dev, device_t child,
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2003-08-22 03:11:53 +00:00
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int reg, uint32_t val, int width);
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2003-04-16 03:15:08 +00:00
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int pci_enable_busmaster_method(device_t dev, device_t child);
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int pci_disable_busmaster_method(device_t dev, device_t child);
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int pci_enable_io_method(device_t dev, device_t child, int space);
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int pci_disable_io_method(device_t dev, device_t child, int space);
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2012-03-03 18:08:57 +00:00
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int pci_find_cap_method(device_t dev, device_t child,
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int capability, int *capreg);
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2005-12-20 19:57:47 +00:00
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int pci_find_extcap_method(device_t dev, device_t child,
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2012-03-03 18:08:57 +00:00
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int capability, int *capreg);
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int pci_find_htcap_method(device_t dev, device_t child,
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2005-12-20 19:57:47 +00:00
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int capability, int *capreg);
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First cut at MI support for PCI Message Signalled Interrupts (MSI):
- Add 3 new functions to the pci_if interface along with suitable wrappers
to provide the device driver visible API:
- pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count'
here is an in and out parameter. The driver stores the desired number
of messages in '*count' before calling the function. On success,
'*count' holds the number of messages allocated to the device. Also on
success, the driver can access the messages as SYS_RES_IRQ resources
starting at rid 1. Note that the legacy INTx interrupt resource will
not be available when using MSI. Note that this function will allocate
either MSI or MSI-X messages depending on the devices capabilities and
the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note
that the driver should activate the memory resource that holds the
MSI-X table and pending bit array (PBA) before calling this function
if the device supports MSI-X.
- pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function
releases the messages allocated for this device. All of the
SYS_RES_IRQ resources need to be released for this function to succeed.
- pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns
the maximum number of MSI or MSI-X messages supported by this device.
MSI-X is preferred if present, but this function will honor the
'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function
should return the largest value that pci_alloc_msi() can return
(assuming the MD code is able to allocate sufficient backing resources
for all of the messages).
- Add default implementations for these 3 methods to the pci_driver generic
PCI bus driver. (The various other PCI bus drivers such as for ACPI and
OFW will inherit these default implementations.) This default
implementation depends on 4 new pcib_if methods that bubble up through
the PCI bridges to the MD code to allocate IRQ values and perform any
needed MD setup code needed:
- PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages.
- PCIB_RELEASE_MSI() releases a group of MSI messages.
- PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message.
- PCIB_RELEASE_MSIX() releases a single MSI-X message.
- Add default implementations for these 4 methods that just pass the
request up to the parent bus's parent bridge driver and use the
default implementation in the various MI PCI bridge drivers.
- Add MI functions for use by MD code when managing MSI and MSI-X
interrupts:
- pci_enable_msi(dev, address, data) programs the MSI capability address
and data registers for a group of MSI messages
- pci_enable_msix(dev, index, address, data) initializes a single MSI-X
message in the MSI-X table
- pci_mask_msix(dev, index) masks a single MSI-X message
- pci_unmask_msix(dev, index) unmasks a single MSI-X message
- pci_pending_msix(dev, index) returns true if the specified MSI-X
message is currently pending
- Save the MSI capability address and data registers in the pci_cfgreg
block in a PCI devices ivars and restore the values when a device is
resumed. Note that the MSI-X table is not currently restored during
resume.
- Add constants for MSI-X register offsets and fields.
- Record interesting data about any MSI-X capability blocks we come
across in the pci_cfgreg block in the ivars for PCI devices.
Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X)
Reviewed by: scottl, grehan, jfv
MFC after: 2 months
2006-11-13 21:47:30 +00:00
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int pci_alloc_msi_method(device_t dev, device_t child, int *count);
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Expand the MSI/MSI-X API to address some deficiencies in the MSI-X support.
- First off, device drivers really do need to know if they are allocating
MSI or MSI-X messages. MSI requires allocating powerof2() messages for
example where MSI-X does not. To address this, split out the MSI-X
support from pci_msi_count() and pci_alloc_msi() into new driver-visible
functions pci_msix_count() and pci_alloc_msix(). As a result,
pci_msi_count() now just returns a count of the max supported MSI
messages for the device, and pci_alloc_msi() only tries to allocate MSI
messages. To get a count of the max supported MSI-X messages, use
pci_msix_count(). To allocate MSI-X messages, use pci_alloc_msix().
pci_release_msi() still handles both MSI and MSI-X messages, however.
As a result of this change, drivers using the existing API will only
use MSI messages and will no longer try to use MSI-X messages.
- Because MSI-X allows for each message to have its own data and address
values (and thus does not require all of the messages to have their
MD vectors allocated as a group), some devices allow for "sparse" use
of MSI-X message slots. For example, if a device supports 8 messages
but the OS is only able to allocate 2 messages, the device may make the
best use of 2 IRQs if it enables the messages at slots 1 and 4 rather
than default of using the first N slots (or indicies) at 1 and 2. To
support this, add a new pci_remap_msix() function that a driver may call
after a successful pci_alloc_msix() (but before allocating any of the
SYS_RES_IRQ resources) to allow the allocated IRQ resources to be
assigned to different message indices. For example, from the earlier
example, after pci_alloc_msix() returned a value of 2, the driver would
call pci_remap_msix() passing in array of integers { 1, 4 } as the
new message indices to use. The rid's for the SYS_RES_IRQ resources
will always match the message indices. Thus, after the call to
pci_remap_msix() the driver would be able to access the first message
in slot 1 at SYS_RES_IRQ rid 1, and the second message at slot 4 at
SYS_RES_IRQ rid 4. Note that the message slots/indices are 1-based
rather than 0-based so that they will always correspond to the rid
values (SYS_RES_IRQ rid 0 is reserved for the legacy INTx interrupt).
To support this API, a new PCIB_REMAP_MSIX() method was added to the
pcib interface to change the message index for a single IRQ.
Tested by: scottl
2007-01-22 21:48:44 +00:00
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int pci_alloc_msix_method(device_t dev, device_t child, int *count);
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2014-08-20 14:57:20 +00:00
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void pci_enable_msi_method(device_t dev, device_t child,
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uint64_t address, uint16_t data);
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void pci_enable_msix_method(device_t dev, device_t child,
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u_int index, uint64_t address, uint32_t data);
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void pci_disable_msi_method(device_t dev, device_t child);
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Expand the MSI/MSI-X API to address some deficiencies in the MSI-X support.
- First off, device drivers really do need to know if they are allocating
MSI or MSI-X messages. MSI requires allocating powerof2() messages for
example where MSI-X does not. To address this, split out the MSI-X
support from pci_msi_count() and pci_alloc_msi() into new driver-visible
functions pci_msix_count() and pci_alloc_msix(). As a result,
pci_msi_count() now just returns a count of the max supported MSI
messages for the device, and pci_alloc_msi() only tries to allocate MSI
messages. To get a count of the max supported MSI-X messages, use
pci_msix_count(). To allocate MSI-X messages, use pci_alloc_msix().
pci_release_msi() still handles both MSI and MSI-X messages, however.
As a result of this change, drivers using the existing API will only
use MSI messages and will no longer try to use MSI-X messages.
- Because MSI-X allows for each message to have its own data and address
values (and thus does not require all of the messages to have their
MD vectors allocated as a group), some devices allow for "sparse" use
of MSI-X message slots. For example, if a device supports 8 messages
but the OS is only able to allocate 2 messages, the device may make the
best use of 2 IRQs if it enables the messages at slots 1 and 4 rather
than default of using the first N slots (or indicies) at 1 and 2. To
support this, add a new pci_remap_msix() function that a driver may call
after a successful pci_alloc_msix() (but before allocating any of the
SYS_RES_IRQ resources) to allow the allocated IRQ resources to be
assigned to different message indices. For example, from the earlier
example, after pci_alloc_msix() returned a value of 2, the driver would
call pci_remap_msix() passing in array of integers { 1, 4 } as the
new message indices to use. The rid's for the SYS_RES_IRQ resources
will always match the message indices. Thus, after the call to
pci_remap_msix() the driver would be able to access the first message
in slot 1 at SYS_RES_IRQ rid 1, and the second message at slot 4 at
SYS_RES_IRQ rid 4. Note that the message slots/indices are 1-based
rather than 0-based so that they will always correspond to the rid
values (SYS_RES_IRQ rid 0 is reserved for the legacy INTx interrupt).
To support this API, a new PCIB_REMAP_MSIX() method was added to the
pcib interface to change the message index for a single IRQ.
Tested by: scottl
2007-01-22 21:48:44 +00:00
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int pci_remap_msix_method(device_t dev, device_t child,
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2007-05-02 17:50:36 +00:00
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int count, const u_int *vectors);
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First cut at MI support for PCI Message Signalled Interrupts (MSI):
- Add 3 new functions to the pci_if interface along with suitable wrappers
to provide the device driver visible API:
- pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI(). '*count'
here is an in and out parameter. The driver stores the desired number
of messages in '*count' before calling the function. On success,
'*count' holds the number of messages allocated to the device. Also on
success, the driver can access the messages as SYS_RES_IRQ resources
starting at rid 1. Note that the legacy INTx interrupt resource will
not be available when using MSI. Note that this function will allocate
either MSI or MSI-X messages depending on the devices capabilities and
the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. Also note
that the driver should activate the memory resource that holds the
MSI-X table and pending bit array (PBA) before calling this function
if the device supports MSI-X.
- pci_release_msi(dev) backed by PCI_RELEASE_MSI(). This function
releases the messages allocated for this device. All of the
SYS_RES_IRQ resources need to be released for this function to succeed.
- pci_msi_count(dev) backed by PCI_MSI_COUNT(). This function returns
the maximum number of MSI or MSI-X messages supported by this device.
MSI-X is preferred if present, but this function will honor the
'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables. This function
should return the largest value that pci_alloc_msi() can return
(assuming the MD code is able to allocate sufficient backing resources
for all of the messages).
- Add default implementations for these 3 methods to the pci_driver generic
PCI bus driver. (The various other PCI bus drivers such as for ACPI and
OFW will inherit these default implementations.) This default
implementation depends on 4 new pcib_if methods that bubble up through
the PCI bridges to the MD code to allocate IRQ values and perform any
needed MD setup code needed:
- PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages.
- PCIB_RELEASE_MSI() releases a group of MSI messages.
- PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message.
- PCIB_RELEASE_MSIX() releases a single MSI-X message.
- Add default implementations for these 4 methods that just pass the
request up to the parent bus's parent bridge driver and use the
default implementation in the various MI PCI bridge drivers.
- Add MI functions for use by MD code when managing MSI and MSI-X
interrupts:
- pci_enable_msi(dev, address, data) programs the MSI capability address
and data registers for a group of MSI messages
- pci_enable_msix(dev, index, address, data) initializes a single MSI-X
message in the MSI-X table
- pci_mask_msix(dev, index) masks a single MSI-X message
- pci_unmask_msix(dev, index) unmasks a single MSI-X message
- pci_pending_msix(dev, index) returns true if the specified MSI-X
message is currently pending
- Save the MSI capability address and data registers in the pci_cfgreg
block in a PCI devices ivars and restore the values when a device is
resumed. Note that the MSI-X table is not currently restored during
resume.
- Add constants for MSI-X register offsets and fields.
- Record interesting data about any MSI-X capability blocks we come
across in the pci_cfgreg block in the ivars for PCI devices.
Tested on: em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X)
Reviewed by: scottl, grehan, jfv
MFC after: 2 months
2006-11-13 21:47:30 +00:00
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int pci_release_msi_method(device_t dev, device_t child);
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int pci_msi_count_method(device_t dev, device_t child);
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Expand the MSI/MSI-X API to address some deficiencies in the MSI-X support.
- First off, device drivers really do need to know if they are allocating
MSI or MSI-X messages. MSI requires allocating powerof2() messages for
example where MSI-X does not. To address this, split out the MSI-X
support from pci_msi_count() and pci_alloc_msi() into new driver-visible
functions pci_msix_count() and pci_alloc_msix(). As a result,
pci_msi_count() now just returns a count of the max supported MSI
messages for the device, and pci_alloc_msi() only tries to allocate MSI
messages. To get a count of the max supported MSI-X messages, use
pci_msix_count(). To allocate MSI-X messages, use pci_alloc_msix().
pci_release_msi() still handles both MSI and MSI-X messages, however.
As a result of this change, drivers using the existing API will only
use MSI messages and will no longer try to use MSI-X messages.
- Because MSI-X allows for each message to have its own data and address
values (and thus does not require all of the messages to have their
MD vectors allocated as a group), some devices allow for "sparse" use
of MSI-X message slots. For example, if a device supports 8 messages
but the OS is only able to allocate 2 messages, the device may make the
best use of 2 IRQs if it enables the messages at slots 1 and 4 rather
than default of using the first N slots (or indicies) at 1 and 2. To
support this, add a new pci_remap_msix() function that a driver may call
after a successful pci_alloc_msix() (but before allocating any of the
SYS_RES_IRQ resources) to allow the allocated IRQ resources to be
assigned to different message indices. For example, from the earlier
example, after pci_alloc_msix() returned a value of 2, the driver would
call pci_remap_msix() passing in array of integers { 1, 4 } as the
new message indices to use. The rid's for the SYS_RES_IRQ resources
will always match the message indices. Thus, after the call to
pci_remap_msix() the driver would be able to access the first message
in slot 1 at SYS_RES_IRQ rid 1, and the second message at slot 4 at
SYS_RES_IRQ rid 4. Note that the message slots/indices are 1-based
rather than 0-based so that they will always correspond to the rid
values (SYS_RES_IRQ rid 0 is reserved for the legacy INTx interrupt).
To support this API, a new PCIB_REMAP_MSIX() method was added to the
pcib interface to change the message index for a single IRQ.
Tested by: scottl
2007-01-22 21:48:44 +00:00
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int pci_msix_count_method(device_t dev, device_t child);
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2002-02-27 05:09:14 +00:00
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struct resource *pci_alloc_resource(device_t dev, device_t child,
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int type, int *rid, u_long start, u_long end, u_long count,
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u_int flags);
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2013-07-18 15:17:11 +00:00
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int pci_release_resource(device_t dev, device_t child, int type,
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int rid, struct resource *r);
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2009-03-03 16:38:59 +00:00
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int pci_activate_resource(device_t dev, device_t child, int type,
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int rid, struct resource *r);
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2009-12-30 20:47:14 +00:00
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int pci_deactivate_resource(device_t dev, device_t child, int type,
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int rid, struct resource *r);
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2002-02-27 05:09:14 +00:00
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void pci_delete_resource(device_t dev, device_t child,
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int type, int rid);
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struct resource_list *pci_get_resource_list (device_t dev, device_t child);
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2007-09-30 11:05:18 +00:00
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struct pci_devinfo *pci_read_device(device_t pcib, int d, int b, int s, int f,
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2002-03-13 16:32:11 +00:00
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size_t size);
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2002-02-27 05:09:14 +00:00
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void pci_print_verbose(struct pci_devinfo *dinfo);
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int pci_freecfg(struct pci_devinfo *dinfo);
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2013-06-27 20:21:54 +00:00
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void pci_child_detached(device_t dev, device_t child);
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2003-02-17 21:20:35 +00:00
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int pci_child_location_str_method(device_t cbdev, device_t child,
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char *buf, size_t buflen);
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int pci_child_pnpinfo_str_method(device_t cbdev, device_t child,
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char *buf, size_t buflen);
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2003-07-01 14:08:33 +00:00
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int pci_assign_interrupt_method(device_t dev, device_t child);
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2003-09-17 08:32:44 +00:00
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int pci_resume(device_t dev);
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2014-09-23 02:56:40 +00:00
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int pci_resume_child(device_t dev, device_t child);
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int pci_suspend_child(device_t dev, device_t child);
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2013-10-24 20:29:29 +00:00
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bus_dma_tag_t pci_get_dma_tag(device_t bus, device_t dev);
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2014-08-22 15:05:51 +00:00
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void pci_child_added_method(device_t dev, device_t child);
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2007-05-16 18:41:42 +00:00
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/** Restore the config register state. The state must be previously
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* saved with pci_cfg_save. However, the pci bus driver takes care of
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* that. This function will also return the device to PCI_POWERSTATE_D0
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* if it is currently in a lower power mode.
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*/
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2005-02-28 01:14:15 +00:00
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void pci_cfg_restore(device_t, struct pci_devinfo *);
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2007-05-16 18:41:42 +00:00
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/** Save the config register state. Optionally set the power state to D3
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* if the third argument is non-zero.
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*/
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2005-02-28 01:14:15 +00:00
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void pci_cfg_save(device_t, struct pci_devinfo *, int);
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2006-11-07 18:55:51 +00:00
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2015-03-01 00:39:33 +00:00
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int pci_mapsize(uint64_t testval);
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void pci_read_bar(device_t dev, int reg, pci_addr_t *mapp,
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pci_addr_t *testvalp, int *bar64);
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struct pci_map *pci_add_bar(device_t dev, int reg, pci_addr_t value,
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pci_addr_t size);
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struct resource *pci_alloc_multi_resource(device_t dev, device_t child,
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int type, int *rid, u_long start, u_long end, u_long count,
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u_long num, u_int flags);
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2015-03-01 00:40:42 +00:00
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int pci_iov_attach_method(device_t bus, device_t dev,
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struct nvlist *pf_schema, struct nvlist *vf_schema);
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2015-03-01 00:40:09 +00:00
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int pci_iov_detach_method(device_t bus, device_t dev);
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device_t pci_create_iov_child_method(device_t bus, device_t pf,
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uint16_t rid, uint16_t vid, uint16_t did);
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2015-03-01 00:40:26 +00:00
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struct resource *pci_vf_alloc_mem_resource(device_t dev, device_t child,
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int *rid, u_long start, u_long end, u_long count,
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u_int flags);
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int pci_vf_release_mem_resource(device_t dev, device_t child,
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int rid, struct resource *r);
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2002-02-27 05:09:14 +00:00
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#endif /* _PCI_PRIVATE_H_ */
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