2009-10-15 21:14:42 +00:00
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/*-
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2009-10-29 15:55:25 +00:00
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* Copyright (c) 2006-2009 RMI Corporation
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2009-10-15 21:14:42 +00:00
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* Copyright (c) 2002-2004 Juli Mallett <jmallett@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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2009-11-05 18:14:25 +00:00
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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2009-12-21 11:29:30 +00:00
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#include "opt_ddb.h"
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2009-10-15 21:14:42 +00:00
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/rtprio.h>
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#include <sys/systm.h>
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#include <sys/interrupt.h>
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#include <sys/kernel.h>
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#include <sys/kthread.h>
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#include <sys/ktr.h>
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#include <sys/limits.h>
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#include <sys/lock.h>
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#include <sys/malloc.h>
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#include <sys/mutex.h>
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#include <sys/proc.h>
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#include <sys/random.h>
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#include <sys/resourcevar.h>
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#include <sys/sched.h>
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#include <sys/sysctl.h>
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#include <sys/unistd.h>
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2009-10-29 21:14:10 +00:00
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#include <sys/cons.h> /* cinit() */
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2009-12-21 11:29:30 +00:00
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#include <sys/kdb.h>
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2009-10-15 21:14:42 +00:00
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#include <sys/reboot.h>
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#include <sys/queue.h>
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#include <sys/smp.h>
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#include <sys/timetc.h>
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#include <vm/vm.h>
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#include <vm/vm_page.h>
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#include <machine/cpu.h>
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#include <machine/cpufunc.h>
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#include <machine/cpuinfo.h>
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#include <machine/cpuregs.h>
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#include <machine/frame.h>
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#include <machine/hwfunc.h>
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#include <machine/md_var.h>
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#include <machine/asm.h>
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#include <machine/pmap.h>
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#include <machine/trap.h>
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#include <machine/clock.h>
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#include <machine/fls64.h>
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#include <machine/intr_machdep.h>
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#include <machine/smp.h>
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2009-10-29 21:30:21 +00:00
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#include <mips/rmi/rmi_mips_exts.h>
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2009-10-15 21:14:42 +00:00
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2009-10-29 15:55:25 +00:00
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#include <mips/rmi/iomap.h>
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#include <mips/rmi/clock.h>
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#include <mips/rmi/msgring.h>
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#include <mips/rmi/xlrconfig.h>
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#include <mips/rmi/interrupt.h>
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#include <mips/rmi/pic.h>
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2009-10-15 21:14:42 +00:00
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#ifdef XLR_PERFMON
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2009-10-29 15:55:25 +00:00
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#include <mips/rmi/perfmon.h>
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2009-10-15 21:14:42 +00:00
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#endif
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void platform_prep_smp_launch(void);
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unsigned long xlr_io_base = (unsigned long)(DEFAULT_XLR_IO_BASE);
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2009-10-29 21:14:10 +00:00
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/* 4KB static data aread to keep a copy of the bootload env until
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2009-10-15 21:14:42 +00:00
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the dynamic kenv is setup */
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char boot1_env[4096];
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extern unsigned long _gp;
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2009-11-05 18:14:25 +00:00
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int rmi_spin_mutex_safe=0;
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2009-10-15 21:14:42 +00:00
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/*
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* Parameters from boot loader
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*/
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2009-10-29 21:14:10 +00:00
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struct boot1_info xlr_boot1_info;
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struct xlr_loader_info xlr_loader_info; /* FIXME : Unused */
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int xlr_run_mode;
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int xlr_argc;
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char **xlr_argv, **xlr_envp;
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uint64_t cpu_mask_info;
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uint32_t xlr_online_cpumask;
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2009-10-15 21:14:42 +00:00
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#ifdef SMP
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static unsigned long xlr_secondary_gp[MAXCPU];
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static unsigned long xlr_secondary_sp[MAXCPU];
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2009-10-29 21:14:10 +00:00
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2009-10-15 21:14:42 +00:00
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#endif
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extern int mips_cpu_online_mask;
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extern int mips_cpu_logical_mask;
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2009-10-29 15:55:25 +00:00
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uint32_t cpu_ltop_map[MAXCPU];
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uint32_t cpu_ptol_map[MAXCPU];
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2009-10-29 21:14:10 +00:00
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uint32_t xlr_core_cpu_mask = 0x1; /* Core 0 thread 0 is always there */
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2009-10-15 21:14:42 +00:00
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void
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platform_reset(void)
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{
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/* FIXME : use proper define */
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2009-10-29 21:14:10 +00:00
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u_int32_t *mmio = (u_int32_t *) 0xbef18000;
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2009-10-15 21:14:42 +00:00
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printf("Rebooting the system now\n");
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mmio[8] = 0x1;
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}
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2009-10-29 21:14:10 +00:00
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void
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platform_secondary_init(void)
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2009-10-15 21:14:42 +00:00
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{
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#ifdef SMP
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xlr_msgring_cpu_init();
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/* Setup interrupts for secondary CPUs here */
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2009-10-29 15:55:25 +00:00
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mips_mask_hard_irq(IPI_SMP_CALL_FUNCTION);
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mips_mask_hard_irq(IPI_STOP);
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mips_mask_hard_irq(IPI_RENDEZVOUS);
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mips_mask_hard_irq(IPI_AST);
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mips_mask_hard_irq(IRQ_TIMER);
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2009-10-15 21:14:42 +00:00
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#ifdef XLR_PERFMON
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2009-10-29 15:55:25 +00:00
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mips_mask_hard_irq(IPI_PERFMON);
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2009-10-15 21:14:42 +00:00
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#endif
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return;
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#endif
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}
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2009-10-29 21:14:10 +00:00
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int xlr_asid_pcpu = 256; /* This the default */
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int xlr_shtlb_enabled = 0;
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2009-10-15 21:14:42 +00:00
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/* This function sets up the number of tlb entries available
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to the kernel based on the number of threads brought up.
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The ASID range also gets divided similarly.
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THE NUMBER OF THREADS BROUGHT UP IN EACH CORE MUST BE THE SAME
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NOTE: This function will mark all 64TLB entries as available
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to the threads brought up in the core. If kernel is brought with say mask
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0x33333333, no TLBs will be available to the threads in each core.
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*/
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2009-10-29 21:14:10 +00:00
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static void
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setup_tlb_resource(void)
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2009-10-15 21:14:42 +00:00
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{
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int mmu_setup;
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int value = 0;
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uint32_t cpu_map = xlr_boot1_info.cpu_online_map;
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uint32_t thr_mask = cpu_map >> (xlr_cpu_id() << 2);
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uint8_t core0 = xlr_boot1_info.cpu_online_map & 0xf;
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uint8_t core_thr_mask;
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2009-10-29 21:14:10 +00:00
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int i = 0, count = 0;
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2009-10-15 21:14:42 +00:00
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/* If CPU0 did not enable shared TLB, other cores need to follow */
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2009-10-29 21:14:10 +00:00
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if ((xlr_cpu_id() != 0) && (xlr_shtlb_enabled == 0))
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2009-10-15 21:14:42 +00:00
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return;
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/* First check if each core is brought up with the same mask */
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2009-10-29 21:14:10 +00:00
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for (i = 1; i < 8; i++) {
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2009-10-15 21:14:42 +00:00
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core_thr_mask = cpu_map >> (i << 2);
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core_thr_mask &= 0xf;
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2009-10-29 21:14:10 +00:00
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if (core_thr_mask && core_thr_mask != core0) {
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2009-10-15 21:14:42 +00:00
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printf
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2009-10-29 21:14:10 +00:00
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("Each core must be brought with same cpu mask\n");
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2009-10-15 21:14:42 +00:00
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printf("Cannot enabled shared TLB. ");
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printf("Falling back to split TLB mode\n");
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return;
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}
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}
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xlr_shtlb_enabled = 1;
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2009-10-29 21:14:10 +00:00
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for (i = 0; i < 4; i++)
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if (thr_mask & (1 << i))
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count++;
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switch (count) {
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case 1:
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xlr_asid_pcpu = 256;
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break;
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case 2:
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xlr_asid_pcpu = 128;
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value = 0x2;
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break;
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default:
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xlr_asid_pcpu = 64;
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value = 0x3;
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break;
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2009-10-15 21:14:42 +00:00
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}
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mmu_setup = read_32bit_phnx_ctrl_reg(4, 0);
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mmu_setup = mmu_setup & ~0x06;
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mmu_setup |= (value << 1);
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/* turn on global mode */
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mmu_setup |= 0x01;
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write_32bit_phnx_ctrl_reg(4, 0, mmu_setup);
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}
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2009-10-29 21:14:10 +00:00
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2009-10-15 21:14:42 +00:00
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/*
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2009-10-29 21:14:10 +00:00
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* Platform specific register setup for CPUs
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2009-10-15 21:14:42 +00:00
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* XLR has control registers accessible with MFCR/MTCR instructions, this
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* code initialized them from the environment variable xlr.cr of form:
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* xlr.cr=reg:val[,reg:val]*, all values in hex.
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* To enable shared TLB option use xlr.shtlb=1
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*/
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2009-10-29 21:14:10 +00:00
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void
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platform_cpu_init()
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2009-10-15 21:14:42 +00:00
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{
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char *hw_env;
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char *start, *end;
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2009-10-29 21:14:10 +00:00
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uint32_t reg, val;
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2009-10-15 21:14:42 +00:00
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int thr_id = xlr_thr_id();
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2009-10-29 21:14:10 +00:00
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if (thr_id == 0) {
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2009-10-15 21:14:42 +00:00
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if ((hw_env = getenv("xlr.shtlb")) != NULL) {
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start = hw_env;
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reg = strtoul(start, &end, 16);
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2009-10-29 21:14:10 +00:00
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if (start != end && reg != 0)
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2009-10-15 21:14:42 +00:00
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setup_tlb_resource();
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} else {
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/* By default TLB entries are shared in a core */
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setup_tlb_resource();
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}
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}
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if ((hw_env = getenv("xlr.cr")) == NULL)
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return;
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start = hw_env;
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while (*start != '\0') {
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reg = strtoul(start, &end, 16);
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if (start == end) {
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printf("Invalid value in xlr.cr %s, cannot read a hex value at %d\n",
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2009-10-29 21:14:10 +00:00
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hw_env, start - hw_env);
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2009-10-15 21:14:42 +00:00
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goto err_return;
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}
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if (*end != ':') {
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printf("Invalid format in xlr.cr %s, ':' expected at pos %d\n",
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2009-10-29 21:14:10 +00:00
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hw_env, end - hw_env);
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2009-10-15 21:14:42 +00:00
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goto err_return;
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}
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2009-10-29 21:14:10 +00:00
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start = end + 1;/* step over ':' */
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2009-10-15 21:14:42 +00:00
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val = strtoul(start, &end, 16);
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if (start == end) {
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printf("Invalid value in xlr.cr %s, cannot read a hex value at pos %d\n",
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2009-10-29 21:14:10 +00:00
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hw_env, start - hw_env);
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2009-10-15 21:14:42 +00:00
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goto err_return;
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}
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if (*end != ',' && *end != '\0') {
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printf("Invalid format in xlr.cr %s, ',' expected at pos %d\n",
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2009-10-29 21:14:10 +00:00
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hw_env, end - hw_env);
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2009-10-15 21:14:42 +00:00
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goto err_return;
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}
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xlr_mtcr(reg, val);
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if (*end == ',')
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2009-10-29 21:14:10 +00:00
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start = end + 1; /* skip over ',' */
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else
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2009-10-15 21:14:42 +00:00
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start = end;
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}
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freeenv(hw_env);
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return;
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err_return:
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panic("Invalid xlr.cr setting!");
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return;
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}
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#ifdef SMP
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extern void xlr_secondary_start(unsigned long, unsigned long, unsigned long);
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2009-10-29 21:14:10 +00:00
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static void
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xlr_secondary_entry(void *data)
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2009-10-15 21:14:42 +00:00
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{
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2009-10-29 21:14:10 +00:00
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unsigned long sp, gp;
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unsigned int cpu = (xlr_cpu_id() << 2) + xlr_thr_id();
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2009-10-15 21:14:42 +00:00
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sp = xlr_secondary_sp[cpu];
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gp = xlr_secondary_gp[cpu];
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xlr_secondary_start((unsigned long)mips_secondary_wait, sp, gp);
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}
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2009-10-29 21:14:10 +00:00
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2009-10-15 21:14:42 +00:00
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#endif
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2009-10-29 21:14:10 +00:00
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static void
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xlr_set_boot_flags(void)
|
2009-10-15 21:14:42 +00:00
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{
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char *p;
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|
|
for (p = getenv("boot_flags"); p && *p != '\0'; p++) {
|
2009-10-29 21:14:10 +00:00
|
|
|
switch (*p) {
|
2009-10-15 21:14:42 +00:00
|
|
|
case 'd':
|
|
|
|
case 'D':
|
|
|
|
boothowto |= RB_KDB;
|
|
|
|
break;
|
|
|
|
case 'g':
|
|
|
|
case 'G':
|
|
|
|
boothowto |= RB_GDB;
|
|
|
|
break;
|
|
|
|
case 'v':
|
|
|
|
case 'V':
|
|
|
|
boothowto |= RB_VERBOSE;
|
|
|
|
break;
|
|
|
|
|
2009-10-29 21:14:10 +00:00
|
|
|
case 's': /* single-user (default, supported for sanity) */
|
2009-10-15 21:14:42 +00:00
|
|
|
case 'S':
|
|
|
|
boothowto |= RB_SINGLE;
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
printf("Unrecognized boot flag '%c'.\n", *p);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-10-29 21:14:10 +00:00
|
|
|
if (p)
|
2009-10-15 21:14:42 +00:00
|
|
|
freeenv(p);
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
2009-10-29 21:14:10 +00:00
|
|
|
extern uint32_t _end;
|
2009-10-29 15:55:25 +00:00
|
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
mips_init(void)
|
|
|
|
{
|
|
|
|
init_param1();
|
|
|
|
init_param2(physmem);
|
|
|
|
|
|
|
|
/* XXX: Catch 22. Something touches the tlb. */
|
2009-10-29 21:14:10 +00:00
|
|
|
|
2009-10-29 15:55:25 +00:00
|
|
|
mips_cpu_init();
|
|
|
|
pmap_bootstrap();
|
2009-10-29 21:14:10 +00:00
|
|
|
|
2009-10-29 15:55:25 +00:00
|
|
|
mips_proc0_init();
|
2009-10-29 21:14:10 +00:00
|
|
|
write_c0_register32(MIPS_COP_0_OSSCRATCH, 7, pcpup->pc_curthread);
|
2009-10-29 15:55:25 +00:00
|
|
|
|
|
|
|
mutex_init();
|
|
|
|
|
|
|
|
PMAP_LOCK_INIT(kernel_pmap);
|
|
|
|
|
|
|
|
#ifdef DDB
|
|
|
|
#ifdef SMP
|
2009-10-29 21:14:10 +00:00
|
|
|
setup_nmi();
|
|
|
|
#endif /* SMP */
|
2009-10-29 15:55:25 +00:00
|
|
|
kdb_init();
|
|
|
|
if (boothowto & RB_KDB) {
|
2009-12-21 11:29:30 +00:00
|
|
|
kdb_enter("Boot flags requested debugger", NULL);
|
2009-10-29 15:55:25 +00:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2009-10-15 21:14:42 +00:00
|
|
|
void
|
2009-10-29 15:55:25 +00:00
|
|
|
platform_start(__register_t a0 __unused,
|
2009-10-29 21:14:10 +00:00
|
|
|
__register_t a1 __unused,
|
|
|
|
__register_t a2 __unused,
|
|
|
|
__register_t a3 __unused)
|
2009-10-15 21:14:42 +00:00
|
|
|
{
|
|
|
|
vm_size_t physsz = 0;
|
2009-10-28 21:41:23 +00:00
|
|
|
int i, j;
|
2009-10-15 21:14:42 +00:00
|
|
|
struct xlr_boot1_mem_map *boot_map;
|
|
|
|
#ifdef SMP
|
|
|
|
uint32_t tmp;
|
2009-10-29 21:14:10 +00:00
|
|
|
void (*wakeup) (void *, void *, unsigned int);
|
|
|
|
|
2009-10-15 21:14:42 +00:00
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
|
|
/* XXX FIXME the code below is not 64 bit clean */
|
|
|
|
/* Save boot loader and other stuff from scratch regs */
|
|
|
|
xlr_boot1_info = *(struct boot1_info *)read_c0_register32(MIPS_COP_0_OSSCRATCH, 0);
|
2009-10-29 21:14:10 +00:00
|
|
|
cpu_mask_info = read_c0_register64(MIPS_COP_0_OSSCRATCH, 1);
|
2009-10-15 21:14:42 +00:00
|
|
|
xlr_online_cpumask = read_c0_register32(MIPS_COP_0_OSSCRATCH, 2);
|
|
|
|
xlr_run_mode = read_c0_register32(MIPS_COP_0_OSSCRATCH, 3);
|
|
|
|
xlr_argc = read_c0_register32(MIPS_COP_0_OSSCRATCH, 4);
|
|
|
|
xlr_argv = (char **)read_c0_register32(MIPS_COP_0_OSSCRATCH, 5);
|
|
|
|
xlr_envp = (char **)read_c0_register32(MIPS_COP_0_OSSCRATCH, 6);
|
|
|
|
|
|
|
|
/* TODO: Verify the magic number here */
|
2009-10-29 21:14:10 +00:00
|
|
|
/* FIXMELATER: xlr_boot1_info.magic_number */
|
2009-10-15 21:14:42 +00:00
|
|
|
|
|
|
|
/* initialize console so that we have printf */
|
2009-10-29 21:14:10 +00:00
|
|
|
boothowto |= (RB_SERIAL | RB_MULTIPLE); /* Use multiple consoles */
|
|
|
|
|
2009-10-15 21:14:42 +00:00
|
|
|
/* clockrate used by delay, so initialize it here */
|
2009-10-29 21:14:10 +00:00
|
|
|
cpu_clock = xlr_boot1_info.cpu_frequency / 1000000;
|
2009-10-29 15:55:25 +00:00
|
|
|
|
2009-10-29 21:14:10 +00:00
|
|
|
/*
|
|
|
|
* Note the time counter on CPU0 runs not at system clock speed, but
|
|
|
|
* at PIC time counter speed (which is returned by
|
|
|
|
* platform_get_frequency(). Thus we do not use
|
|
|
|
* xlr_boot1_info.cpu_frequency here.
|
2009-10-29 15:55:25 +00:00
|
|
|
*/
|
|
|
|
mips_timer_early_init(platform_get_frequency());
|
2009-11-05 18:14:25 +00:00
|
|
|
|
|
|
|
/* Init the time counter in the PIC and local putc routine*/
|
|
|
|
rmi_early_counter_init();
|
|
|
|
|
|
|
|
/* Init console please */
|
2009-10-15 21:14:42 +00:00
|
|
|
cninit();
|
2009-10-28 21:36:46 +00:00
|
|
|
init_static_kenv(boot1_env, sizeof(boot1_env));
|
2009-10-29 21:14:10 +00:00
|
|
|
printf("Environment (from %d args):\n", xlr_argc - 1);
|
2009-10-15 21:14:42 +00:00
|
|
|
if (xlr_argc == 1)
|
|
|
|
printf("\tNone\n");
|
2009-10-29 21:14:10 +00:00
|
|
|
for (i = 1; i < xlr_argc; i++) {
|
2009-10-28 21:36:46 +00:00
|
|
|
char *n;
|
|
|
|
|
2009-10-15 21:14:42 +00:00
|
|
|
printf("\t%s\n", xlr_argv[i]);
|
2009-10-28 21:36:46 +00:00
|
|
|
n = strsep(&xlr_argv[i], "=");
|
2009-10-28 21:39:33 +00:00
|
|
|
if (xlr_argv[i] == NULL)
|
2009-10-28 21:36:46 +00:00
|
|
|
setenv(n, "1");
|
|
|
|
else
|
|
|
|
setenv(n, xlr_argv[i]);
|
2009-10-15 21:14:42 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
xlr_set_boot_flags();
|
|
|
|
|
2009-10-29 21:14:10 +00:00
|
|
|
/* get physical memory info from boot loader */
|
2009-10-15 21:14:42 +00:00
|
|
|
boot_map = (struct xlr_boot1_mem_map *)
|
2009-10-29 21:14:10 +00:00
|
|
|
(unsigned long)xlr_boot1_info.psb_mem_map;
|
|
|
|
for (i = 0, j = 0; i < boot_map->num_entries; i++, j += 2) {
|
2009-10-15 21:14:42 +00:00
|
|
|
if (boot_map->physmem_map[i].type == BOOT1_MEM_RAM) {
|
|
|
|
if (j == 14) {
|
2009-10-29 21:14:10 +00:00
|
|
|
printf("*** ERROR *** memory map too large ***\n");
|
2009-10-15 21:14:42 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
if (j == 0) {
|
2009-10-29 21:14:10 +00:00
|
|
|
/* TODO FIXME */
|
2009-10-15 21:14:42 +00:00
|
|
|
/* start after kernel end */
|
|
|
|
phys_avail[0] = (vm_paddr_t)
|
2009-10-29 21:14:10 +00:00
|
|
|
MIPS_KSEG0_TO_PHYS(&_end) + 0x20000;
|
2009-10-15 21:14:42 +00:00
|
|
|
/* boot loader start */
|
|
|
|
/* HACK to Use bootloaders memory region */
|
2009-10-29 21:14:10 +00:00
|
|
|
/* TODO FIXME */
|
|
|
|
if (boot_map->physmem_map[0].size == 0x0c000000) {
|
2009-10-15 21:14:42 +00:00
|
|
|
boot_map->physmem_map[0].size = 0x0ff00000;
|
|
|
|
}
|
|
|
|
phys_avail[1] = boot_map->physmem_map[0].addr +
|
2009-10-29 21:14:10 +00:00
|
|
|
boot_map->physmem_map[0].size;
|
2009-10-15 21:14:42 +00:00
|
|
|
|
|
|
|
} else {
|
|
|
|
/*
|
|
|
|
* Can't use this code yet, because most of the fixed allocations happen from
|
|
|
|
* the biggest physical area. If we have more than 512M memory the kernel will try
|
|
|
|
* to map from the second are which is not in KSEG0 and not mapped
|
|
|
|
*/
|
|
|
|
phys_avail[j] = (vm_paddr_t)
|
2009-10-29 21:14:10 +00:00
|
|
|
boot_map->physmem_map[i].addr;
|
|
|
|
phys_avail[j + 1] = phys_avail[j] +
|
|
|
|
boot_map->physmem_map[i].size;
|
|
|
|
#if 0 /* FIXME TOD0 */
|
|
|
|
phys_avail[j] = phys_avail[j + 1] = 0;
|
2009-10-15 21:14:42 +00:00
|
|
|
#endif
|
|
|
|
}
|
|
|
|
physsz += boot_map->physmem_map[i].size;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* FIXME XLR TODO */
|
2009-10-29 21:14:10 +00:00
|
|
|
phys_avail[j] = phys_avail[j + 1] = 0;
|
2009-10-15 21:14:42 +00:00
|
|
|
realmem = physmem = btoc(physsz);
|
|
|
|
|
2009-10-29 21:14:10 +00:00
|
|
|
/* Store pcpu in scratch 5 */
|
|
|
|
write_c0_register32(MIPS_COP_0_OSSCRATCH, 5, pcpup);
|
2009-10-15 21:14:42 +00:00
|
|
|
|
|
|
|
/* Set up hz, among others. */
|
|
|
|
mips_init();
|
|
|
|
|
|
|
|
#ifdef SMP
|
2009-10-29 21:14:10 +00:00
|
|
|
/*
|
|
|
|
* If thread 0 of any core is not available then mark whole core as
|
|
|
|
* not available
|
|
|
|
*/
|
2009-10-15 21:14:42 +00:00
|
|
|
tmp = xlr_boot1_info.cpu_online_map;
|
2009-10-29 21:14:10 +00:00
|
|
|
for (i = 4; i < MAXCPU; i += 4) {
|
|
|
|
if ((tmp & (0xf << i)) && !(tmp & (0x1 << i))) {
|
|
|
|
/*
|
|
|
|
* Oopps.. thread 0 is not available. Disable whole
|
|
|
|
* core
|
|
|
|
*/
|
|
|
|
tmp = tmp & ~(0xf << i);
|
2009-10-15 21:14:42 +00:00
|
|
|
printf("WARNING: Core %d is disabled because thread 0"
|
2009-10-29 21:14:10 +00:00
|
|
|
" of this core is not enabled.\n", i / 4);
|
2009-10-15 21:14:42 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
xlr_boot1_info.cpu_online_map = tmp;
|
|
|
|
|
|
|
|
/* Wakeup Other cpus, and put them in bsd park code. */
|
2009-10-29 21:14:10 +00:00
|
|
|
for (i = 1, j = 1; i < 32; i++) {
|
2009-10-15 21:14:42 +00:00
|
|
|
/* Allocate stack for all other cpus from fbsd kseg0 memory. */
|
2009-10-29 21:14:10 +00:00
|
|
|
if ((1U << i) & xlr_boot1_info.cpu_online_map) {
|
|
|
|
xlr_secondary_gp[i] =
|
|
|
|
pmap_steal_memory(PAGE_SIZE);
|
|
|
|
if (!xlr_secondary_gp[i])
|
2009-10-15 21:14:42 +00:00
|
|
|
panic("Allocation failed for secondary cpu stacks");
|
2009-10-29 21:14:10 +00:00
|
|
|
xlr_secondary_sp[i] =
|
|
|
|
xlr_secondary_gp[i] + PAGE_SIZE - CALLFRAME_SIZ;
|
2009-10-15 21:14:42 +00:00
|
|
|
xlr_secondary_gp[i] = (unsigned long)&_gp;
|
2009-10-29 21:14:10 +00:00
|
|
|
/* Build ltop and ptol cpu map. */
|
2009-10-15 21:14:42 +00:00
|
|
|
cpu_ltop_map[j] = i;
|
|
|
|
cpu_ptol_map[i] = j;
|
2009-10-29 21:14:10 +00:00
|
|
|
if ((i & 0x3) == 0) /* store thread0 of each core */
|
|
|
|
xlr_core_cpu_mask |= (1 << j);
|
|
|
|
mips_cpu_logical_mask |= (1 << j);
|
2009-10-15 21:14:42 +00:00
|
|
|
j++;
|
|
|
|
}
|
|
|
|
}
|
2009-10-29 21:14:10 +00:00
|
|
|
|
2009-10-15 21:14:42 +00:00
|
|
|
mips_cpu_online_mask |= xlr_boot1_info.cpu_online_map;
|
2009-10-29 21:14:10 +00:00
|
|
|
wakeup = ((void (*) (void *, void *, unsigned int))
|
|
|
|
(unsigned long)(xlr_boot1_info.wakeup));
|
2009-10-15 21:14:42 +00:00
|
|
|
printf("Waking up CPUs 0x%llx.\n", xlr_boot1_info.cpu_online_map & ~(0x1U));
|
2009-10-29 21:14:10 +00:00
|
|
|
if (xlr_boot1_info.cpu_online_map & ~(0x1U))
|
|
|
|
wakeup(xlr_secondary_entry, 0,
|
|
|
|
(unsigned int)xlr_boot1_info.cpu_online_map);
|
2009-10-15 21:14:42 +00:00
|
|
|
#endif
|
|
|
|
|
2009-10-29 21:14:10 +00:00
|
|
|
/* xlr specific post initialization */
|
|
|
|
/*
|
|
|
|
* The expectation is that mutex_init() is already done in
|
|
|
|
* mips_init() XXX NOTE: We may need to move this to SMP based init
|
|
|
|
* code for each CPU, later.
|
|
|
|
*/
|
2009-11-05 18:14:25 +00:00
|
|
|
rmi_spin_mutex_safe = 1;
|
2009-10-29 15:55:25 +00:00
|
|
|
on_chip_init();
|
2009-11-05 18:14:25 +00:00
|
|
|
mips_timer_init_params(platform_get_frequency(), 0);
|
2009-11-06 12:52:51 +00:00
|
|
|
printf("Platform specific startup now completes\n");
|
2009-10-15 21:14:42 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
platform_identify(void)
|
|
|
|
{
|
2009-10-29 21:14:10 +00:00
|
|
|
printf("Board [%d:%d], processor 0x%08x\n", (int)xlr_boot1_info.board_major_version,
|
|
|
|
(int)xlr_boot1_info.board_minor_version, mips_rd_prid());
|
2009-10-15 21:14:42 +00:00
|
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* XXX Maybe return the state of the watchdog in enter, and pass it to
|
|
|
|
* exit? Like spl().
|
|
|
|
*/
|
|
|
|
void
|
|
|
|
platform_trap_enter(void)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
platform_trap_exit(void)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2009-10-29 15:55:25 +00:00
|
|
|
/*
|
|
|
|
void
|
|
|
|
platform_update_intrmask(int intr)
|
|
|
|
{
|
|
|
|
write_c0_eimr64(read_c0_eimr64() | (1ULL<<intr));
|
|
|
|
}
|
|
|
|
*/
|
2009-10-15 21:14:42 +00:00
|
|
|
|
2009-10-29 21:14:10 +00:00
|
|
|
void
|
|
|
|
disable_msgring_int(void *arg);
|
|
|
|
void
|
|
|
|
enable_msgring_int(void *arg);
|
2009-10-15 21:14:42 +00:00
|
|
|
void xlr_msgring_handler(struct trapframe *tf);
|
|
|
|
void msgring_process_fast_intr(void *arg);
|
|
|
|
|
|
|
|
struct msgring_ithread {
|
|
|
|
struct thread *i_thread;
|
2009-10-29 21:14:10 +00:00
|
|
|
u_int i_pending;
|
|
|
|
u_int i_flags;
|
|
|
|
int i_cpu;
|
2009-10-15 21:14:42 +00:00
|
|
|
};
|
|
|
|
struct msgring_ithread msgring_ithreads[MAXCPU];
|
|
|
|
char ithd_name[MAXCPU][32];
|
|
|
|
|
|
|
|
void
|
|
|
|
msgring_process_fast_intr(void *arg)
|
|
|
|
{
|
|
|
|
int cpu = PCPU_GET(cpuid);
|
|
|
|
volatile struct msgring_ithread *it;
|
|
|
|
struct proc *p;
|
|
|
|
struct thread *td;
|
2009-10-29 21:14:10 +00:00
|
|
|
|
2009-10-15 21:14:42 +00:00
|
|
|
/* wakeup an appropriate intr_thread for processing this interrupt */
|
|
|
|
it = (volatile struct msgring_ithread *)&msgring_ithreads[cpu];
|
|
|
|
td = it->i_thread;
|
|
|
|
p = td->td_proc;
|
2009-10-29 15:55:25 +00:00
|
|
|
|
2009-10-29 21:14:10 +00:00
|
|
|
/*
|
|
|
|
* Interrupt thread will enable the interrupts after processing all
|
|
|
|
* messages
|
|
|
|
*/
|
2009-10-15 21:14:42 +00:00
|
|
|
disable_msgring_int(NULL);
|
|
|
|
it->i_pending = 1;
|
|
|
|
if (TD_AWAITING_INTR(td)) {
|
2009-10-29 21:14:10 +00:00
|
|
|
thread_lock(td);
|
2009-10-15 21:14:42 +00:00
|
|
|
CTR3(KTR_INTR, "%s: schedule pid %d (%s)", __func__, p->p_pid,
|
2009-10-29 21:14:10 +00:00
|
|
|
p->p_comm);
|
2009-10-15 21:14:42 +00:00
|
|
|
TD_CLR_IWAIT(td);
|
2009-10-29 15:55:25 +00:00
|
|
|
sched_add(td, SRQ_INTR);
|
2009-10-29 21:14:10 +00:00
|
|
|
thread_unlock(td);
|
2009-10-15 21:14:42 +00:00
|
|
|
} else {
|
|
|
|
CTR4(KTR_INTR, "%s: pid %d (%s): state %d",
|
2009-10-29 21:14:10 +00:00
|
|
|
__func__, p->p_pid, p->p_comm, td->td_state);
|
2009-10-15 21:14:42 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
}
|
2009-10-29 21:14:10 +00:00
|
|
|
|
2009-10-15 21:14:42 +00:00
|
|
|
#define MIT_DEAD 4
|
|
|
|
static void
|
2009-10-29 21:14:10 +00:00
|
|
|
msgring_process(void *arg)
|
2009-10-15 21:14:42 +00:00
|
|
|
{
|
|
|
|
volatile struct msgring_ithread *ithd;
|
|
|
|
struct thread *td;
|
|
|
|
struct proc *p;
|
|
|
|
|
|
|
|
td = curthread;
|
|
|
|
p = td->td_proc;
|
|
|
|
ithd = (volatile struct msgring_ithread *)arg;
|
|
|
|
KASSERT(ithd->i_thread == td,
|
2009-10-29 21:14:10 +00:00
|
|
|
("%s:msg_ithread and proc linkage out of sync", __func__));
|
2009-10-15 21:14:42 +00:00
|
|
|
|
|
|
|
/* First bind this thread to the right CPU */
|
2009-10-29 15:55:25 +00:00
|
|
|
thread_lock(td);
|
2009-10-15 21:14:42 +00:00
|
|
|
sched_bind(td, ithd->i_cpu);
|
2009-10-29 15:55:25 +00:00
|
|
|
thread_unlock(td);
|
2009-10-15 21:14:42 +00:00
|
|
|
|
2009-10-29 21:14:10 +00:00
|
|
|
//printf("Started %s on CPU %d\n", __FUNCTION__, ithd->i_cpu);
|
2009-10-15 21:14:42 +00:00
|
|
|
|
2009-10-29 21:14:10 +00:00
|
|
|
while (1) {
|
2009-10-15 21:14:42 +00:00
|
|
|
if (ithd->i_flags & MIT_DEAD) {
|
|
|
|
CTR3(KTR_INTR, "%s: pid %d (%s) exiting", __func__,
|
2009-10-29 21:14:10 +00:00
|
|
|
p->p_pid, p->p_comm);
|
2009-10-29 15:55:25 +00:00
|
|
|
kthread_exit();
|
2009-10-15 21:14:42 +00:00
|
|
|
}
|
|
|
|
while (ithd->i_pending) {
|
|
|
|
/*
|
2009-10-29 21:14:10 +00:00
|
|
|
* This might need a full read and write barrier to
|
|
|
|
* make sure that this write posts before any of the
|
|
|
|
* memory or device accesses in the handlers.
|
2009-10-15 21:14:42 +00:00
|
|
|
*/
|
|
|
|
atomic_store_rel_int(&ithd->i_pending, 0);
|
|
|
|
xlr_msgring_handler(NULL);
|
|
|
|
}
|
|
|
|
if (!ithd->i_pending && !(ithd->i_flags & MIT_DEAD)) {
|
2009-10-29 21:14:10 +00:00
|
|
|
thread_lock(td);
|
2009-10-29 15:55:25 +00:00
|
|
|
sched_class(td, PRI_ITHD);
|
2009-10-15 21:14:42 +00:00
|
|
|
TD_SET_IWAIT(td);
|
2009-10-29 21:14:10 +00:00
|
|
|
thread_unlock(td);
|
2009-10-15 21:14:42 +00:00
|
|
|
enable_msgring_int(NULL);
|
|
|
|
mi_switch(SW_VOL, NULL);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
}
|
2009-10-29 21:14:10 +00:00
|
|
|
void
|
|
|
|
platform_prep_smp_launch(void)
|
2009-10-15 21:14:42 +00:00
|
|
|
{
|
|
|
|
int cpu;
|
|
|
|
uint32_t cpu_mask;
|
|
|
|
struct msgring_ithread *ithd;
|
|
|
|
struct thread *td;
|
|
|
|
struct proc *p;
|
|
|
|
int error;
|
|
|
|
|
|
|
|
cpu_mask = PCPU_GET(cpumask) | PCPU_GET(other_cpus);
|
|
|
|
|
|
|
|
/* Create kernel threads for message ring interrupt processing */
|
|
|
|
/* Currently create one task for thread 0 of each core */
|
2009-10-29 21:14:10 +00:00
|
|
|
for (cpu = 0; cpu < MAXCPU; cpu += 1) {
|
2009-10-15 21:14:42 +00:00
|
|
|
|
2009-10-29 21:14:10 +00:00
|
|
|
if (!((1 << cpu) & cpu_mask))
|
2009-10-15 21:14:42 +00:00
|
|
|
continue;
|
|
|
|
|
2009-10-29 21:14:10 +00:00
|
|
|
if ((cpu_ltop_map[cpu] % 4) != 0)
|
2009-10-15 21:14:42 +00:00
|
|
|
continue;
|
|
|
|
|
|
|
|
ithd = &msgring_ithreads[cpu];
|
|
|
|
sprintf(ithd_name[cpu], "msg_intr%d", cpu);
|
2009-10-29 15:55:25 +00:00
|
|
|
error = kproc_create(msgring_process,
|
2009-10-29 21:14:10 +00:00
|
|
|
(void *)ithd,
|
|
|
|
&p,
|
|
|
|
(RFSTOPPED | RFHIGHPID),
|
|
|
|
2,
|
|
|
|
ithd_name[cpu]);
|
2009-10-29 15:55:25 +00:00
|
|
|
|
2009-10-15 21:14:42 +00:00
|
|
|
if (error)
|
2009-10-29 15:55:25 +00:00
|
|
|
panic("kproc_create() failed with %d", error);
|
2009-10-29 21:14:10 +00:00
|
|
|
td = FIRST_THREAD_IN_PROC(p); /* XXXKSE */
|
2009-10-29 15:55:25 +00:00
|
|
|
|
|
|
|
thread_lock(td);
|
|
|
|
sched_class(td, PRI_ITHD);
|
2009-10-15 21:14:42 +00:00
|
|
|
TD_SET_IWAIT(td);
|
2009-10-29 15:55:25 +00:00
|
|
|
thread_unlock(td);
|
2009-10-15 21:14:42 +00:00
|
|
|
ithd->i_thread = td;
|
|
|
|
ithd->i_pending = 0;
|
|
|
|
ithd->i_cpu = cpu;
|
|
|
|
CTR2(KTR_INTR, "%s: created %s", __func__, ithd_name[cpu]);
|
|
|
|
}
|
|
|
|
}
|