2004-05-14 11:46:45 +00:00
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/* $NetBSD: sa11x0_gpioreg.h,v 1.2 2001/07/30 15:58:56 rjs Exp $ */
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/*-
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* Copyright (c) 2001 The NetBSD Foundation, Inc. All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Ichiro FUKUHARA (ichiro@ichiro.org).
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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/*
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2012-06-13 04:59:00 +00:00
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* SA-11x0 GPIO Register
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2004-05-14 11:46:45 +00:00
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*/
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#define SAGPIO_NPORTS 8
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/* GPIO pin-level register */
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#define SAGPIO_PLR 0x00
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/* GPIO pin direction register */
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#define SAGPIO_PDR 0x04
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/* GPIO pin output set register */
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#define SAGPIO_PSR 0x08
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/* GPIO pin output clear register */
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#define SAGPIO_PCR 0x0C
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/* GPIO rising-edge detect register */
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#define SAGPIO_RER 0x10
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/* GPIO falling-edge detect register */
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#define SAGPIO_FER 0x14
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/* GPIO edge-detect status register */
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#define SAGPIO_EDR 0x18
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/* GPIO alternate function register */
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#define SAGPIO_AFR 0x1C
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/* XXX */
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#define GPIO(x) (0x00000001 << (x))
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/*
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* SA-11x0 GPIOs parameter
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*/
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/*
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port name desc
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0 Reserved
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1 Reserved
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2...9 LDD{8..15} LCD DATA(8-15)
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10 SSP_TXD SSP transmit
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11 SSP_RXD SSP receive
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12 SSP_SCLK SSP serial clock
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13 SSP_SFRM SSP frameclock
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14 UART_TXD UART transmit
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15 UART_RXD UART receive
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16 GPCLK_OUT General-purpose clock out
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17 Reserved
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18 UART_SCLK Sample clock input
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19 SSP_CLK Sample clock input
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20 UART_SCLK3 Sample clock input
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21 MCP_CLK MCP dock in
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22 TREQA Either TIC request A
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23 TREQB Either TIC request B
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24 Reserved
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25 RTC Real Time Clock
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26 RCLK_OUT internal clock /2
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27 32KHZ_OUT Raw 32.768kHz osc output
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*/
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