1995-08-24 08:56:20 +00:00
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/*
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* Intel PCIC or compatible Controller driver
|
1999-01-19 00:18:28 +00:00
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* May be built to make a loadable module.
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1995-08-24 08:56:20 +00:00
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*-------------------------------------------------------------------------
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*
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* Copyright (c) 1995 Andrew McRae. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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1999-09-26 21:52:43 +00:00
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*
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* $FreeBSD$
|
1995-08-24 08:56:20 +00:00
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|
*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
|
1999-01-19 00:18:28 +00:00
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#include <sys/module.h>
|
1997-01-13 21:51:13 +00:00
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#include <sys/select.h>
|
1995-08-24 08:56:20 +00:00
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#include <machine/clock.h>
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1999-10-25 02:41:58 +00:00
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#if 0
|
1997-01-14 16:29:05 +00:00
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#include <i386/isa/icu.h>
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#include <i386/isa/isa_device.h>
|
1999-09-26 21:52:43 +00:00
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#include <i386/isa/intr_machdep.h>
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1999-10-25 02:41:58 +00:00
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#endif
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1997-01-14 16:29:05 +00:00
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1995-11-21 08:27:00 +00:00
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#include <pccard/i82365.h>
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1997-01-13 21:51:13 +00:00
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1997-11-18 21:04:01 +00:00
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#include <pccard/cardinfo.h>
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1995-12-16 00:11:11 +00:00
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#include <pccard/driver.h>
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1995-11-21 08:27:00 +00:00
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#include <pccard/slot.h>
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1999-03-10 15:00:54 +00:00
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#include <pccard/pcic.h>
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#ifdef APIC_IO
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#include <machine/smp.h>
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#endif
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1995-10-21 00:55:36 +00:00
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1995-08-24 08:56:20 +00:00
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/*
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* Prototypes for interrupt handler.
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*/
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1999-10-16 05:11:46 +00:00
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static inthand2_t pcicintr;
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1995-11-09 20:44:36 +00:00
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static int pcic_ioctl __P((struct slot *, int, caddr_t));
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static int pcic_power __P((struct slot *));
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1995-11-13 08:39:44 +00:00
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static timeout_t pcic_reset;
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1997-01-08 00:22:58 +00:00
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static void pcic_resume(struct slot *);
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1995-11-09 20:44:36 +00:00
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static void pcic_disable __P((struct slot *));
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static void pcic_mapirq __P((struct slot *, int));
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static timeout_t pcictimeout;
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1997-09-21 22:02:25 +00:00
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static struct callout_handle pcictimeout_ch
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= CALLOUT_HANDLE_INITIALIZER(&pcictimeout_ch);
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1995-11-09 20:44:36 +00:00
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static int pcic_memory(struct slot *, int);
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static int pcic_io(struct slot *, int);
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1995-08-24 08:56:20 +00:00
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/*
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* Per-slot data table.
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*/
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1995-11-09 20:44:36 +00:00
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static struct pcic_slot {
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1997-10-26 04:36:24 +00:00
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int slotnum; /* My slot number */
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1995-08-24 08:56:20 +00:00
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int index; /* Index register */
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int data; /* Data register */
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int offset; /* Offset value for index */
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1995-11-09 20:44:36 +00:00
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char controller; /* Device type */
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char revision; /* Device Revision */
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1997-10-26 04:36:24 +00:00
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struct slot *slt; /* Back ptr to slot */
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u_char (*getb)(struct pcic_slot *, int);
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void (*putb)(struct pcic_slot *, int, u_char);
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1997-04-20 07:21:12 +00:00
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u_char *regs; /* Pointer to regs in mem */
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1995-11-09 20:44:36 +00:00
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} pcic_slots[PCIC_MAX_SLOTS];
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static int pcic_irq;
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static struct slot_ctrl cinfo;
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|
1995-08-24 08:56:20 +00:00
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/*
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* Internal inline functions for accessing the PCIC.
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*/
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/*
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* Read a register from the PCIC.
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*/
|
1998-04-15 17:47:40 +00:00
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static __inline unsigned char
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1997-10-06 02:46:38 +00:00
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getb1(struct pcic_slot *sp, int reg)
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1995-08-24 08:56:20 +00:00
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{
|
1997-10-06 02:46:38 +00:00
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outb(sp->index, sp->offset + reg);
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return inb(sp->data);
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1995-08-24 08:56:20 +00:00
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}
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/*
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* Write a register on the PCIC
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*/
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1998-04-15 17:47:40 +00:00
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static __inline void
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1997-10-06 02:46:38 +00:00
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putb1(struct pcic_slot *sp, int reg, unsigned char val)
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1995-08-24 08:56:20 +00:00
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{
|
1997-10-06 02:46:38 +00:00
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outb(sp->index, sp->offset + reg);
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outb(sp->data, val);
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1995-08-24 08:56:20 +00:00
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}
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1997-01-08 00:22:58 +00:00
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1995-08-24 08:56:20 +00:00
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/*
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* Clear bit(s) of a register.
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*/
|
1998-04-15 17:47:40 +00:00
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static __inline void
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1995-08-24 08:56:20 +00:00
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clrb(struct pcic_slot *sp, int reg, unsigned char mask)
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{
|
1997-10-06 02:46:38 +00:00
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sp->putb(sp, reg, sp->getb(sp, reg) & ~mask);
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1995-08-24 08:56:20 +00:00
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}
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1997-01-08 00:22:58 +00:00
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1995-08-24 08:56:20 +00:00
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/*
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* Set bit(s) of a register
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*/
|
1998-04-15 17:47:40 +00:00
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static __inline void
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1995-08-24 08:56:20 +00:00
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setb(struct pcic_slot *sp, int reg, unsigned char mask)
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{
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1997-10-06 02:46:38 +00:00
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sp->putb(sp, reg, sp->getb(sp, reg) | mask);
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1995-08-24 08:56:20 +00:00
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}
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/*
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* Write a 16 bit value to 2 adjacent PCIC registers
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*/
|
1998-04-15 17:47:40 +00:00
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static __inline void
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1997-10-06 03:17:36 +00:00
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putw(struct pcic_slot *sp, int reg, unsigned short word)
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1995-08-24 08:56:20 +00:00
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{
|
1997-10-06 02:46:38 +00:00
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sp->putb(sp, reg, word & 0xFF);
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sp->putb(sp, reg + 1, (word >> 8) & 0xff);
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1995-08-24 08:56:20 +00:00
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}
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/*
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* entry point from main code to map/unmap memory context.
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*/
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static int
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1997-10-26 04:36:24 +00:00
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pcic_memory(struct slot *slt, int win)
|
1995-08-24 08:56:20 +00:00
|
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{
|
1997-10-26 04:36:24 +00:00
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struct pcic_slot *sp = slt->cdata;
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struct mem_desc *mp = &slt->mem[win];
|
1995-11-09 20:44:36 +00:00
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int reg = mp->window * PCIC_MEMSIZE + PCIC_MEMBASE;
|
1995-08-24 08:56:20 +00:00
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|
1997-01-08 00:22:58 +00:00
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if (mp->flags & MDF_ACTIVE) {
|
1998-08-16 01:21:52 +00:00
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|
unsigned long sys_addr = (uintptr_t)(void *)mp->start >> 12;
|
1995-11-09 20:44:36 +00:00
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/*
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|
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* Write the addresses, card offsets and length.
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* The values are all stored as the upper 12 bits of the
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* 24 bit address i.e everything is allocated as 4 Kb chunks.
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*/
|
1997-10-06 03:17:36 +00:00
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putw(sp, reg, sys_addr & 0xFFF);
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putw(sp, reg+2, (sys_addr + (mp->size >> 12) - 1) & 0xFFF);
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putw(sp, reg+4, ((mp->card >> 12) - sys_addr) & 0x3FFF);
|
1995-11-09 20:44:36 +00:00
|
|
|
/*
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|
|
* Each 16 bit register has some flags in the upper bits.
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*/
|
1995-08-24 08:56:20 +00:00
|
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|
if (mp->flags & MDF_16BITS)
|
1995-11-09 20:44:36 +00:00
|
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|
setb(sp, reg+1, PCIC_DATA16);
|
1995-08-24 08:56:20 +00:00
|
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|
if (mp->flags & MDF_ZEROWS)
|
1995-11-09 20:44:36 +00:00
|
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|
setb(sp, reg+1, PCIC_ZEROWS);
|
1995-08-24 08:56:20 +00:00
|
|
|
if (mp->flags & MDF_WS0)
|
1995-11-09 20:44:36 +00:00
|
|
|
setb(sp, reg+3, PCIC_MW0);
|
1995-08-24 08:56:20 +00:00
|
|
|
if (mp->flags & MDF_WS1)
|
1995-11-09 20:44:36 +00:00
|
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|
setb(sp, reg+3, PCIC_MW1);
|
1995-08-24 08:56:20 +00:00
|
|
|
if (mp->flags & MDF_ATTR)
|
1995-11-09 20:44:36 +00:00
|
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|
setb(sp, reg+5, PCIC_REG);
|
1995-08-24 08:56:20 +00:00
|
|
|
if (mp->flags & MDF_WP)
|
1995-11-09 20:44:36 +00:00
|
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|
setb(sp, reg+5, PCIC_WP);
|
|
|
|
/*
|
|
|
|
* Enable the memory window. By experiment, we need a delay.
|
|
|
|
*/
|
1997-10-06 03:17:36 +00:00
|
|
|
setb(sp, PCIC_ADDRWINE, (1<<win) | PCIC_MEMCS16);
|
1995-08-24 08:56:20 +00:00
|
|
|
DELAY(50);
|
1997-01-08 00:22:58 +00:00
|
|
|
} else {
|
1997-10-06 03:17:36 +00:00
|
|
|
clrb(sp, PCIC_ADDRWINE, 1<<win);
|
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|
|
putw(sp, reg, 0);
|
|
|
|
putw(sp, reg+2, 0);
|
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|
|
putw(sp, reg+4, 0);
|
1997-01-08 00:22:58 +00:00
|
|
|
}
|
1995-08-24 08:56:20 +00:00
|
|
|
return(0);
|
|
|
|
}
|
1995-11-09 20:44:36 +00:00
|
|
|
|
1995-08-24 08:56:20 +00:00
|
|
|
/*
|
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|
|
* pcic_io - map or unmap I/O context
|
|
|
|
*/
|
|
|
|
static int
|
1997-10-26 04:36:24 +00:00
|
|
|
pcic_io(struct slot *slt, int win)
|
1995-08-24 08:56:20 +00:00
|
|
|
{
|
1995-11-09 20:44:36 +00:00
|
|
|
int mask, reg;
|
1997-10-26 04:36:24 +00:00
|
|
|
struct pcic_slot *sp = slt->cdata;
|
|
|
|
struct io_desc *ip = &slt->io[win];
|
1996-02-21 23:20:21 +00:00
|
|
|
switch (win) {
|
|
|
|
case 0:
|
1995-08-24 08:56:20 +00:00
|
|
|
mask = PCIC_IO0_EN;
|
|
|
|
reg = PCIC_IO0;
|
1996-02-21 23:20:21 +00:00
|
|
|
break;
|
|
|
|
case 1:
|
1995-08-24 08:56:20 +00:00
|
|
|
mask = PCIC_IO1_EN;
|
|
|
|
reg = PCIC_IO1;
|
1996-02-21 23:20:21 +00:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
panic("Illegal PCIC I/O window request!");
|
1995-11-09 20:44:36 +00:00
|
|
|
}
|
|
|
|
if (ip->flags & IODF_ACTIVE) {
|
1996-02-21 23:20:21 +00:00
|
|
|
unsigned char x, ioctlv;
|
1995-08-24 08:56:20 +00:00
|
|
|
|
1997-10-06 03:17:36 +00:00
|
|
|
putw(sp, reg, ip->start);
|
|
|
|
putw(sp, reg+2, ip->start+ip->size-1);
|
1996-02-21 23:20:21 +00:00
|
|
|
x = 0;
|
1995-08-24 08:56:20 +00:00
|
|
|
if (ip->flags & IODF_ZEROWS)
|
1996-02-21 23:20:21 +00:00
|
|
|
x |= PCIC_IO_0WS;
|
1995-08-24 08:56:20 +00:00
|
|
|
if (ip->flags & IODF_WS)
|
|
|
|
x |= PCIC_IO_WS;
|
|
|
|
if (ip->flags & IODF_CS16)
|
|
|
|
x |= PCIC_IO_CS16;
|
1996-02-21 23:20:21 +00:00
|
|
|
if (ip->flags & IODF_16BIT)
|
1995-08-24 08:56:20 +00:00
|
|
|
x |= PCIC_IO_16BIT;
|
1995-11-09 20:44:36 +00:00
|
|
|
/*
|
|
|
|
* Extract the current flags and merge with new flags.
|
|
|
|
* Flags for window 0 in lower nybble, and in upper nybble
|
|
|
|
* for window 1.
|
|
|
|
*/
|
1997-04-20 07:21:12 +00:00
|
|
|
ioctlv = sp->getb(sp, PCIC_IOCTL);
|
1996-02-21 23:20:21 +00:00
|
|
|
DELAY(100);
|
|
|
|
switch (win) {
|
|
|
|
case 0:
|
1997-04-20 07:21:12 +00:00
|
|
|
sp->putb(sp, PCIC_IOCTL, x | (ioctlv & 0xf0));
|
1996-02-21 23:20:21 +00:00
|
|
|
break;
|
|
|
|
case 1:
|
1997-04-20 07:21:12 +00:00
|
|
|
sp->putb(sp, PCIC_IOCTL, (x << 4) | (ioctlv & 0xf));
|
1996-02-21 23:20:21 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
DELAY(100);
|
1997-10-06 03:17:36 +00:00
|
|
|
setb(sp, PCIC_ADDRWINE, mask);
|
1995-08-24 08:56:20 +00:00
|
|
|
DELAY(100);
|
1995-11-09 20:44:36 +00:00
|
|
|
} else {
|
1997-10-06 03:17:36 +00:00
|
|
|
clrb(sp, PCIC_ADDRWINE, mask);
|
1996-02-21 23:20:21 +00:00
|
|
|
DELAY(100);
|
1997-10-06 03:17:36 +00:00
|
|
|
putw(sp, reg, 0);
|
|
|
|
putw(sp, reg + 2, 0);
|
1995-11-09 20:44:36 +00:00
|
|
|
}
|
1995-08-24 08:56:20 +00:00
|
|
|
return(0);
|
|
|
|
}
|
1995-11-09 20:44:36 +00:00
|
|
|
|
1995-08-24 08:56:20 +00:00
|
|
|
/*
|
|
|
|
* Look for an Intel PCIC (or compatible).
|
|
|
|
* For each available slot, allocate a PC-CARD slot.
|
|
|
|
*/
|
|
|
|
|
1996-02-21 23:20:21 +00:00
|
|
|
/*
|
|
|
|
* VLSI 82C146 has incompatibilities about the I/O address
|
1997-01-08 00:22:58 +00:00
|
|
|
* of slot 1. Assume it's the only PCIC whose vendor ID is 0x84,
|
|
|
|
* contact Nate Williams <nate@FreeBSD.org> if incorrect.
|
1996-02-21 23:20:21 +00:00
|
|
|
*/
|
1999-10-15 17:29:21 +00:00
|
|
|
static int
|
|
|
|
pcic_probe(device_t dev)
|
1995-08-24 08:56:20 +00:00
|
|
|
{
|
1998-12-07 21:58:50 +00:00
|
|
|
int slotnum, validslots = 0;
|
1997-10-26 04:36:24 +00:00
|
|
|
struct slot *slt;
|
1995-11-09 20:44:36 +00:00
|
|
|
struct pcic_slot *sp;
|
|
|
|
unsigned char c;
|
1999-10-16 05:11:46 +00:00
|
|
|
void *ih;
|
|
|
|
char *name;
|
1999-10-15 17:29:21 +00:00
|
|
|
int i;
|
1999-10-16 05:11:46 +00:00
|
|
|
int error;
|
|
|
|
struct resource *res;
|
|
|
|
int rid;
|
1997-02-21 05:46:57 +00:00
|
|
|
static int maybe_vlsi = 0;
|
1995-08-24 08:56:20 +00:00
|
|
|
|
1999-10-15 17:29:21 +00:00
|
|
|
if (device_get_unit(dev) != 0)
|
|
|
|
return ENXIO;
|
|
|
|
|
1995-11-09 20:44:36 +00:00
|
|
|
/*
|
|
|
|
* Initialise controller information structure.
|
|
|
|
*/
|
1995-08-24 08:56:20 +00:00
|
|
|
cinfo.mapmem = pcic_memory;
|
|
|
|
cinfo.mapio = pcic_io;
|
|
|
|
cinfo.ioctl = pcic_ioctl;
|
|
|
|
cinfo.power = pcic_power;
|
|
|
|
cinfo.mapirq = pcic_mapirq;
|
|
|
|
cinfo.reset = pcic_reset;
|
|
|
|
cinfo.disable = pcic_disable;
|
1997-01-08 00:22:58 +00:00
|
|
|
cinfo.resume = pcic_resume;
|
1995-08-24 08:56:20 +00:00
|
|
|
cinfo.maxmem = PCIC_MEM_WIN;
|
|
|
|
cinfo.maxio = PCIC_IO_WIN;
|
|
|
|
|
1995-11-09 20:44:36 +00:00
|
|
|
sp = pcic_slots;
|
1997-10-26 04:36:24 +00:00
|
|
|
for (slotnum = 0; slotnum < PCIC_MAX_SLOTS; slotnum++, sp++) {
|
1995-11-09 20:44:36 +00:00
|
|
|
/*
|
|
|
|
* Initialise the PCIC slot table.
|
|
|
|
*/
|
1997-04-20 07:21:12 +00:00
|
|
|
sp->getb = getb1;
|
|
|
|
sp->putb = putb1;
|
1997-10-26 04:36:24 +00:00
|
|
|
if (slotnum < 4) {
|
1995-11-09 20:44:36 +00:00
|
|
|
sp->index = PCIC_INDEX_0;
|
|
|
|
sp->data = PCIC_DATA_0;
|
1997-10-26 04:36:24 +00:00
|
|
|
sp->offset = slotnum * PCIC_SLOT_SIZE;
|
1995-11-09 20:44:36 +00:00
|
|
|
} else {
|
|
|
|
sp->index = PCIC_INDEX_1;
|
|
|
|
sp->data = PCIC_DATA_1;
|
1997-10-26 04:36:24 +00:00
|
|
|
sp->offset = (slotnum - 4) * PCIC_SLOT_SIZE;
|
1995-08-24 08:56:20 +00:00
|
|
|
}
|
1997-02-18 19:20:52 +00:00
|
|
|
/*
|
|
|
|
* XXX - Screwed up slot 1 on the VLSI chips. According to
|
|
|
|
* the Linux PCMCIA code from David Hinds, working chipsets
|
|
|
|
* return 0x84 from their (correct) ID ports, while the broken
|
|
|
|
* ones would need to be probed at the new offset we set after
|
|
|
|
* we assume it's broken.
|
|
|
|
*/
|
1997-10-26 04:36:24 +00:00
|
|
|
if (slotnum == 1 && maybe_vlsi && sp->getb(sp, PCIC_ID_REV) != 0x84) {
|
1997-01-08 00:22:58 +00:00
|
|
|
sp->index += 4;
|
|
|
|
sp->data += 4;
|
|
|
|
sp->offset = PCIC_SLOT_SIZE << 1;
|
|
|
|
}
|
1995-11-09 20:44:36 +00:00
|
|
|
/*
|
|
|
|
* see if there's a PCMCIA controller here
|
|
|
|
* Intel PCMCIA controllers use 0x82 and 0x83
|
|
|
|
* IBM clone chips use 0x88 and 0x89, apparently
|
|
|
|
*/
|
1997-10-06 02:46:38 +00:00
|
|
|
c = sp->getb(sp, PCIC_ID_REV);
|
1995-11-09 20:44:36 +00:00
|
|
|
sp->revision = -1;
|
|
|
|
switch(c) {
|
|
|
|
/*
|
|
|
|
* 82365 or clones.
|
|
|
|
*/
|
|
|
|
case 0x82:
|
|
|
|
case 0x83:
|
|
|
|
sp->controller = PCIC_I82365;
|
|
|
|
sp->revision = c & 1;
|
|
|
|
/*
|
|
|
|
* Now check for VADEM chips.
|
|
|
|
*/
|
|
|
|
outb(sp->index, 0x0E);
|
|
|
|
outb(sp->index, 0x37);
|
|
|
|
setb(sp, 0x3A, 0x40);
|
1997-10-06 02:46:38 +00:00
|
|
|
c = sp->getb(sp, PCIC_ID_REV);
|
1995-11-09 20:44:36 +00:00
|
|
|
if (c & 0x08) {
|
1998-08-25 22:46:44 +00:00
|
|
|
switch (sp->revision = c & 7) {
|
|
|
|
case 1:
|
|
|
|
sp->controller = PCIC_VG365;
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
sp->controller = PCIC_VG465;
|
|
|
|
break;
|
|
|
|
case 3:
|
|
|
|
sp->controller = PCIC_VG468;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
sp->controller = PCIC_VG469;
|
|
|
|
break;
|
|
|
|
}
|
1995-11-09 20:44:36 +00:00
|
|
|
clrb(sp, 0x3A, 0x40);
|
1995-08-24 08:56:20 +00:00
|
|
|
}
|
1996-02-21 23:20:21 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Check for RICOH RF5C396 PCMCIA Controller
|
|
|
|
*/
|
1997-10-06 02:46:38 +00:00
|
|
|
c = sp->getb(sp, 0x3a);
|
1996-02-21 23:20:21 +00:00
|
|
|
if (c == 0xb2) {
|
|
|
|
sp->controller = PCIC_RF5C396;
|
|
|
|
}
|
|
|
|
|
1995-11-09 20:44:36 +00:00
|
|
|
break;
|
|
|
|
/*
|
|
|
|
* VLSI chips.
|
|
|
|
*/
|
|
|
|
case 0x84:
|
|
|
|
sp->controller = PCIC_VLSI;
|
1997-02-21 05:46:57 +00:00
|
|
|
maybe_vlsi = 1;
|
1995-11-09 20:44:36 +00:00
|
|
|
break;
|
|
|
|
case 0x88:
|
|
|
|
case 0x89:
|
|
|
|
sp->controller = PCIC_IBM;
|
|
|
|
sp->revision = c & 1;
|
|
|
|
break;
|
1996-02-21 23:20:21 +00:00
|
|
|
case 0x8a:
|
|
|
|
sp->controller = PCIC_IBM_KING;
|
|
|
|
sp->revision = c & 1;
|
|
|
|
break;
|
1995-11-09 20:44:36 +00:00
|
|
|
default:
|
|
|
|
continue;
|
1995-08-24 08:56:20 +00:00
|
|
|
}
|
1995-11-09 20:44:36 +00:00
|
|
|
/*
|
|
|
|
* Check for Cirrus logic chips.
|
|
|
|
*/
|
1997-04-20 07:21:12 +00:00
|
|
|
sp->putb(sp, 0x1F, 0);
|
|
|
|
c = sp->getb(sp, 0x1F);
|
1995-11-09 20:44:36 +00:00
|
|
|
if ((c & 0xC0) == 0xC0) {
|
1997-04-20 07:21:12 +00:00
|
|
|
c = sp->getb(sp, 0x1F);
|
1995-11-09 20:44:36 +00:00
|
|
|
if ((c & 0xC0) == 0) {
|
|
|
|
if (c & 0x20)
|
|
|
|
sp->controller = PCIC_PD672X;
|
|
|
|
else
|
|
|
|
sp->controller = PCIC_PD6710;
|
|
|
|
sp->revision = 8 - ((c & 0x1F) >> 2);
|
1995-08-24 08:56:20 +00:00
|
|
|
}
|
|
|
|
}
|
1995-11-09 20:44:36 +00:00
|
|
|
switch(sp->controller) {
|
|
|
|
case PCIC_I82365:
|
1999-10-16 05:11:46 +00:00
|
|
|
name = "Intel i82365";
|
1995-11-09 20:44:36 +00:00
|
|
|
break;
|
|
|
|
case PCIC_IBM:
|
1999-10-16 05:11:46 +00:00
|
|
|
name = "IBM PCIC";
|
1995-11-09 20:44:36 +00:00
|
|
|
break;
|
1996-02-21 23:20:21 +00:00
|
|
|
case PCIC_IBM_KING:
|
1999-10-16 05:11:46 +00:00
|
|
|
name = "IBM KING PCMCIA Controller";
|
1996-02-21 23:20:21 +00:00
|
|
|
break;
|
1995-11-09 20:44:36 +00:00
|
|
|
case PCIC_PD672X:
|
1999-10-16 05:11:46 +00:00
|
|
|
name = "Cirrus Logic PD672X";
|
1995-11-09 20:44:36 +00:00
|
|
|
break;
|
|
|
|
case PCIC_PD6710:
|
1999-10-16 05:11:46 +00:00
|
|
|
name = "Cirrus Logic PD6710";
|
1995-11-09 20:44:36 +00:00
|
|
|
break;
|
1998-08-25 22:46:44 +00:00
|
|
|
case PCIC_VG365:
|
1999-10-16 05:11:46 +00:00
|
|
|
name = "Vadem 365";
|
1998-08-25 22:46:44 +00:00
|
|
|
break;
|
|
|
|
case PCIC_VG465:
|
1999-10-16 05:11:46 +00:00
|
|
|
name = "Vadem 465";
|
1998-08-25 22:46:44 +00:00
|
|
|
break;
|
1995-11-09 20:44:36 +00:00
|
|
|
case PCIC_VG468:
|
1999-10-16 05:11:46 +00:00
|
|
|
name = "Vadem 468";
|
1995-11-09 20:44:36 +00:00
|
|
|
break;
|
|
|
|
case PCIC_VG469:
|
1999-10-16 05:11:46 +00:00
|
|
|
name = "Vadem 469";
|
1995-11-09 20:44:36 +00:00
|
|
|
break;
|
1996-02-21 23:20:21 +00:00
|
|
|
case PCIC_RF5C396:
|
1999-10-16 05:11:46 +00:00
|
|
|
name = "Ricoh RF5C396";
|
1996-02-21 23:20:21 +00:00
|
|
|
break;
|
|
|
|
case PCIC_VLSI:
|
1999-10-16 05:11:46 +00:00
|
|
|
name = "VLSI 82C146";
|
1996-02-21 23:20:21 +00:00
|
|
|
break;
|
1995-11-09 20:44:36 +00:00
|
|
|
default:
|
1999-10-16 05:11:46 +00:00
|
|
|
name = "Unknown!";
|
1995-11-09 20:44:36 +00:00
|
|
|
break;
|
1995-08-24 08:56:20 +00:00
|
|
|
}
|
1999-10-16 05:11:46 +00:00
|
|
|
device_set_desc(dev, name);
|
1995-11-09 20:44:36 +00:00
|
|
|
/*
|
|
|
|
* OK it seems we have a PCIC or lookalike.
|
|
|
|
* Allocate a slot and initialise the data structures.
|
|
|
|
*/
|
|
|
|
validslots++;
|
1997-10-26 04:36:24 +00:00
|
|
|
sp->slotnum = slotnum;
|
|
|
|
slt = pccard_alloc_slot(&cinfo);
|
|
|
|
if (slt == 0)
|
1995-11-09 20:44:36 +00:00
|
|
|
continue;
|
1997-10-26 04:36:24 +00:00
|
|
|
slt->cdata = sp;
|
|
|
|
sp->slt = slt;
|
1995-11-09 20:44:36 +00:00
|
|
|
/*
|
1999-10-25 02:41:58 +00:00
|
|
|
* If we haven't allocated an interrupt for the controller,
|
|
|
|
* then attempt to get one.
|
1995-11-09 20:44:36 +00:00
|
|
|
*/
|
|
|
|
if (pcic_irq == 0) {
|
1999-01-29 01:18:15 +00:00
|
|
|
/* See if the user has requested a specific IRQ */
|
1999-10-16 05:11:46 +00:00
|
|
|
if (!getenv_int("machdep.pccard.pcic_irq", &pcic_irq))
|
|
|
|
pcic_irq = 0;
|
|
|
|
rid = 0;
|
|
|
|
res = bus_alloc_resource(dev, SYS_RES_IRQ,
|
|
|
|
&rid, pcic_irq, ~0, 1, RF_ACTIVE);
|
|
|
|
if (res) {
|
|
|
|
error = bus_setup_intr(dev, res,
|
|
|
|
INTR_TYPE_MISC, pcicintr, NULL, &ih);
|
|
|
|
if (error) {
|
|
|
|
bus_release_resource(dev, SYS_RES_IRQ,
|
|
|
|
rid, res);
|
|
|
|
return error;
|
|
|
|
}
|
|
|
|
pcic_irq = rman_get_start(res);
|
|
|
|
} else {
|
|
|
|
printf("pcic: polling, can't alloc %d\n",
|
|
|
|
pcic_irq);
|
1999-08-17 22:13:06 +00:00
|
|
|
}
|
1995-08-24 08:56:20 +00:00
|
|
|
}
|
1997-10-06 03:17:36 +00:00
|
|
|
/*
|
|
|
|
* Modem cards send the speaker audio (dialing noises)
|
|
|
|
* to the host's speaker. Cirrus Logic PCIC chips must
|
|
|
|
* enable this. There is also a Low Power Dynamic Mode bit
|
|
|
|
* that claims to reduce power consumption by 30%, so
|
|
|
|
* enable it and hope for the best.
|
|
|
|
*/
|
|
|
|
if (sp->controller == PCIC_PD672X) {
|
|
|
|
setb(sp, PCIC_MISC1, PCIC_SPKR_EN);
|
|
|
|
setb(sp, PCIC_MISC2, PCIC_LPDM_EN);
|
1997-10-06 04:02:42 +00:00
|
|
|
}
|
1995-11-09 20:44:36 +00:00
|
|
|
/*
|
|
|
|
* Check for a card in this slot.
|
|
|
|
*/
|
1997-10-06 03:17:36 +00:00
|
|
|
setb(sp, PCIC_POWER, PCIC_PCPWRE| PCIC_DISRST);
|
1997-10-06 02:46:38 +00:00
|
|
|
if ((sp->getb(sp, PCIC_STATUS) & PCIC_CD) != PCIC_CD) {
|
1997-10-26 04:36:24 +00:00
|
|
|
slt->laststate = slt->state = empty;
|
1995-11-09 20:44:36 +00:00
|
|
|
} else {
|
1997-10-26 04:36:24 +00:00
|
|
|
slt->laststate = slt->state = filled;
|
|
|
|
pccard_event(sp->slt, card_inserted);
|
1995-11-09 20:44:36 +00:00
|
|
|
}
|
|
|
|
/*
|
|
|
|
* Assign IRQ for slot changes
|
|
|
|
*/
|
|
|
|
if (pcic_irq > 0)
|
1997-04-20 07:21:12 +00:00
|
|
|
sp->putb(sp, PCIC_STAT_INT, (pcic_irq << 4) | 0xF);
|
1995-08-24 08:56:20 +00:00
|
|
|
}
|
1998-04-20 15:15:20 +00:00
|
|
|
if (validslots && pcic_irq <= 0)
|
1997-11-04 17:50:23 +00:00
|
|
|
pcictimeout_ch = timeout(pcictimeout, 0, hz/2);
|
1999-10-15 17:29:21 +00:00
|
|
|
if (validslots) {
|
|
|
|
for (i = 0; i < validslots; i++) {
|
|
|
|
device_add_child(dev, NULL, -1, NULL);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return(validslots ? 0 : ENXIO);
|
1995-08-24 08:56:20 +00:00
|
|
|
}
|
1995-11-09 20:44:36 +00:00
|
|
|
|
1995-08-24 08:56:20 +00:00
|
|
|
/*
|
|
|
|
* ioctl calls - Controller specific ioctls
|
|
|
|
*/
|
|
|
|
static int
|
1997-10-26 04:36:24 +00:00
|
|
|
pcic_ioctl(struct slot *slt, int cmd, caddr_t data)
|
1995-08-24 08:56:20 +00:00
|
|
|
{
|
1997-10-26 04:36:24 +00:00
|
|
|
struct pcic_slot *sp = slt->cdata;
|
1995-08-24 08:56:20 +00:00
|
|
|
|
1995-11-09 20:44:36 +00:00
|
|
|
switch(cmd) {
|
1995-08-24 08:56:20 +00:00
|
|
|
default:
|
1999-08-01 18:12:51 +00:00
|
|
|
return(ENOTTY);
|
1995-11-09 20:44:36 +00:00
|
|
|
/*
|
|
|
|
* Get/set PCIC registers
|
|
|
|
*/
|
1995-08-24 08:56:20 +00:00
|
|
|
case PIOCGREG:
|
|
|
|
((struct pcic_reg *)data)->value =
|
1997-04-20 07:21:12 +00:00
|
|
|
sp->getb(sp, ((struct pcic_reg *)data)->reg);
|
1995-08-24 08:56:20 +00:00
|
|
|
break;
|
|
|
|
case PIOCSREG:
|
1997-04-20 07:21:12 +00:00
|
|
|
sp->putb(sp, ((struct pcic_reg *)data)->reg,
|
1995-08-24 08:56:20 +00:00
|
|
|
((struct pcic_reg *)data)->value);
|
|
|
|
break;
|
1995-11-09 20:44:36 +00:00
|
|
|
}
|
1995-08-24 08:56:20 +00:00
|
|
|
return(0);
|
|
|
|
}
|
1995-11-09 20:44:36 +00:00
|
|
|
|
1995-08-24 08:56:20 +00:00
|
|
|
/*
|
|
|
|
* pcic_power - Enable the power of the slot according to
|
|
|
|
* the parameters in the power structure(s).
|
|
|
|
*/
|
|
|
|
static int
|
1997-10-26 04:36:24 +00:00
|
|
|
pcic_power(struct slot *slt)
|
1995-08-24 08:56:20 +00:00
|
|
|
{
|
1996-01-06 07:49:43 +00:00
|
|
|
unsigned char reg = PCIC_DISRST|PCIC_PCPWRE;
|
1997-10-26 04:36:24 +00:00
|
|
|
struct pcic_slot *sp = slt->cdata;
|
1995-08-24 08:56:20 +00:00
|
|
|
|
1995-11-09 20:44:36 +00:00
|
|
|
switch(sp->controller) {
|
1995-08-24 08:56:20 +00:00
|
|
|
case PCIC_PD672X:
|
|
|
|
case PCIC_PD6710:
|
1998-08-25 22:46:44 +00:00
|
|
|
case PCIC_VG365:
|
|
|
|
case PCIC_VG465:
|
1996-02-21 23:20:21 +00:00
|
|
|
case PCIC_VG468:
|
1995-11-09 20:44:36 +00:00
|
|
|
case PCIC_VG469:
|
1996-02-21 23:20:21 +00:00
|
|
|
case PCIC_RF5C396:
|
|
|
|
case PCIC_VLSI:
|
|
|
|
case PCIC_IBM_KING:
|
1997-10-26 04:36:24 +00:00
|
|
|
switch(slt->pwr.vpp) {
|
1995-08-24 08:56:20 +00:00
|
|
|
default:
|
|
|
|
return(EINVAL);
|
|
|
|
case 0:
|
|
|
|
break;
|
|
|
|
case 50:
|
|
|
|
case 33:
|
|
|
|
reg |= PCIC_VPP_5V;
|
|
|
|
break;
|
|
|
|
case 120:
|
|
|
|
reg |= PCIC_VPP_12V;
|
|
|
|
break;
|
1995-11-09 20:44:36 +00:00
|
|
|
}
|
1997-10-26 04:36:24 +00:00
|
|
|
switch(slt->pwr.vcc) {
|
1995-08-24 08:56:20 +00:00
|
|
|
default:
|
|
|
|
return(EINVAL);
|
|
|
|
case 0:
|
|
|
|
break;
|
|
|
|
case 33:
|
1996-02-21 23:20:21 +00:00
|
|
|
if (sp->controller == PCIC_IBM_KING) {
|
|
|
|
reg |= PCIC_VCC_5V_KING;
|
|
|
|
break;
|
|
|
|
}
|
1997-05-22 07:29:24 +00:00
|
|
|
reg |= PCIC_VCC_3V;
|
1998-08-25 22:46:44 +00:00
|
|
|
if ((sp->controller == PCIC_VG468) ||
|
|
|
|
(sp->controller == PCIC_VG469) ||
|
|
|
|
(sp->controller == PCIC_VG465) ||
|
|
|
|
(sp->controller == PCIC_VG365))
|
1995-11-09 20:44:36 +00:00
|
|
|
setb(sp, 0x2f, 0x03) ;
|
|
|
|
else
|
|
|
|
setb(sp, 0x16, 0x02);
|
1995-08-24 08:56:20 +00:00
|
|
|
break;
|
|
|
|
case 50:
|
1996-02-21 23:20:21 +00:00
|
|
|
if (sp->controller == PCIC_IBM_KING) {
|
|
|
|
reg |= PCIC_VCC_5V_KING;
|
|
|
|
break;
|
|
|
|
}
|
1995-08-24 08:56:20 +00:00
|
|
|
reg |= PCIC_VCC_5V;
|
1998-08-25 22:46:44 +00:00
|
|
|
if ((sp->controller == PCIC_VG468) ||
|
|
|
|
(sp->controller == PCIC_VG469) ||
|
|
|
|
(sp->controller == PCIC_VG465) ||
|
|
|
|
(sp->controller == PCIC_VG365))
|
1995-11-09 20:44:36 +00:00
|
|
|
clrb(sp, 0x2f, 0x03) ;
|
|
|
|
else
|
|
|
|
clrb(sp, 0x16, 0x02);
|
1995-08-24 08:56:20 +00:00
|
|
|
break;
|
|
|
|
}
|
1996-02-21 23:20:21 +00:00
|
|
|
break;
|
1995-11-09 20:44:36 +00:00
|
|
|
}
|
1997-10-06 02:46:38 +00:00
|
|
|
sp->putb(sp, PCIC_POWER, reg);
|
1995-08-24 08:56:20 +00:00
|
|
|
DELAY(300*1000);
|
1997-10-26 04:36:24 +00:00
|
|
|
if (slt->pwr.vcc) {
|
1995-08-24 08:56:20 +00:00
|
|
|
reg |= PCIC_OUTENA;
|
1997-10-06 02:46:38 +00:00
|
|
|
sp->putb(sp, PCIC_POWER, reg);
|
|
|
|
DELAY(100*1000);
|
1995-11-09 20:44:36 +00:00
|
|
|
}
|
1997-05-22 07:29:24 +00:00
|
|
|
/* Some chips are smarter than us it seems, so if we weren't
|
|
|
|
* allowed to use 5V, try 3.3 instead
|
|
|
|
*/
|
1997-10-26 04:36:24 +00:00
|
|
|
if (!(sp->getb(sp, PCIC_STATUS) & 0x40) && slt->pwr.vcc == 50) {
|
|
|
|
slt->pwr.vcc = 33;
|
|
|
|
slt->pwr.vpp = 0;
|
|
|
|
return (pcic_power(slt));
|
1997-05-22 07:29:24 +00:00
|
|
|
}
|
1995-08-24 08:56:20 +00:00
|
|
|
return(0);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* tell the PCIC which irq we want to use. only the following are legal:
|
|
|
|
* 3, 4, 5, 7, 9, 10, 11, 12, 14, 15
|
|
|
|
*/
|
|
|
|
static void
|
1997-10-28 20:58:53 +00:00
|
|
|
pcic_mapirq(struct slot *slt, int irq)
|
1995-08-24 08:56:20 +00:00
|
|
|
{
|
1997-10-26 04:36:24 +00:00
|
|
|
struct pcic_slot *sp = slt->cdata;
|
1995-08-24 08:56:20 +00:00
|
|
|
if (irq == 0)
|
|
|
|
clrb(sp, PCIC_INT_GEN, 0xF);
|
|
|
|
else
|
1997-10-06 02:46:38 +00:00
|
|
|
sp->putb(sp, PCIC_INT_GEN,
|
|
|
|
(sp->getb(sp, PCIC_INT_GEN) & 0xF0) | irq);
|
1995-08-24 08:56:20 +00:00
|
|
|
}
|
1995-11-09 20:44:36 +00:00
|
|
|
|
1995-08-24 08:56:20 +00:00
|
|
|
/*
|
|
|
|
* pcic_reset - Reset the card and enable initial power.
|
|
|
|
*/
|
|
|
|
static void
|
1995-11-13 08:39:44 +00:00
|
|
|
pcic_reset(void *chan)
|
1995-08-24 08:56:20 +00:00
|
|
|
{
|
1997-10-26 04:36:24 +00:00
|
|
|
struct slot *slt = chan;
|
|
|
|
struct pcic_slot *sp = slt->cdata;
|
1995-11-09 20:44:36 +00:00
|
|
|
|
1997-10-26 04:36:24 +00:00
|
|
|
switch (slt->insert_seq) {
|
1995-11-09 20:44:36 +00:00
|
|
|
case 0: /* Something funny happended on the way to the pub... */
|
|
|
|
return;
|
|
|
|
case 1: /* Assert reset */
|
1997-10-06 03:17:36 +00:00
|
|
|
clrb(sp, PCIC_INT_GEN, PCIC_CARDRESET);
|
1997-10-26 04:36:24 +00:00
|
|
|
slt->insert_seq = 2;
|
1997-12-02 21:31:35 +00:00
|
|
|
timeout(pcic_reset, (void *)slt, hz/4);
|
1995-11-09 20:44:36 +00:00
|
|
|
return;
|
|
|
|
case 2: /* Deassert it again */
|
1997-10-06 03:17:36 +00:00
|
|
|
setb(sp, PCIC_INT_GEN, PCIC_CARDRESET|PCIC_IOCARD);
|
1997-10-26 04:36:24 +00:00
|
|
|
slt->insert_seq = 3;
|
1997-12-02 21:31:35 +00:00
|
|
|
timeout(pcic_reset, (void *)slt, hz/4);
|
1995-11-09 20:44:36 +00:00
|
|
|
return;
|
|
|
|
case 3: /* Wait if card needs more time */
|
1997-04-20 07:21:12 +00:00
|
|
|
if (!sp->getb(sp, PCIC_STATUS) & PCIC_READY) {
|
1997-12-02 21:31:35 +00:00
|
|
|
timeout(pcic_reset, (void *)slt, hz/10);
|
1995-11-09 20:44:36 +00:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
1997-10-26 04:36:24 +00:00
|
|
|
slt->insert_seq = 0;
|
1995-11-09 20:44:36 +00:00
|
|
|
if (sp->controller == PCIC_PD672X || sp->controller == PCIC_PD6710) {
|
1997-04-20 07:21:12 +00:00
|
|
|
sp->putb(sp, PCIC_TIME_SETUP0, 0x1);
|
|
|
|
sp->putb(sp, PCIC_TIME_CMD0, 0x6);
|
|
|
|
sp->putb(sp, PCIC_TIME_RECOV0, 0x0);
|
|
|
|
sp->putb(sp, PCIC_TIME_SETUP1, 1);
|
|
|
|
sp->putb(sp, PCIC_TIME_CMD1, 0xf);
|
|
|
|
sp->putb(sp, PCIC_TIME_RECOV1, 0);
|
1995-11-09 20:44:36 +00:00
|
|
|
}
|
1997-10-26 04:36:24 +00:00
|
|
|
selwakeup(&slt->selp);
|
1995-08-24 08:56:20 +00:00
|
|
|
}
|
1995-11-09 20:44:36 +00:00
|
|
|
|
1995-08-24 08:56:20 +00:00
|
|
|
/*
|
|
|
|
* pcic_disable - Disable the slot.
|
|
|
|
*/
|
|
|
|
static void
|
1997-10-26 04:36:24 +00:00
|
|
|
pcic_disable(struct slot *slt)
|
1995-08-24 08:56:20 +00:00
|
|
|
{
|
1997-10-26 04:36:24 +00:00
|
|
|
struct pcic_slot *sp = slt->cdata;
|
1995-08-24 08:56:20 +00:00
|
|
|
|
1997-04-20 07:21:12 +00:00
|
|
|
sp->putb(sp, PCIC_INT_GEN, 0);
|
|
|
|
sp->putb(sp, PCIC_POWER, 0);
|
1995-08-24 08:56:20 +00:00
|
|
|
}
|
|
|
|
|
1995-10-21 00:55:36 +00:00
|
|
|
/*
|
1998-04-20 15:15:20 +00:00
|
|
|
* PCIC timer. If the controller doesn't have a free IRQ to use
|
|
|
|
* or if interrupt steering doesn't work, poll the controller for
|
|
|
|
* insertion/removal events.
|
1995-10-21 00:55:36 +00:00
|
|
|
*/
|
|
|
|
static void
|
1995-11-09 08:58:20 +00:00
|
|
|
pcictimeout(void *chan)
|
1995-10-21 00:55:36 +00:00
|
|
|
{
|
1999-09-26 21:52:43 +00:00
|
|
|
pcicintr(0);
|
1997-11-04 17:50:23 +00:00
|
|
|
pcictimeout_ch = timeout(pcictimeout, 0, hz/2);
|
1995-10-21 00:55:36 +00:00
|
|
|
}
|
|
|
|
|
1995-08-24 08:56:20 +00:00
|
|
|
/*
|
|
|
|
* PCIC Interrupt handler.
|
|
|
|
* Check each slot in turn, and read the card status change
|
|
|
|
* register. If this is non-zero, then a change has occurred
|
|
|
|
* on this card, so send an event to the main code.
|
|
|
|
*/
|
|
|
|
static void
|
1999-10-16 05:11:46 +00:00
|
|
|
pcicintr(void *arg)
|
1995-08-24 08:56:20 +00:00
|
|
|
{
|
1995-11-09 20:44:36 +00:00
|
|
|
int slot, s;
|
|
|
|
unsigned char chg;
|
|
|
|
struct pcic_slot *sp = pcic_slots;
|
1995-08-24 08:56:20 +00:00
|
|
|
|
|
|
|
s = splhigh();
|
1999-10-25 23:17:24 +00:00
|
|
|
for (slot = 0; slot < PCIC_MAX_SLOTS; slot++, sp++) {
|
|
|
|
if (sp->slt && (chg = sp->getb(sp, PCIC_STAT_CHG)) != 0) {
|
1995-10-21 00:55:36 +00:00
|
|
|
if (chg & PCIC_CDTCH) {
|
1997-04-20 07:21:12 +00:00
|
|
|
if ((sp->getb(sp, PCIC_STATUS) & PCIC_CD) ==
|
1995-10-21 00:55:36 +00:00
|
|
|
PCIC_CD) {
|
1997-10-26 04:36:24 +00:00
|
|
|
pccard_event(sp->slt, card_inserted);
|
1995-10-21 00:55:36 +00:00
|
|
|
} else {
|
1997-10-26 04:36:24 +00:00
|
|
|
pccard_event(sp->slt, card_removed);
|
1995-10-21 00:55:36 +00:00
|
|
|
}
|
|
|
|
}
|
1999-10-25 23:17:24 +00:00
|
|
|
}
|
|
|
|
}
|
1995-08-24 08:56:20 +00:00
|
|
|
splx(s);
|
|
|
|
}
|
1997-01-08 00:22:58 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* pcic_resume - Suspend/resume support for PCIC
|
|
|
|
*/
|
|
|
|
static void
|
1997-10-26 04:36:24 +00:00
|
|
|
pcic_resume(struct slot *slt)
|
1997-01-08 00:22:58 +00:00
|
|
|
{
|
1997-10-26 04:36:24 +00:00
|
|
|
struct pcic_slot *sp = slt->cdata;
|
1999-10-25 02:41:58 +00:00
|
|
|
|
1997-01-08 00:22:58 +00:00
|
|
|
if (pcic_irq > 0)
|
1997-04-20 07:21:12 +00:00
|
|
|
sp->putb(sp, PCIC_STAT_INT, (pcic_irq << 4) | 0xF);
|
1997-10-06 03:17:36 +00:00
|
|
|
if (sp->controller == PCIC_PD672X) {
|
1997-10-06 04:02:42 +00:00
|
|
|
setb(sp, PCIC_MISC1, PCIC_SPKR_EN);
|
|
|
|
setb(sp, PCIC_MISC2, PCIC_LPDM_EN);
|
1997-10-06 03:17:36 +00:00
|
|
|
}
|
1997-01-08 00:22:58 +00:00
|
|
|
}
|
1999-10-15 17:29:21 +00:00
|
|
|
|
1999-10-25 02:41:58 +00:00
|
|
|
static int
|
|
|
|
pcic_activate_resource(device_t dev, device_t child, int type, int rid,
|
|
|
|
struct resource *r)
|
|
|
|
{
|
|
|
|
struct pccard_devinfo *devi = device_get_ivars(child);
|
|
|
|
int err;
|
|
|
|
|
|
|
|
switch (type) {
|
|
|
|
case SYS_RES_IOPORT:
|
1999-10-25 23:17:24 +00:00
|
|
|
{
|
|
|
|
struct io_desc *ip = &devi->slt->io[rid];
|
1999-10-25 02:41:58 +00:00
|
|
|
ip->flags |= IODF_ACTIVE;
|
|
|
|
ip->start = rman_get_start(r);
|
|
|
|
ip->size = rman_get_end(r) - rman_get_start(r) + 1;
|
|
|
|
err = pcic_io(devi->slt, rid);
|
1999-10-25 23:17:24 +00:00
|
|
|
if (err)
|
1999-10-25 02:41:58 +00:00
|
|
|
return err;
|
|
|
|
break;
|
1999-10-25 23:17:24 +00:00
|
|
|
}
|
1999-10-25 02:41:58 +00:00
|
|
|
case SYS_RES_IRQ:
|
|
|
|
pcic_mapirq(devi->slt, rman_get_start(r));
|
|
|
|
break;
|
1999-10-25 23:17:24 +00:00
|
|
|
case SYS_RES_MEMORY:
|
|
|
|
{
|
|
|
|
struct mem_desc *mp = &devi->slt->mem[rid];
|
|
|
|
mp->flags |= IODF_ACTIVE;
|
1999-10-28 04:51:39 +00:00
|
|
|
mp->start = (caddr_t) rman_get_start(r);
|
1999-10-25 23:17:24 +00:00
|
|
|
mp->size = rman_get_end(r) - rman_get_start(r) + 1;
|
|
|
|
err = pcic_memory(devi->slt, rid);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
break;
|
|
|
|
}
|
1999-10-25 02:41:58 +00:00
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
err = bus_generic_activate_resource(dev, child, type, rid, r);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
pcic_deactivate_resource(device_t dev, device_t child, int type, int rid,
|
|
|
|
struct resource *r)
|
|
|
|
{
|
|
|
|
struct pccard_devinfo *devi = device_get_ivars(child);
|
|
|
|
int err;
|
|
|
|
|
|
|
|
switch (type) {
|
|
|
|
case SYS_RES_IOPORT:
|
1999-10-25 23:17:24 +00:00
|
|
|
{
|
|
|
|
struct io_desc *ip = &devi->slt->io[rid];
|
1999-10-25 02:41:58 +00:00
|
|
|
ip->flags &= ~IODF_ACTIVE;
|
|
|
|
err = pcic_io(devi->slt, rid);
|
|
|
|
if (err) {
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
break;
|
1999-10-25 23:17:24 +00:00
|
|
|
}
|
1999-10-25 02:41:58 +00:00
|
|
|
case SYS_RES_IRQ:
|
|
|
|
pcic_mapirq(devi->slt, 0);
|
|
|
|
break;
|
|
|
|
case SYS_RES_MEMORY:
|
1999-10-25 23:17:24 +00:00
|
|
|
{
|
|
|
|
struct mem_desc *mp = &devi->slt->mem[rid];
|
|
|
|
mp->flags &= ~IODF_ACTIVE;
|
|
|
|
err = pcic_memory(devi->slt, rid);
|
|
|
|
if (err) {
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
1999-10-25 02:41:58 +00:00
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
err = bus_generic_deactivate_resource(dev, child, type, rid, r);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
pcic_setup_intr(device_t dev, device_t child, struct resource *irq,
|
|
|
|
int flags, driver_intr_t *intr, void *arg, void **cookiep)
|
|
|
|
{
|
|
|
|
return (bus_generic_setup_intr(dev, child, irq, flags, intr, arg,
|
|
|
|
cookiep));
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
pcic_teardown_intr(device_t dev, device_t child, struct resource *irq,
|
|
|
|
void *cookie)
|
|
|
|
{
|
|
|
|
return (bus_generic_teardown_intr(dev, child, irq, cookie));
|
|
|
|
}
|
|
|
|
|
1999-10-15 17:29:21 +00:00
|
|
|
static device_method_t pcic_methods[] = {
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|
|
|
/* Device interface */
|
|
|
|
DEVMETHOD(device_probe, pcic_probe),
|
|
|
|
DEVMETHOD(device_attach, bus_generic_attach),
|
|
|
|
DEVMETHOD(device_detach, bus_generic_detach),
|
|
|
|
DEVMETHOD(device_shutdown, bus_generic_shutdown),
|
|
|
|
DEVMETHOD(device_suspend, bus_generic_suspend),
|
|
|
|
DEVMETHOD(device_resume, bus_generic_resume),
|
|
|
|
|
|
|
|
/* Bus interface */
|
|
|
|
DEVMETHOD(bus_print_child, bus_generic_print_child),
|
|
|
|
DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource),
|
|
|
|
DEVMETHOD(bus_release_resource, bus_generic_release_resource),
|
1999-10-25 02:41:58 +00:00
|
|
|
DEVMETHOD(bus_activate_resource, pcic_activate_resource),
|
|
|
|
DEVMETHOD(bus_deactivate_resource, pcic_deactivate_resource),
|
|
|
|
DEVMETHOD(bus_setup_intr, pcic_setup_intr),
|
|
|
|
DEVMETHOD(bus_teardown_intr, pcic_teardown_intr),
|
1999-10-15 17:29:21 +00:00
|
|
|
|
|
|
|
{ 0, 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
devclass_t pcic_devclass;
|
|
|
|
|
|
|
|
static driver_t pcic_driver = {
|
|
|
|
"pcic",
|
|
|
|
pcic_methods,
|
|
|
|
1, /* no softc */
|
|
|
|
};
|
|
|
|
|
|
|
|
DRIVER_MODULE(pcic, isa, pcic_driver, pcic_devclass, 0, 0);
|