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freebsd-skq/sys/sparc64/include/bus_common.h

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/* -> /*- for license, minor formatting changes
2005-01-07 02:29:27 +00:00
/*-
Add bus_common.h, which contains some definiton that apply to both PCI and SBus. Obtained from: NetBSD
2001-12-30 16:13:05 +00:00
* Copyright (c) 1992, 1993
* The Regents of the University of California. All rights reserved.
*
* This software was developed by the Computer Systems Engineering group
* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
* contributed to Berkeley.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* form: @(#)sbusreg.h 8.1 (Berkeley) 6/11/93
* from: NetBSD: iommureg.h,v 1.6 2001/07/20 00:07:13 eeh Exp
*
* $FreeBSD$
*/
#ifndef _MACHINE_BUS_COMMON_H_
Style(9) fix - use #define<tab> consistently. Approved by: re (kensmith)
2007-09-06 14:56:09 +00:00
#define _MACHINE_BUS_COMMON_H_
Add bus_common.h, which contains some definiton that apply to both PCI and SBus. Obtained from: NetBSD
2001-12-30 16:13:05 +00:00
- Add macros for the states of the interrupt clear registers. - Change INTMAP_VEC() to take an INO as its second argument rather than an INR. The former is what I actually intended with this macro and how it's currently used.
2009-12-22 21:48:18 +00:00
#define INTCLR_PENDING 0x000000003ULL /* Interrupt queued to CPU */
#define INTCLR_RECEIVED 0x000000001ULL /* Interrupt received */
#define INTCLR_IDLE 0x000000000ULL /* Interrupt idle */
Make these constants unsigned which is more appropriate.
2009-12-22 21:42:54 +00:00
#define INTMAP_V 0x080000000ULL /* Interrupt valid (enabled) */
#define INTMAP_TID_MASK 0x07c000000ULL /* UPA target ID */
Style(9) fix - use #define<tab> consistently. Approved by: re (kensmith)
2007-09-06 14:56:09 +00:00
#define INTMAP_TID_SHIFT 26
Make these constants unsigned which is more appropriate.
2009-12-22 21:42:54 +00:00
#define INTMAP_IGN_MASK 0x0000007c0ULL /* Interrupt group no. */
Style(9) fix - use #define<tab> consistently. Approved by: re (kensmith)
2007-09-06 14:56:09 +00:00
#define INTMAP_IGN_SHIFT 6
Make these constants unsigned which is more appropriate.
2009-12-22 21:42:54 +00:00
#define INTMAP_INO_MASK 0x00000003fULL /* Interrupt number */
Style(9) fix - use #define<tab> consistently. Approved by: re (kensmith)
2007-09-06 14:56:09 +00:00
#define INTMAP_INR_MASK (INTMAP_IGN_MASK | INTMAP_INO_MASK)
Make these constants unsigned which is more appropriate.
2009-12-22 21:42:54 +00:00
#define INTMAP_SBUSSLOT_MASK 0x000000018ULL /* SBus slot # */
#define INTMAP_PCIBUS_MASK 0x000000010ULL /* PCI bus number (A or B) */
#define INTMAP_PCISLOT_MASK 0x00000000cULL /* PCI slot # */
#define INTMAP_PCIINT_MASK 0x000000003ULL /* PCI interrupt #A,#B,#C,#D */
#define INTMAP_OBIO_MASK 0x000000020ULL /* Onboard device */
o Revamp the sparc64 interrupt code in order to be able to interface with the INTR_FILTER-enabled MI code. Basically this consists of registering an interrupt controller (of which there can be multiple and optionally different ones either per host-to-foo bridge or shared amongst host-to-foo bridges in any one machine) along with an interrupt vector as specific argument for all the interrupt vectors used by a given host-to-foo bridge (roughly similar to registering interrupt sources on amd64 and i386), providing functions to enable, clear and disable the interrupts of the children beneath the bridge. This also includes: - No longer entering a critical section in tl0_intr() and tl1_intr() for executing interrupt handlers but rather let the handlers enter it themselves so in the case of intr_event_handle() we don't enter a nested critical section. - Adding infrastructure for binding delivery of interrupt vectors to specific CPUs which later on can be interfaced with the code from amd64/i386 for binding interrupts to specific CPUs. - Getting rid of the wrapper hack introduced along the lines of the API changes for INTR_FILTER which as a side-effect caused interrupts associated with ithread handlers only to get the elevated priority of those associated with filters ("fast handlers") (this removes the hack also in the non-INTR_FILTER case). - Disabling (by not clearing) an interrupt in the interrupt controller until all associated handlers have been executed, which is crucial for the typical locking strategy of NIC drivers in order to work correctly in case of shared interrupts. This was a more or less theoretical problem on sparc64 though, as shared interrupts are rather uncommon there except for the on-board SCCs and UARTs. Note that due to the behavior of at least of some of the interrupt controllers used on sparc64 an enable+EOI instead of a disable+EOI approach (as implied by the INTR_FILTER MI code and implemented on other architectures) is used as the latter can cause lost interrupts or in the worst case interrupt starvation. o Correct a typo in sbus_alloc_resource() which caused (pass-through) allocations to only work down to the grandchildren of the bus, which wasn't a real problem so far as we don't support any devices which are great-grandchildren or greater of a U2S bridge, yet. o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4() in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid of some other unneeded members in fhc_softc. Reviewed by: marcel (earlier version) Approved by: re (kensmith)
2007-09-06 19:16:30 +00:00
#define INTIGN(x) (((x) & INTMAP_IGN_MASK) >> INTMAP_IGN_SHIFT)
Style(9) fix - use #define<tab> consistently. Approved by: re (kensmith)
2007-09-06 14:56:09 +00:00
#define INTVEC(x) ((x) & INTMAP_INR_MASK)
#define INTSLOT(x) (((x) >> 3) & 0x7)
Always initialize the UPA target module id in the interrupt mapping register to the one of the processor doing the interrupt setup. This is required since this field is preinitialized to 0, but there exist machines which have no processor with a MID of 0 (e.g. e450s with 1 or 2 processors). Add some more macros for handle the interrupt mapping registers, and rename some existing ones for consistency. Approved by: re
2002-12-01 23:30:26 +00:00
#define INTPRI(x) ((x) & 0x7)
#define INTINO(x) ((x) & INTMAP_INO_MASK)
o Rename ic_eoi to ic_clear to emphasize the functions it points don't send and EOI which works like on amd64/i386 and blocks all interrupts on the relevant interrupt controller. o Replace the post_filter and post_inthread hooks registered when creating the interrupt events with just ic_clear as on sparc64 we don't need to do any disable->EOI->enable dance to unblock all but the relevant interrupt while running the filter or handler; just not clearing the interrupt already has the same effect. o Merge from amd64/i386: - Split the intr_table_lock into an sx lock used for most things, and a spin lock to protect intrcnt_index. - Add support for binding interrupts to CPUs, including for the bus_bind_intr(9) interface, a assign_cpu hook and initially shuffling interrupts arround in a round-robin fashion. Reviewed by: jhb MFC after: 1 month
2008-04-23 20:04:38 +00:00
#define INTMAP_ENABLE(mr, mid) \
(INTMAP_TID((mr), (mid)) | INTMAP_V)
#define INTMAP_TID(mr, mid) \
(((mr) & ~INTMAP_TID_MASK) | ((mid) << INTMAP_TID_SHIFT))
- Add macros for the states of the interrupt clear registers. - Change INTMAP_VEC() to take an INO as its second argument rather than an INR. The former is what I actually intended with this macro and how it's currently used.
2009-12-22 21:48:18 +00:00
#define INTMAP_VEC(ign, ino) \
o Rename ic_eoi to ic_clear to emphasize the functions it points don't send and EOI which works like on amd64/i386 and blocks all interrupts on the relevant interrupt controller. o Replace the post_filter and post_inthread hooks registered when creating the interrupt events with just ic_clear as on sparc64 we don't need to do any disable->EOI->enable dance to unblock all but the relevant interrupt while running the filter or handler; just not clearing the interrupt already has the same effect. o Merge from amd64/i386: - Split the intr_table_lock into an sx lock used for most things, and a spin lock to protect intrcnt_index. - Add support for binding interrupts to CPUs, including for the bus_bind_intr(9) interface, a assign_cpu hook and initially shuffling interrupts arround in a round-robin fashion. Reviewed by: jhb MFC after: 1 month
2008-04-23 20:04:38 +00:00
((((ign) << INTMAP_IGN_SHIFT) & INTMAP_IGN_MASK) | \
- Add macros for the states of the interrupt clear registers. - Change INTMAP_VEC() to take an INO as its second argument rather than an INR. The former is what I actually intended with this macro and how it's currently used.
2009-12-22 21:48:18 +00:00
((ino) & INTMAP_INO_MASK))
Add bus_common.h, which contains some definiton that apply to both PCI and SBus. Obtained from: NetBSD
2001-12-30 16:13:05 +00:00
Add support for the counter-timer which is included in the Sun U2S and U2P bridges as a time counter.
2002-02-13 16:16:36 +00:00
/* counter-timer support. */
- Use the name returned by device_get_nameunit(9) for the name of the counter-timer timecounter so the associated SYSCTL nodes don't clash on machines having multiple U2P and U2S bridges as well as establishing a clear mapping between these bridges and their timecounter device. - Don't bother setting up a "nice" name for the IOMMU, just use the name returned by device_get_nameunit(9), too. - Fix some minor style(9) bugs. - Use __FBSDID in counter.c MFC after: 1 week
2008-05-07 21:22:15 +00:00
void sparc64_counter_init(const char *name, bus_space_tag_t tag,
bus_space_handle_t handle, bus_addr_t offset);
Add support for the counter-timer which is included in the Sun U2S and U2P bridges as a time counter.
2002-02-13 16:16:36 +00:00
Add bus_common.h, which contains some definiton that apply to both PCI and SBus. Obtained from: NetBSD
2001-12-30 16:13:05 +00:00
#endif /* !_MACHINE_BUS_COMMON_H_ */
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