187 lines
8.7 KiB
C
187 lines
8.7 KiB
C
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/* $NetBSD: nsphyterreg.h,v 1.4 2005/12/11 12:22:42 christos Exp $ */
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/*-
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* Copyright (c) 1999, 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _DEV_MII_NSPHYTERREG_H_
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#define _DEV_MII_NSPHYTERREG_H_
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/*
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* DP83843 registers; We also have the MacPHYTER (DP83815) internal
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* PHY register definitions here, since the two are, for our purposes,
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* compatible.
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*/
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#define MII_NSPHYTER_PHYSTS 0x10 /* PHY status */
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#define PHYSTS_REL 0x8000 /* receive error latch */
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#define PHYSTS_CIML 0x4000 /* CIM latch */
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#define PHYSTS_FCSL 0x2000 /* false carrier sense latch */
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#define PHYSTS_DEVRDY 0x0800 /* device ready */
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#define PHYSTS_PGRX 0x0400 /* page received */
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#define PHYSTS_ANEGEN 0x0200 /* autoneg. enabled */
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#define PHYSTS_MIIINTR 0x0100 /* MII interrupt */
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#define PHYSTS_REMFAULT 0x0080 /* remote fault */
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#define PHYSTS_JABBER 0x0040 /* jabber detect */
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#define PHYSTS_NWAYCOMP 0x0020 /* NWAY complete */
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#define PHYSTS_RESETSTAT 0x0010 /* reset status */
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#define PHYSTS_LOOPBACK 0x0008 /* loopback status */
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#define PHYSTS_DUPLEX 0x0004 /* full duplex */
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#define PHYSTS_SPEED10 0x0002 /* speed == 10Mb/s */
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#define PHYSTS_LINK 0x0001 /* link up */
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/* Below are the MacPHYTER bits that are different. */
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#define PHYSTS_MP_REL 0x2000 /* receive error latch */
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#define PHYSTS_MP_POLARITY 0x1000 /* polarity inverted */
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#define PHYSTS_MP_FCSL 0x0800 /* false carrier sense latch */
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#define PHYSTS_MP_SIGNAL 0x0400 /* signal detect */
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#define PHYSTS_MP_DESCRLK 0x0200 /* de-scrambler lock */
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#define PHYSTS_MP_PGRX 0x0100 /* page received */
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#define PHYSTS_MP_MIIINTR 0x0080 /* MII interrupt */
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#define PHYSTS_MP_REMFAULT 0x0040 /* remote fault */
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#define PHYSTS_MP_JABBER 0x0020 /* jabber detect */
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#define PHYSTS_MP_NWAYCOMP 0x0010 /* NWAY complete */
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#define MII_NSPHYTER_MIPSCR 0x11 /* MII interrupt PHY specific
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control */
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#define MIPSCR_INTEN 0x0002 /* interrupt enable */
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#define MIPSCR_TINT 0x0001 /* test interrupt */
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#define MII_NSPHYTER_MIPGSR 0x12 /* MII interrupt PHY generic
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status */
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#define MIPGSR_MINT 0x8000 /* MII interrupt pending */
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/* The bits below are MacPHYTER only. */
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#define MIPGSR_MSK_LINK 0x4000 /* mask link status event */
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#define MIPGSR_MSK_JAB 0x2000 /* mask jabber event */
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#define MIPGSR_MSK_RF 0x1000 /* mask remote fault event */
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#define MIPGSR_MSK_ANC 0x0800 /* mask auto-neg complete event */
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#define MIPGSR_MSK_FHF 0x0400 /* mask false carrier half full event */
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#define MIPGSR_MSK_RHF 0x0200 /* mask RX error half full event */
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#define MII_NSPHYTER_DCR 0x13 /* Disconnect counter */
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#define MII_NSPHYTER_FCSCR 0x14 /* False carrier sense counter */
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#define MII_NSPHYTER_RECR 0x15 /* Receive error counter */
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#define MII_NSPHYTER_PCSR 0x16 /* PCS configuration and status */
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#define PCSR_SINGLE_SD 0x8000 /* single-ended SD mode */
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#define PCSR_FEFI_EN 0x4000 /* far end fault indication mode */
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#define PCSR_DESCR_TO_RST 0x2000 /* reset descrambler timeout counter */
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#define PCSR_DESCR_TO_SEL 0x1000 /* descrambler timer mode */
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#define PCSR_DESCR_TO_DIS 0x0800 /* descrambler timer disable */
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#define PCSR_LD_SCR_SD 0x0400 /* load scrambler seed */
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#define PCSR_TX_QUIET 0x0200 /* 100Mb/s transmit true quiet mode */
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#define PCSR_TX_PATTERN 0x0180 /* 100Mb/s transmit test pattern */
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#define PCSR_F_LINK_100 0x0040 /* force good link in 100Mb/s */
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#define PCSR_CIM_DIS 0x0020 /* carrier integrity monitor disable */
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#define PCSR_CIM_STATUS 0x0010 /* carrier integrity monitor status */
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#define PCSR_CODE_ERR 0x0008 /* code errors */
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#define PCSR_PME_ERR 0x0004 /* premature end errors */
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#define PCSR_LINK_ERR 0x0002 /* link errors */
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#define PCSR_PKT_ERR 0x0001 /* packet errors */
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/* Below are the MacPHYTER bits that are different. */
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#define PCSR_MP_BYP_4B5B 0x1000 /* bypass encoder */
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#define PCSR_MP_FREE_CLK 0x0800 /* free funning RX clock */
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#define PCSR_MP_TQ_EN 0x0400 /* enable True Quiet mode */
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#define PCSR_MP_SD_FORCE_B 0x0200 /* force signal detection */
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#define PCSR_MP_SD_OPTION 0x0100 /* enhanced signal detection alg. */
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#define PCSR_MP_NRZI_BYPASS 0x0004 /* NRZI bypass enabled */
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/* The bits below are not on MacPHYTER. */
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#define MII_NSPHYTER_LBR 0x17 /* loopback and bypass */
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#define LBR_BP_STRETCH 0x4000 /* bypass LED stretching */
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#define LBR_BP_4B5B 0x2000 /* bypass encoding/decoding */
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#define LBR_BP_SCR 0x1000 /* bypass scrambler/descrambler */
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#define LBR_BP_RX 0x0800 /* bypass receive function */
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#define LBR_BP_TX 0x0400 /* bypass transmit function */
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#define LBR_100_DP_CTL 0x0380 /* 100Mb/s data patch control */
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#define LBR_TW_LBEN 0x0020 /* TWISTER loopback enable */
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#define LBR_10_ENDEC_LB 0x0010 /* 10Mb/s ENDEC loopback */
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/* The bits below are not on MacPHYTER. */
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#define MII_NSPHYTER_10BTSCR 0x18 /* 10baseT status and control */
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#define BTSCR_AUI_TPI 0x2000 /* TREX operating mode */
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#define BTSCR_RX_SERIAL 0x1000 /* 10baseT RX serial mode */
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#define BTSCR_TX_SERIAL 0x0800 /* 10baseT TX serial mode */
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#define BTSCR_POL_DS 0x0400 /* polarity detection and correction
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disable */
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#define BTSCR_AUTOSW_EN 0x0200 /* AUI/TPI autoswitch */
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#define BTSCR_LP_DS 0x0100 /* link pulse disable */
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#define BTSCR_HB_DS 0x0080 /* heartbeat disabled */
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#define BTSCR_LS_SEL 0x0040 /* low squelch select */
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#define BTSCR_AUI_SEL 0x0020 /* AUI select */
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#define BTSCR_JAB_DS 0x0010 /* jabber disable */
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#define BTSCR_THIN_SEL 0x0008 /* thin ethernet select */
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#define BTSCR_TX_FILT_DS 0x0004 /* TPI receive filter disable */
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#define MII_NSPHYTER_PHYCTRL 0x19 /* PHY control */
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#define PHYCTRL_TW_EQSEL 0x3000 /* TWISTER e.q. select */
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#define PHYCTRL_BLW_DS 0x0800 /* TWISTER base line wander disable */
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#define PHYCTRL_REPEATER 0x0200 /* repeater mode */
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#define PHYCTRL_LED_TXRX_MODE 0x0180 /* LED TX/RX mode */
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#define PHYCTRL_LED_DUP_MODE 0x0040 /* LED DUP mode */
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#define PHYCTRL_FX_EN 0x0020 /* Fiber mode enable */
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#define PHYCTRL_PHYADDR 0x001f /* PHY address */
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/* Below are the MacPHYTER bits that are different. */
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#define PHYCRTL_MP_PSR_15 0x0800 /* BIST sequence select */
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#define PHYCTRL_MP_BIST_STAT 0x0400 /* BIST passed */
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#define PHYCTRL_MP_BIST_START 0x0200 /* start BIST */
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#define PHYCTRL_MP_BP_STRETCH 0x0100 /* bypass LED stretching */
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#define PHYCTRL_MP_PAUSE_STS 0x0080 /* pause status */
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/* The bits below are MacPHYTER only. */
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#define MII_MACPHYTER_TBTCTL 0x1a /* 10baseT Control */
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#define TBTCTL_LOOPBACK_10_DIS 0x0100 /* loopback 10Mb/s disable */
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#define TBTCTL_LP_DIS 0x0080 /* link pulse disable */
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#define TBTCTL_FORCE_LINK_10 0x0040 /* force 10Mb/s link good */
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#define TBTCTL_FORCE_POL_COR 0x0020 /* force polarity correction */
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#define TBTCTL_INV_POLARITY 0x0010 /* inverted polarity */
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#define TBTCTL_AUTOPOL_DIS 0x0008 /* auto-polarity disable */
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#define TBTCTL_HEARTBEAT_DIS 0x0002 /* heartbeat disable */
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#define TBTCTL_JABBER_DIS 0x0001 /* jabber disable */
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#endif /* _DEV_MII_NSPHYTERREG_H_ */
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