2010-07-20 07:11:19 +00:00
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/***********************license start***************
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2012-03-11 04:14:00 +00:00
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* Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights
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2010-11-28 06:20:41 +00:00
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* reserved.
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2010-07-20 07:11:19 +00:00
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*
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*
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2010-11-28 06:20:41 +00:00
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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2010-07-20 07:11:19 +00:00
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*
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2010-11-28 06:20:41 +00:00
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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2010-07-20 07:11:19 +00:00
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*
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2010-11-28 06:20:41 +00:00
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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2012-03-11 04:14:00 +00:00
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* * Neither the name of Cavium Inc. nor the names of
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2010-11-28 06:20:41 +00:00
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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* This Software, including technical data, may be subject to U.S. export control
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* laws, including the U.S. Export Administration Act and its associated
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* regulations, and may be subject to export or import regulations in other
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* countries.
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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2012-03-11 04:14:00 +00:00
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* AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
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2010-11-28 06:20:41 +00:00
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* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
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* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
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* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
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* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
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* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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2010-07-20 07:11:19 +00:00
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***********************license end**************************************/
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2010-11-28 06:20:41 +00:00
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2010-07-20 07:11:19 +00:00
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/**
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* @file
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*
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* Functions for XAUI initialization, configuration,
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* and monitoring.
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*
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2012-03-11 04:14:00 +00:00
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* <hr>$Revision: 70030 $<hr>
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2010-07-20 07:11:19 +00:00
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*/
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2010-11-28 06:20:41 +00:00
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#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
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#include <asm/octeon/cvmx.h>
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#include <asm/octeon/cvmx-config.h>
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#ifdef CVMX_ENABLE_PKO_FUNCTIONS
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2012-03-11 04:14:00 +00:00
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#include <asm/octeon/cvmx-qlm.h>
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2010-11-28 06:20:41 +00:00
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#include <asm/octeon/cvmx-helper.h>
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2012-03-11 04:14:00 +00:00
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#include <asm/octeon/cvmx-helper-cfg.h>
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2010-11-28 06:20:41 +00:00
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#endif
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#include <asm/octeon/cvmx-gmxx-defs.h>
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#include <asm/octeon/cvmx-pko-defs.h>
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2012-03-11 04:14:00 +00:00
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#include <asm/octeon/cvmx-pcsx-defs.h>
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2010-11-28 06:20:41 +00:00
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#include <asm/octeon/cvmx-pcsxx-defs.h>
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#include <asm/octeon/cvmx-ciu-defs.h>
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#else
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2010-11-28 08:18:16 +00:00
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#if !defined(__FreeBSD__) || !defined(_KERNEL)
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2010-07-20 07:11:19 +00:00
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#include "executive-config.h"
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#include "cvmx-config.h"
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2010-11-28 06:20:41 +00:00
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2010-07-20 07:11:19 +00:00
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#ifdef CVMX_ENABLE_PKO_FUNCTIONS
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#include "cvmx.h"
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#include "cvmx-helper.h"
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2012-03-11 04:14:00 +00:00
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#include "cvmx-helper-cfg.h"
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#include "cvmx-qlm.h"
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2010-11-28 08:18:16 +00:00
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#endif
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#else
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2010-07-20 07:11:19 +00:00
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#include "cvmx.h"
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#include "cvmx-helper.h"
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2012-03-11 06:17:49 +00:00
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#include "cvmx-qlm.h"
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2010-11-28 06:20:41 +00:00
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#endif
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#endif
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2010-07-20 07:11:19 +00:00
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Update the port of FreeBSD to Cavium Octeon to use the Cavium Simple Executive
library:
o) Increase inline unit / large function growth limits for MIPS to accommodate
the needs of the Simple Executive, which uses a shocking amount of inlining.
o) Remove TARGET_OCTEON and use CPU_CNMIPS to do things required by cnMIPS and
the Octeon SoC.
o) Add OCTEON_VENDOR_LANNER to use Lanner's allocation of vendor-specific
board numbers, specifically to support the MR320.
o) Add OCTEON_BOARD_CAPK_0100ND to hard-wire configuration for the CAPK-0100nd,
which improperly uses an evaluation board's board number and breaks board
detection at runtime. This board is sold by Portwell as the CAM-0100.
o) Add support for the RTC available on some Octeon boards.
o) Add support for the Octeon PCI bus. Note that rman_[sg]et_virtual for IO
ports can not work unless building for n64.
o) Clean up the CompactFlash driver to use Simple Executive macros and
structures where possible (it would be advisable to use the Simple Executive
API to set the PIO mode, too, but that is not done presently.) Also use
structures from FreeBSD's ATA layer rather than structures copied from
Linux.
o) Print available Octeon SoC features on boot.
o) Add support for the Octeon timecounter.
o) Use the Simple Executive's routines rather than local copies for doing reads
and writes to 64-bit addresses and use its macros for various device
addresses rather than using local copies.
o) Rename octeon_board_real to octeon_is_simulation to reduce differences with
Cavium-provided code originally written for Linux. Also make it use the
same simplified test that the Simple Executive and Linux both use rather
than our complex one.
o) Add support for the Octeon CIU, which is the main interrupt unit, as a bus
to use normal interrupt allocation and setup routines.
o) Use the Simple Executive's bootmem facility to allocate physical memory for
the kernel, rather than assuming we know which addresses we can steal.
NB: This may reduce the amount of RAM the kernel reports you as having if
you are leaving large temporary allocations made by U-Boot allocated
when starting FreeBSD.
o) Add a port of the Cavium-provided Ethernet driver for Linux. This changes
Ethernet interface naming from rgmxN to octeN. The new driver has vast
improvements over the old one, both in performance and functionality, but
does still have some features which have not been ported entirely and there
may be unimplemented code that can be hit in everyday use. I will make
every effort to correct those as they are reported.
o) Support loading the kernel on non-contiguous cores.
o) Add very conservative support for harvesting randomness from the Octeon
random number device.
o) Turn SMP on by default.
o) Clean up the style of the Octeon kernel configurations a little and make
them compile with -march=octeon.
o) Add support for the Lanner MR320 and the CAPK-0100nd to the Simple
Executive.
o) Modify the Simple Executive to build on FreeBSD and to build without
executive-config.h or cvmx-config.h. In the future we may want to
revert part of these changes and supply executive-config.h and
cvmx-config.h and access to the options contained in those files via
kernel configuration files.
o) Modify the Simple Executive USB routines to support getting and setting
of the USB PID.
2010-07-20 19:25:11 +00:00
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#ifdef CVMX_ENABLE_PKO_FUNCTIONS
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2010-07-20 07:11:19 +00:00
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2012-03-11 04:14:00 +00:00
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int __cvmx_helper_xaui_enumerate(int interface)
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{
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union cvmx_gmxx_hg2_control gmx_hg2_control;
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/* If HiGig2 is enabled return 16 ports, otherwise return 1 port */
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gmx_hg2_control.u64 = cvmx_read_csr(CVMX_GMXX_HG2_CONTROL(interface));
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if (gmx_hg2_control.s.hg2tx_en)
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return 16;
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else
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return 1;
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}
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2010-07-20 07:11:19 +00:00
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/**
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* @INTERNAL
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* Probe a XAUI interface and determine the number of ports
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* connected to it. The XAUI interface should still be down
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* after this call.
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*
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* @param interface Interface to probe
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*
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* @return Number of ports on the interface. Zero to disable.
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*/
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int __cvmx_helper_xaui_probe(int interface)
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{
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int i;
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cvmx_gmxx_inf_mode_t mode;
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2010-11-28 06:20:41 +00:00
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/* CN63XX Pass 1.0 errata G-14395 requires the QLM De-emphasis be programmed */
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if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_0))
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{
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cvmx_ciu_qlm2_t ciu_qlm;
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ciu_qlm.u64 = cvmx_read_csr(CVMX_CIU_QLM2);
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ciu_qlm.s.txbypass = 1;
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ciu_qlm.s.txdeemph = 0x5;
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ciu_qlm.s.txmargin = 0x1a;
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cvmx_write_csr(CVMX_CIU_QLM2, ciu_qlm.u64);
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}
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2012-03-11 04:14:00 +00:00
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/* CN63XX Pass 2.0 and 2.1 errata G-15273 requires the QLM De-emphasis be
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programmed when using a 156.25Mhz ref clock */
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if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0) ||
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OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_1))
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{
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/* Read the QLM speed pins */
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cvmx_mio_rst_boot_t mio_rst_boot;
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mio_rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);
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if (mio_rst_boot.cn63xx.qlm2_spd == 0xb)
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{
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cvmx_ciu_qlm2_t ciu_qlm;
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ciu_qlm.u64 = cvmx_read_csr(CVMX_CIU_QLM2);
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ciu_qlm.s.txbypass = 1;
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ciu_qlm.s.txdeemph = 0xa;
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ciu_qlm.s.txmargin = 0x1f;
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cvmx_write_csr(CVMX_CIU_QLM2, ciu_qlm.u64);
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}
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}
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/* Check if QLM is configured correct for XAUI/RXAUI, verify the
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speed as well as mode */
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if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
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{
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int qlm, status;
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qlm = cvmx_qlm_interface(interface);
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status = cvmx_qlm_get_status(qlm);
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if (status != 2 && status != 10)
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return 0;
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}
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2010-07-20 07:11:19 +00:00
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/* Due to errata GMX-700 on CN56XXp1.x and CN52XXp1.x, the interface
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needs to be enabled before IPD otherwise per port backpressure
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may not work properly */
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mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
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mode.s.en = 1;
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cvmx_write_csr(CVMX_GMXX_INF_MODE(interface), mode.u64);
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__cvmx_helper_setup_gmx(interface, 1);
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2012-03-11 04:14:00 +00:00
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if (!OCTEON_IS_MODEL(OCTEON_CN68XX))
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2010-07-20 07:11:19 +00:00
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{
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2012-03-11 04:14:00 +00:00
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/* Setup PKO to support 16 ports for HiGig2 virtual ports. We're pointing
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all of the PKO packet ports for this interface to the XAUI. This allows
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us to use HiGig2 backpressure per port */
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for (i=0; i<16; i++)
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{
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cvmx_pko_mem_port_ptrs_t pko_mem_port_ptrs;
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pko_mem_port_ptrs.u64 = 0;
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/* We set each PKO port to have equal priority in a round robin
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fashion */
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pko_mem_port_ptrs.s.static_p = 0;
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pko_mem_port_ptrs.s.qos_mask = 0xff;
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/* All PKO ports map to the same XAUI hardware port */
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pko_mem_port_ptrs.s.eid = interface*4;
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pko_mem_port_ptrs.s.pid = interface*16 + i;
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cvmx_write_csr(CVMX_PKO_MEM_PORT_PTRS, pko_mem_port_ptrs.u64);
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}
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2010-07-20 07:11:19 +00:00
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}
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2012-03-11 04:14:00 +00:00
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return __cvmx_helper_xaui_enumerate(interface);
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2010-07-20 07:11:19 +00:00
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}
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/**
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* @INTERNAL
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2012-03-11 04:14:00 +00:00
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* Bringup XAUI interface. After this call packet I/O should be
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* fully functional.
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2010-07-20 07:11:19 +00:00
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*
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* @param interface Interface to bring up
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*
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* @return Zero on success, negative on failure
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*/
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2012-03-11 06:17:49 +00:00
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static int __cvmx_helper_xaui_link_init(int interface)
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2010-07-20 07:11:19 +00:00
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{
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cvmx_gmxx_prtx_cfg_t gmx_cfg;
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cvmx_pcsxx_control1_reg_t xauiCtl;
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cvmx_pcsxx_misc_ctl_reg_t xauiMiscCtl;
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cvmx_gmxx_tx_xaui_ctl_t gmxXauiTxCtl;
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/* (1) Interface has already been enabled. */
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/* (2) Disable GMX. */
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xauiMiscCtl.u64 = cvmx_read_csr(CVMX_PCSXX_MISC_CTL_REG(interface));
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xauiMiscCtl.s.gmxeno = 1;
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cvmx_write_csr (CVMX_PCSXX_MISC_CTL_REG(interface), xauiMiscCtl.u64);
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/* (3) Disable GMX and PCSX interrupts. */
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cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0,interface), 0x0);
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cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), 0x0);
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cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), 0x0);
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/* (4) Bring up the PCSX and GMX reconciliation layer. */
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/* (4)a Set polarity and lane swapping. */
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/* (4)b */
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gmxXauiTxCtl.u64 = cvmx_read_csr (CVMX_GMXX_TX_XAUI_CTL(interface));
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gmxXauiTxCtl.s.dic_en = 1; /* Enable better IFG packing and improves performance */
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gmxXauiTxCtl.s.uni_en = 0;
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cvmx_write_csr (CVMX_GMXX_TX_XAUI_CTL(interface), gmxXauiTxCtl.u64);
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/* (4)c Aply reset sequence */
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xauiCtl.u64 = cvmx_read_csr (CVMX_PCSXX_CONTROL1_REG(interface));
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xauiCtl.s.lo_pwr = 0;
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2012-03-11 04:14:00 +00:00
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/* Errata G-15618 requires disabling PCS soft reset in some OCTEON II models. */
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if (!OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X)
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&& !OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)
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&& !OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_1)
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&& !OCTEON_IS_MODEL(OCTEON_CN66XX_PASS1_X)
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|
|
&& !OCTEON_IS_MODEL(OCTEON_CN68XX))
|
|
|
|
|
xauiCtl.s.reset = 1;
|
2010-07-20 07:11:19 +00:00
|
|
|
cvmx_write_csr (CVMX_PCSXX_CONTROL1_REG(interface), xauiCtl.u64);
|
|
|
|
|
|
|
|
|
|
/* Wait for PCS to come out of reset */
|
|
|
|
|
if (CVMX_WAIT_FOR_FIELD64(CVMX_PCSXX_CONTROL1_REG(interface), cvmx_pcsxx_control1_reg_t, reset, ==, 0, 10000))
|
|
|
|
|
return -1;
|
|
|
|
|
/* Wait for PCS to be aligned */
|
|
|
|
|
if (CVMX_WAIT_FOR_FIELD64(CVMX_PCSXX_10GBX_STATUS_REG(interface), cvmx_pcsxx_10gbx_status_reg_t, alignd, ==, 1, 10000))
|
|
|
|
|
return -1;
|
|
|
|
|
/* Wait for RX to be ready */
|
|
|
|
|
if (CVMX_WAIT_FOR_FIELD64(CVMX_GMXX_RX_XAUI_CTL(interface), cvmx_gmxx_rx_xaui_ctl_t, status, ==, 0, 10000))
|
|
|
|
|
return -1;
|
|
|
|
|
|
|
|
|
|
/* (6) Configure GMX */
|
|
|
|
|
|
|
|
|
|
/* Wait for GMX RX to be idle */
|
|
|
|
|
if (CVMX_WAIT_FOR_FIELD64(CVMX_GMXX_PRTX_CFG(0, interface), cvmx_gmxx_prtx_cfg_t, rx_idle, ==, 1, 10000))
|
|
|
|
|
return -1;
|
|
|
|
|
/* Wait for GMX TX to be idle */
|
|
|
|
|
if (CVMX_WAIT_FOR_FIELD64(CVMX_GMXX_PRTX_CFG(0, interface), cvmx_gmxx_prtx_cfg_t, tx_idle, ==, 1, 10000))
|
|
|
|
|
return -1;
|
|
|
|
|
|
|
|
|
|
/* GMX configure */
|
|
|
|
|
gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
|
|
|
|
|
gmx_cfg.s.speed = 1;
|
|
|
|
|
gmx_cfg.s.speed_msb = 0;
|
|
|
|
|
gmx_cfg.s.slottime = 1;
|
|
|
|
|
cvmx_write_csr(CVMX_GMXX_TX_PRTS(interface), 1);
|
|
|
|
|
cvmx_write_csr(CVMX_GMXX_TXX_SLOT(0, interface), 512);
|
|
|
|
|
cvmx_write_csr(CVMX_GMXX_TXX_BURST(0, interface), 8192);
|
|
|
|
|
cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
|
|
|
|
|
|
|
|
|
|
/* Wait for receive link */
|
|
|
|
|
if (CVMX_WAIT_FOR_FIELD64(CVMX_PCSXX_STATUS1_REG(interface), cvmx_pcsxx_status1_reg_t, rcv_lnk, ==, 1, 10000))
|
|
|
|
|
return -1;
|
|
|
|
|
if (CVMX_WAIT_FOR_FIELD64(CVMX_PCSXX_STATUS2_REG(interface), cvmx_pcsxx_status2_reg_t, xmtflt, ==, 0, 10000))
|
|
|
|
|
return -1;
|
|
|
|
|
if (CVMX_WAIT_FOR_FIELD64(CVMX_PCSXX_STATUS2_REG(interface), cvmx_pcsxx_status2_reg_t, rcvflt, ==, 0, 10000))
|
|
|
|
|
return -1;
|
|
|
|
|
|
|
|
|
|
/* (8) Enable packet reception */
|
|
|
|
|
xauiMiscCtl.s.gmxeno = 0;
|
|
|
|
|
cvmx_write_csr (CVMX_PCSXX_MISC_CTL_REG(interface), xauiMiscCtl.u64);
|
|
|
|
|
|
2012-03-11 04:14:00 +00:00
|
|
|
/* Clear all error interrupts before enabling the interface. */
|
|
|
|
|
cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(0,interface), ~0x0ull);
|
|
|
|
|
cvmx_write_csr(CVMX_GMXX_TX_INT_REG(interface), ~0x0ull);
|
|
|
|
|
cvmx_write_csr(CVMX_PCSXX_INT_REG(interface), ~0x0ull);
|
|
|
|
|
|
|
|
|
|
/* Enable GMX */
|
2010-07-20 07:11:19 +00:00
|
|
|
gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
|
|
|
|
|
gmx_cfg.s.en = 1;
|
|
|
|
|
cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
|
2010-11-28 06:20:41 +00:00
|
|
|
|
2012-03-11 04:14:00 +00:00
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @INTERNAL
|
|
|
|
|
* Bringup and enable a XAUI interface. After this call packet
|
|
|
|
|
* I/O should be fully functional. This is called with IPD
|
|
|
|
|
* enabled but PKO disabled.
|
|
|
|
|
*
|
|
|
|
|
* @param interface Interface to bring up
|
|
|
|
|
*
|
|
|
|
|
* @return Zero on success, negative on failure
|
|
|
|
|
*/
|
|
|
|
|
int __cvmx_helper_xaui_enable(int interface)
|
|
|
|
|
{
|
|
|
|
|
/* Setup PKND and BPID */
|
|
|
|
|
if (octeon_has_feature(OCTEON_FEATURE_PKND))
|
|
|
|
|
{
|
|
|
|
|
cvmx_gmxx_bpid_msk_t bpid_msk;
|
|
|
|
|
cvmx_gmxx_bpid_mapx_t bpid_map;
|
|
|
|
|
cvmx_gmxx_prtx_cfg_t gmxx_prtx_cfg;
|
|
|
|
|
cvmx_gmxx_txx_append_t gmxx_txx_append_cfg;
|
|
|
|
|
|
|
|
|
|
/* Setup PKIND */
|
|
|
|
|
gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
|
|
|
|
|
gmxx_prtx_cfg.s.pknd = cvmx_helper_get_pknd(interface, 0);
|
|
|
|
|
cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmxx_prtx_cfg.u64);
|
|
|
|
|
|
|
|
|
|
/* Setup BPID */
|
|
|
|
|
bpid_map.u64 = cvmx_read_csr(CVMX_GMXX_BPID_MAPX(0, interface));
|
|
|
|
|
bpid_map.s.val = 1;
|
|
|
|
|
bpid_map.s.bpid = cvmx_helper_get_bpid(interface, 0);
|
|
|
|
|
cvmx_write_csr(CVMX_GMXX_BPID_MAPX(0, interface), bpid_map.u64);
|
|
|
|
|
|
|
|
|
|
bpid_msk.u64 = cvmx_read_csr(CVMX_GMXX_BPID_MSK(interface));
|
|
|
|
|
bpid_msk.s.msk_or |= 1;
|
|
|
|
|
bpid_msk.s.msk_and &= ~1;
|
|
|
|
|
cvmx_write_csr(CVMX_GMXX_BPID_MSK(interface), bpid_msk.u64);
|
|
|
|
|
|
|
|
|
|
/* CN68XX adds the padding and FCS in PKO, not GMX */
|
|
|
|
|
gmxx_txx_append_cfg.u64 = cvmx_read_csr(CVMX_GMXX_TXX_APPEND(0, interface));
|
|
|
|
|
gmxx_txx_append_cfg.s.fcs = 0;
|
|
|
|
|
gmxx_txx_append_cfg.s.pad = 0;
|
|
|
|
|
cvmx_write_csr(CVMX_GMXX_TXX_APPEND(0, interface), gmxx_txx_append_cfg.u64);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
__cvmx_helper_xaui_link_init(interface);
|
2010-11-28 06:20:41 +00:00
|
|
|
|
2010-07-20 07:11:19 +00:00
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @INTERNAL
|
|
|
|
|
* Return the link state of an IPD/PKO port as returned by
|
|
|
|
|
* auto negotiation. The result of this function may not match
|
|
|
|
|
* Octeon's link config if auto negotiation has changed since
|
|
|
|
|
* the last call to cvmx_helper_link_set().
|
|
|
|
|
*
|
|
|
|
|
* @param ipd_port IPD/PKO port to query
|
|
|
|
|
*
|
|
|
|
|
* @return Link state
|
|
|
|
|
*/
|
|
|
|
|
cvmx_helper_link_info_t __cvmx_helper_xaui_link_get(int ipd_port)
|
|
|
|
|
{
|
|
|
|
|
int interface = cvmx_helper_get_interface_num(ipd_port);
|
|
|
|
|
cvmx_gmxx_tx_xaui_ctl_t gmxx_tx_xaui_ctl;
|
|
|
|
|
cvmx_gmxx_rx_xaui_ctl_t gmxx_rx_xaui_ctl;
|
|
|
|
|
cvmx_pcsxx_status1_reg_t pcsxx_status1_reg;
|
|
|
|
|
cvmx_helper_link_info_t result;
|
|
|
|
|
|
|
|
|
|
gmxx_tx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface));
|
|
|
|
|
gmxx_rx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RX_XAUI_CTL(interface));
|
|
|
|
|
pcsxx_status1_reg.u64 = cvmx_read_csr(CVMX_PCSXX_STATUS1_REG(interface));
|
|
|
|
|
result.u64 = 0;
|
|
|
|
|
|
|
|
|
|
/* Only return a link if both RX and TX are happy */
|
|
|
|
|
if ((gmxx_tx_xaui_ctl.s.ls == 0) && (gmxx_rx_xaui_ctl.s.status == 0) &&
|
|
|
|
|
(pcsxx_status1_reg.s.rcv_lnk == 1))
|
|
|
|
|
{
|
2012-03-11 04:14:00 +00:00
|
|
|
cvmx_pcsxx_misc_ctl_reg_t misc_ctl;
|
2010-07-20 07:11:19 +00:00
|
|
|
result.s.link_up = 1;
|
|
|
|
|
result.s.full_duplex = 1;
|
2012-03-11 04:14:00 +00:00
|
|
|
if (OCTEON_IS_MODEL(OCTEON_CN68XX))
|
|
|
|
|
{
|
|
|
|
|
cvmx_mio_qlmx_cfg_t qlm_cfg;
|
|
|
|
|
int lanes;
|
|
|
|
|
int qlm = (interface == 1) ? 0 : interface;
|
|
|
|
|
|
|
|
|
|
qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(qlm));
|
|
|
|
|
result.s.speed = cvmx_qlm_get_gbaud_mhz(qlm) * 8 / 10;
|
|
|
|
|
lanes = (qlm_cfg.s.qlm_cfg == 7) ? 2 : 4;
|
|
|
|
|
result.s.speed *= lanes;
|
|
|
|
|
}
|
|
|
|
|
else if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
|
|
|
|
|
{
|
|
|
|
|
int qlm = cvmx_qlm_interface(interface);
|
|
|
|
|
result.s.speed = cvmx_qlm_get_gbaud_mhz(qlm) * 8 / 10;
|
|
|
|
|
result.s.speed *= 4;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
result.s.speed = 10000;
|
|
|
|
|
misc_ctl.u64 = cvmx_read_csr(CVMX_PCSXX_MISC_CTL_REG(interface));
|
|
|
|
|
if (misc_ctl.s.gmxeno)
|
|
|
|
|
__cvmx_helper_xaui_link_init(interface);
|
2010-07-20 07:11:19 +00:00
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
/* Disable GMX and PCSX interrupts. */
|
|
|
|
|
cvmx_write_csr (CVMX_GMXX_RXX_INT_EN(0,interface), 0x0);
|
|
|
|
|
cvmx_write_csr (CVMX_GMXX_TX_INT_EN(interface), 0x0);
|
|
|
|
|
cvmx_write_csr (CVMX_PCSXX_INT_EN_REG(interface), 0x0);
|
|
|
|
|
}
|
|
|
|
|
return result;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @INTERNAL
|
|
|
|
|
* Configure an IPD/PKO port for the specified link state. This
|
|
|
|
|
* function does not influence auto negotiation at the PHY level.
|
|
|
|
|
* The passed link state must always match the link state returned
|
|
|
|
|
* by cvmx_helper_link_get(). It is normally best to use
|
|
|
|
|
* cvmx_helper_link_autoconf() instead.
|
|
|
|
|
*
|
|
|
|
|
* @param ipd_port IPD/PKO port to configure
|
|
|
|
|
* @param link_info The new link state
|
|
|
|
|
*
|
|
|
|
|
* @return Zero on success, negative on failure
|
|
|
|
|
*/
|
|
|
|
|
int __cvmx_helper_xaui_link_set(int ipd_port, cvmx_helper_link_info_t link_info)
|
|
|
|
|
{
|
|
|
|
|
int interface = cvmx_helper_get_interface_num(ipd_port);
|
|
|
|
|
cvmx_gmxx_tx_xaui_ctl_t gmxx_tx_xaui_ctl;
|
|
|
|
|
cvmx_gmxx_rx_xaui_ctl_t gmxx_rx_xaui_ctl;
|
|
|
|
|
|
|
|
|
|
gmxx_tx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface));
|
|
|
|
|
gmxx_rx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RX_XAUI_CTL(interface));
|
|
|
|
|
|
|
|
|
|
/* If the link shouldn't be up, then just return */
|
|
|
|
|
if (!link_info.s.link_up)
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
/* Do nothing if both RX and TX are happy */
|
|
|
|
|
if ((gmxx_tx_xaui_ctl.s.ls == 0) && (gmxx_rx_xaui_ctl.s.status == 0))
|
|
|
|
|
return 0;
|
2012-03-11 04:14:00 +00:00
|
|
|
|
2010-07-20 07:11:19 +00:00
|
|
|
/* Bring the link up */
|
2012-03-11 04:14:00 +00:00
|
|
|
return __cvmx_helper_xaui_link_init(interface);
|
2010-07-20 07:11:19 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @INTERNAL
|
|
|
|
|
* Configure a port for internal and/or external loopback. Internal loopback
|
|
|
|
|
* causes packets sent by the port to be received by Octeon. External loopback
|
|
|
|
|
* causes packets received from the wire to sent out again.
|
|
|
|
|
*
|
|
|
|
|
* @param ipd_port IPD/PKO port to loopback.
|
|
|
|
|
* @param enable_internal
|
|
|
|
|
* Non zero if you want internal loopback
|
|
|
|
|
* @param enable_external
|
|
|
|
|
* Non zero if you want external loopback
|
|
|
|
|
*
|
|
|
|
|
* @return Zero on success, negative on failure.
|
|
|
|
|
*/
|
|
|
|
|
extern int __cvmx_helper_xaui_configure_loopback(int ipd_port, int enable_internal, int enable_external)
|
|
|
|
|
{
|
|
|
|
|
int interface = cvmx_helper_get_interface_num(ipd_port);
|
|
|
|
|
cvmx_pcsxx_control1_reg_t pcsxx_control1_reg;
|
|
|
|
|
cvmx_gmxx_xaui_ext_loopback_t gmxx_xaui_ext_loopback;
|
|
|
|
|
|
|
|
|
|
/* Set the internal loop */
|
|
|
|
|
pcsxx_control1_reg.u64 = cvmx_read_csr(CVMX_PCSXX_CONTROL1_REG(interface));
|
|
|
|
|
pcsxx_control1_reg.s.loopbck1 = enable_internal;
|
|
|
|
|
cvmx_write_csr(CVMX_PCSXX_CONTROL1_REG(interface), pcsxx_control1_reg.u64);
|
|
|
|
|
|
|
|
|
|
/* Set the external loop */
|
|
|
|
|
gmxx_xaui_ext_loopback.u64 = cvmx_read_csr(CVMX_GMXX_XAUI_EXT_LOOPBACK(interface));
|
|
|
|
|
gmxx_xaui_ext_loopback.s.en = enable_external;
|
|
|
|
|
cvmx_write_csr(CVMX_GMXX_XAUI_EXT_LOOPBACK(interface), gmxx_xaui_ext_loopback.u64);
|
|
|
|
|
|
|
|
|
|
/* Take the link through a reset */
|
2012-03-11 04:14:00 +00:00
|
|
|
return __cvmx_helper_xaui_link_init(interface);
|
2010-07-20 07:11:19 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#endif /* CVMX_ENABLE_PKO_FUNCTIONS */
|
|
|
|
|
|