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freebsd-skq/sys/mips/atheros/ar71xx_setup.c

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Preparation work for supporting the AR91xx and AR724x. * Implement a SoC probe function, from Linux, which determines the SoC family, type and revision. This only probes the AR71xx series SoC and (currently) panics on others. * Migrate some of the AR71XX specific hardware init (USB device, determining system frequencies) into using the cpuops introduced in an earlier commit. Other SoC specific hardware stuff (per-device flush/WB, GPIO pin wiring, Ethernet PLL setup, other things I've likely missed) will be introduced in subsequent commits. Reviewed by: imp@ Obtained from: (partially) Linux
2010-08-19 02:03:12 +00:00
/*-
* Copyright (c) 2010 Adrian Chadd
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include "opt_ddb.h"
#include <sys/param.h>
#include <sys/conf.h>
#include <sys/kernel.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/cons.h>
#include <sys/kdb.h>
#include <sys/reboot.h>
#include <vm/vm.h>
#include <vm/vm_page.h>
#include <net/ethernet.h>
#include <machine/clock.h>
#include <machine/cpu.h>
Remove duplicate header includes
2011-06-26 10:07:48 +00:00
#include <machine/cpuregs.h>
Preparation work for supporting the AR91xx and AR724x. * Implement a SoC probe function, from Linux, which determines the SoC family, type and revision. This only probes the AR71xx series SoC and (currently) panics on others. * Migrate some of the AR71XX specific hardware init (USB device, determining system frequencies) into using the cpuops introduced in an earlier commit. Other SoC specific hardware stuff (per-device flush/WB, GPIO pin wiring, Ethernet PLL setup, other things I've likely missed) will be introduced in subsequent commits. Reviewed by: imp@ Obtained from: (partially) Linux
2010-08-19 02:03:12 +00:00
#include <machine/hwfunc.h>
#include <machine/md_var.h>
#include <machine/trap.h>
#include <machine/vmparam.h>
#include <mips/atheros/ar71xxreg.h>
Tie in the AR933x support into -HEAD.
2013-03-28 19:30:56 +00:00
#include <mips/atheros/ar933xreg.h>
Implement some initial AR934x support routines. This code reads the PLL configuration registers and correctly programs things so the UART and such can come up. There's MIPS74k platform issues that need fixing; but this at least brings things up enough to echo stuff out the serial port and allow for interactive debugging with ddb. Tested: * AR71xx SoCs * AR933x SoC * AR9344 board (DB120) Obtained from: Qualcomm Atheros; Linux/OpenWRT
2013-07-21 03:56:57 +00:00
#include <mips/atheros/ar934xreg.h>
Add initial Qualcomm Atheros QCA955x SoC support. This adds the initial frequency poking and configures up enough for it to boot and spit out data over the console. There's still a whole bunch of work to do in the reset path and devices to support this thing, but hey, it's alive! ath> go 0x80050100 ## Starting application at 0x80050100 ... CPU platform: Atheros AR9558 rev 0 CPU Frequency=720 MHz CPU DDR Frequency=600 MHz CPU AHB Frequency=200 MHz platform frequency: 720 MHz CPU reference clock: 0 MHz CPU MDIO clock: 40 MHz Done at: hackathon Obtained from: Linux OpenWRT, Qualcomm Atheros
2015-01-05 02:06:26 +00:00
#include <mips/atheros/qca955xreg.h>
Add initial support for the QCA953x ("Honeybee") from Qualcomm Atheros. The QCA953x SoC is an integrated 2x2 2GHz 11n + MIPS24k core, with a 5 port FE switch, gige WAN port, and all the same stuff you'd find on its predecessor - the AR9331. However, buried deep in here somewhere is also a PCIe EP/RC for various applications and some other weird bits I don't yet know about. This is enough to get the reference board up and booting. I haven't yet had it pass lots of packets - I need to finalise the ethernet switch bits and the GMAC configuration (ie, how the ethernet ports and switch are wired up) and I'll bring that in when I commit the base configuration files to use the thing. The wifi stuff will come much later. I have to port that support from Linux ath9k and extend our vendor HAL to support it. The reference board (AP143) comes with 32MB RAM and 4MB flash, so in order to use it I need to get USB working fully so I can run root from there. Thankyou to Qualcomm Atheros for access to the reference design board. Details: * Add register definitions from openwrt; * It looks like a QCA955x but shrunk down to a QCA933x footprint, so use the QCA955x bits and fix up the clock detection code to do the QCA953x bits (they're very subtly different); * Teach GPIO about it; * Teach EHCI about it; * Teach if_arge about it; * Teach the CPU detection code about it. Tested: * AP143, QCA9533v2 SoC Obtained from: Linux, Linux OpenWRT
2015-11-16 04:28:00 +00:00
#include <mips/atheros/qca953xreg.h>
Tie in the AR933x support into -HEAD.
2013-03-28 19:30:56 +00:00
Preparation work for supporting the AR91xx and AR724x. * Implement a SoC probe function, from Linux, which determines the SoC family, type and revision. This only probes the AR71xx series SoC and (currently) panics on others. * Migrate some of the AR71XX specific hardware init (USB device, determining system frequencies) into using the cpuops introduced in an earlier commit. Other SoC specific hardware stuff (per-device flush/WB, GPIO pin wiring, Ethernet PLL setup, other things I've likely missed) will be introduced in subsequent commits. Reviewed by: imp@ Obtained from: (partially) Linux
2010-08-19 02:03:12 +00:00
#include <mips/atheros/ar71xx_setup.h>
#include <mips/atheros/ar71xx_cpudef.h>
#include <mips/atheros/ar71xx_chip.h>
Add some initial AR724X chipset support. This is untested but should at least allow an AR724X to boot. The current code is lacking the detail needed to expose the PCIe bus. It is also lacking any NIC, PLL or flush/WB code.
2010-08-19 11:53:55 +00:00
#include <mips/atheros/ar724x_chip.h>
Add initial Atheros AR91XX support. This works well enough to bring a system up to single-user mode using an MDROOT. Known Issues: * The EHCI USB doesn't currently work and will panic the kernel during attach. * The onboard ethernet won't work until the PLL routines have been fleshed out and shoe-horned into if_arge. * The WMAC device glue (and quite likely the if_ath support) hasn't yet been implemented.
2010-08-19 11:40:10 +00:00
#include <mips/atheros/ar91xx_chip.h>
Tie in the AR933x support into -HEAD.
2013-03-28 19:30:56 +00:00
#include <mips/atheros/ar933x_chip.h>
Implement some initial AR934x support routines. This code reads the PLL configuration registers and correctly programs things so the UART and such can come up. There's MIPS74k platform issues that need fixing; but this at least brings things up enough to echo stuff out the serial port and allow for interactive debugging with ddb. Tested: * AR71xx SoCs * AR933x SoC * AR9344 board (DB120) Obtained from: Qualcomm Atheros; Linux/OpenWRT
2013-07-21 03:56:57 +00:00
#include <mips/atheros/ar934x_chip.h>
Add initial support for the QCA953x ("Honeybee") from Qualcomm Atheros. The QCA953x SoC is an integrated 2x2 2GHz 11n + MIPS24k core, with a 5 port FE switch, gige WAN port, and all the same stuff you'd find on its predecessor - the AR9331. However, buried deep in here somewhere is also a PCIe EP/RC for various applications and some other weird bits I don't yet know about. This is enough to get the reference board up and booting. I haven't yet had it pass lots of packets - I need to finalise the ethernet switch bits and the GMAC configuration (ie, how the ethernet ports and switch are wired up) and I'll bring that in when I commit the base configuration files to use the thing. The wifi stuff will come much later. I have to port that support from Linux ath9k and extend our vendor HAL to support it. The reference board (AP143) comes with 32MB RAM and 4MB flash, so in order to use it I need to get USB working fully so I can run root from there. Thankyou to Qualcomm Atheros for access to the reference design board. Details: * Add register definitions from openwrt; * It looks like a QCA955x but shrunk down to a QCA933x footprint, so use the QCA955x bits and fix up the clock detection code to do the QCA953x bits (they're very subtly different); * Teach GPIO about it; * Teach EHCI about it; * Teach if_arge about it; * Teach the CPU detection code about it. Tested: * AP143, QCA9533v2 SoC Obtained from: Linux, Linux OpenWRT
2015-11-16 04:28:00 +00:00
#include <mips/atheros/qca953x_chip.h>
Add initial Qualcomm Atheros QCA955x SoC support. This adds the initial frequency poking and configures up enough for it to boot and spit out data over the console. There's still a whole bunch of work to do in the reset path and devices to support this thing, but hey, it's alive! ath> go 0x80050100 ## Starting application at 0x80050100 ... CPU platform: Atheros AR9558 rev 0 CPU Frequency=720 MHz CPU DDR Frequency=600 MHz CPU AHB Frequency=200 MHz platform frequency: 720 MHz CPU reference clock: 0 MHz CPU MDIO clock: 40 MHz Done at: hackathon Obtained from: Linux OpenWRT, Qualcomm Atheros
2015-01-05 02:06:26 +00:00
#include <mips/atheros/qca955x_chip.h>
Remove duplicate header includes
2011-06-26 10:07:48 +00:00
Preparation work for supporting the AR91xx and AR724x. * Implement a SoC probe function, from Linux, which determines the SoC family, type and revision. This only probes the AR71xx series SoC and (currently) panics on others. * Migrate some of the AR71XX specific hardware init (USB device, determining system frequencies) into using the cpuops introduced in an earlier commit. Other SoC specific hardware stuff (per-device flush/WB, GPIO pin wiring, Ethernet PLL setup, other things I've likely missed) will be introduced in subsequent commits. Reviewed by: imp@ Obtained from: (partially) Linux
2010-08-19 02:03:12 +00:00
#define AR71XX_SYS_TYPE_LEN 128
static char ar71xx_sys_type[AR71XX_SYS_TYPE_LEN];
enum ar71xx_soc_type ar71xx_soc;
struct ar71xx_cpu_def * ar71xx_cpu_ops = NULL;
void
ar71xx_detect_sys_type(void)
{
char *chip = "????";
uint32_t id;
uint32_t major;
uint32_t minor;
uint32_t rev = 0;
id = ATH_READ_REG(AR71XX_RST_RESET_REG_REV_ID);
major = id & REV_ID_MAJOR_MASK;
switch (major) {
case REV_ID_MAJOR_AR71XX:
minor = id & AR71XX_REV_ID_MINOR_MASK;
rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
rev &= AR71XX_REV_ID_REVISION_MASK;
Fix mistaken indenting.
2010-08-19 12:52:49 +00:00
ar71xx_cpu_ops = &ar71xx_chip_def;
Preparation work for supporting the AR91xx and AR724x. * Implement a SoC probe function, from Linux, which determines the SoC family, type and revision. This only probes the AR71xx series SoC and (currently) panics on others. * Migrate some of the AR71XX specific hardware init (USB device, determining system frequencies) into using the cpuops introduced in an earlier commit. Other SoC specific hardware stuff (per-device flush/WB, GPIO pin wiring, Ethernet PLL setup, other things I've likely missed) will be introduced in subsequent commits. Reviewed by: imp@ Obtained from: (partially) Linux
2010-08-19 02:03:12 +00:00
switch (minor) {
case AR71XX_REV_ID_MINOR_AR7130:
ar71xx_soc = AR71XX_SOC_AR7130;
chip = "7130";
break;
case AR71XX_REV_ID_MINOR_AR7141:
ar71xx_soc = AR71XX_SOC_AR7141;
chip = "7141";
break;
case AR71XX_REV_ID_MINOR_AR7161:
ar71xx_soc = AR71XX_SOC_AR7161;
chip = "7161";
break;
}
break;
Add some initial AR724X chipset support. This is untested but should at least allow an AR724X to boot. The current code is lacking the detail needed to expose the PCIe bus. It is also lacking any NIC, PLL or flush/WB code.
2010-08-19 11:53:55 +00:00
case REV_ID_MAJOR_AR7240:
ar71xx_soc = AR71XX_SOC_AR7240;
chip = "7240";
Fix mistaken indenting.
2010-08-19 12:52:49 +00:00
ar71xx_cpu_ops = &ar724x_chip_def;
Add some initial AR724X chipset support. This is untested but should at least allow an AR724X to boot. The current code is lacking the detail needed to expose the PCIe bus. It is also lacking any NIC, PLL or flush/WB code.
2010-08-19 11:53:55 +00:00
rev = (id & AR724X_REV_ID_REVISION_MASK);
break;
case REV_ID_MAJOR_AR7241:
ar71xx_soc = AR71XX_SOC_AR7241;
chip = "7241";
Fix mistaken indenting.
2010-08-19 12:52:49 +00:00
ar71xx_cpu_ops = &ar724x_chip_def;
Add some initial AR724X chipset support. This is untested but should at least allow an AR724X to boot. The current code is lacking the detail needed to expose the PCIe bus. It is also lacking any NIC, PLL or flush/WB code.
2010-08-19 11:53:55 +00:00
rev = (id & AR724X_REV_ID_REVISION_MASK);
break;
case REV_ID_MAJOR_AR7242:
ar71xx_soc = AR71XX_SOC_AR7242;
chip = "7242";
Fix mistaken indenting.
2010-08-19 12:52:49 +00:00
ar71xx_cpu_ops = &ar724x_chip_def;
Add some initial AR724X chipset support. This is untested but should at least allow an AR724X to boot. The current code is lacking the detail needed to expose the PCIe bus. It is also lacking any NIC, PLL or flush/WB code.
2010-08-19 11:53:55 +00:00
rev = (id & AR724X_REV_ID_REVISION_MASK);
break;
Add initial Atheros AR91XX support. This works well enough to bring a system up to single-user mode using an MDROOT. Known Issues: * The EHCI USB doesn't currently work and will panic the kernel during attach. * The onboard ethernet won't work until the PLL routines have been fleshed out and shoe-horned into if_arge. * The WMAC device glue (and quite likely the if_ath support) hasn't yet been implemented.
2010-08-19 11:40:10 +00:00
case REV_ID_MAJOR_AR913X:
minor = id & AR91XX_REV_ID_MINOR_MASK;
rev = id >> AR91XX_REV_ID_REVISION_SHIFT;
rev &= AR91XX_REV_ID_REVISION_MASK;
Fix mistaken indenting.
2010-08-19 12:52:49 +00:00
ar71xx_cpu_ops = &ar91xx_chip_def;
Add initial Atheros AR91XX support. This works well enough to bring a system up to single-user mode using an MDROOT. Known Issues: * The EHCI USB doesn't currently work and will panic the kernel during attach. * The onboard ethernet won't work until the PLL routines have been fleshed out and shoe-horned into if_arge. * The WMAC device glue (and quite likely the if_ath support) hasn't yet been implemented.
2010-08-19 11:40:10 +00:00
switch (minor) {
case AR91XX_REV_ID_MINOR_AR9130:
ar71xx_soc = AR71XX_SOC_AR9130;
chip = "9130";
break;
case AR91XX_REV_ID_MINOR_AR9132:
ar71xx_soc = AR71XX_SOC_AR9132;
chip = "9132";
break;
}
break;
Tie in the AR933x support into -HEAD.
2013-03-28 19:30:56 +00:00
case REV_ID_MAJOR_AR9330:
minor = 0;
rev = (id & AR933X_REV_ID_REVISION_MASK);
chip = "9330";
ar71xx_cpu_ops = &ar933x_chip_def;
* Add AR9330/AR9331 to the soc identifier enum; * Set it when probing the CPU type.
2013-04-05 00:22:17 +00:00
ar71xx_soc = AR71XX_SOC_AR9330;
Tie in the AR933x support into -HEAD.
2013-03-28 19:30:56 +00:00
break;
case REV_ID_MAJOR_AR9331:
minor = 1;
rev = (id & AR933X_REV_ID_REVISION_MASK);
chip = "9331";
* Add AR9330/AR9331 to the soc identifier enum; * Set it when probing the CPU type.
2013-04-05 00:22:17 +00:00
ar71xx_soc = AR71XX_SOC_AR9331;
Tie in the AR933x support into -HEAD.
2013-03-28 19:30:56 +00:00
ar71xx_cpu_ops = &ar933x_chip_def;
break;
Add initial Atheros AR91XX support. This works well enough to bring a system up to single-user mode using an MDROOT. Known Issues: * The EHCI USB doesn't currently work and will panic the kernel during attach. * The onboard ethernet won't work until the PLL routines have been fleshed out and shoe-horned into if_arge. * The WMAC device glue (and quite likely the if_ath support) hasn't yet been implemented.
2010-08-19 11:40:10 +00:00
Implement some initial AR934x support routines. This code reads the PLL configuration registers and correctly programs things so the UART and such can come up. There's MIPS74k platform issues that need fixing; but this at least brings things up enough to echo stuff out the serial port and allow for interactive debugging with ddb. Tested: * AR71xx SoCs * AR933x SoC * AR9344 board (DB120) Obtained from: Qualcomm Atheros; Linux/OpenWRT
2013-07-21 03:56:57 +00:00
case REV_ID_MAJOR_AR9341:
minor = 0;
rev = (id & AR934X_REV_ID_REVISION_MASK);
chip = "9341";
ar71xx_soc = AR71XX_SOC_AR9341;
ar71xx_cpu_ops = &ar934x_chip_def;
break;
case REV_ID_MAJOR_AR9342:
minor = 0;
rev = (id & AR934X_REV_ID_REVISION_MASK);
chip = "9342";
ar71xx_soc = AR71XX_SOC_AR9342;
ar71xx_cpu_ops = &ar934x_chip_def;
break;
case REV_ID_MAJOR_AR9344:
minor = 0;
rev = (id & AR934X_REV_ID_REVISION_MASK);
chip = "9344";
ar71xx_soc = AR71XX_SOC_AR9344;
ar71xx_cpu_ops = &ar934x_chip_def;
break;
Add initial support for the QCA953x ("Honeybee") from Qualcomm Atheros. The QCA953x SoC is an integrated 2x2 2GHz 11n + MIPS24k core, with a 5 port FE switch, gige WAN port, and all the same stuff you'd find on its predecessor - the AR9331. However, buried deep in here somewhere is also a PCIe EP/RC for various applications and some other weird bits I don't yet know about. This is enough to get the reference board up and booting. I haven't yet had it pass lots of packets - I need to finalise the ethernet switch bits and the GMAC configuration (ie, how the ethernet ports and switch are wired up) and I'll bring that in when I commit the base configuration files to use the thing. The wifi stuff will come much later. I have to port that support from Linux ath9k and extend our vendor HAL to support it. The reference board (AP143) comes with 32MB RAM and 4MB flash, so in order to use it I need to get USB working fully so I can run root from there. Thankyou to Qualcomm Atheros for access to the reference design board. Details: * Add register definitions from openwrt; * It looks like a QCA955x but shrunk down to a QCA933x footprint, so use the QCA955x bits and fix up the clock detection code to do the QCA953x bits (they're very subtly different); * Teach GPIO about it; * Teach EHCI about it; * Teach if_arge about it; * Teach the CPU detection code about it. Tested: * AP143, QCA9533v2 SoC Obtained from: Linux, Linux OpenWRT
2015-11-16 04:28:00 +00:00
case REV_ID_MAJOR_QCA9533:
minor = 0;
rev = (id & QCA953X_REV_ID_REVISION_MASK);
chip = "9533";
ar71xx_soc = AR71XX_SOC_QCA9533;
ar71xx_cpu_ops = &qca953x_chip_def;
break;
case REV_ID_MAJOR_QCA9533_V2:
minor = 0;
rev = (id & QCA953X_REV_ID_REVISION_MASK);
chip = "9533v2";
ar71xx_soc = AR71XX_SOC_QCA9533_V2;
ar71xx_cpu_ops = &qca953x_chip_def;
break;
Add initial Qualcomm Atheros QCA955x SoC support. This adds the initial frequency poking and configures up enough for it to boot and spit out data over the console. There's still a whole bunch of work to do in the reset path and devices to support this thing, but hey, it's alive! ath> go 0x80050100 ## Starting application at 0x80050100 ... CPU platform: Atheros AR9558 rev 0 CPU Frequency=720 MHz CPU DDR Frequency=600 MHz CPU AHB Frequency=200 MHz platform frequency: 720 MHz CPU reference clock: 0 MHz CPU MDIO clock: 40 MHz Done at: hackathon Obtained from: Linux OpenWRT, Qualcomm Atheros
2015-01-05 02:06:26 +00:00
case REV_ID_MAJOR_QCA9556:
minor = 0;
rev = (id & QCA955X_REV_ID_REVISION_MASK);
chip = "9556";
ar71xx_soc = AR71XX_SOC_QCA9556;
ar71xx_cpu_ops = &qca955x_chip_def;
break;
case REV_ID_MAJOR_QCA9558:
minor = 0;
rev = (id & QCA955X_REV_ID_REVISION_MASK);
chip = "9558";
ar71xx_soc = AR71XX_SOC_QCA9558;
ar71xx_cpu_ops = &qca955x_chip_def;
break;
Preparation work for supporting the AR91xx and AR724x. * Implement a SoC probe function, from Linux, which determines the SoC family, type and revision. This only probes the AR71xx series SoC and (currently) panics on others. * Migrate some of the AR71XX specific hardware init (USB device, determining system frequencies) into using the cpuops introduced in an earlier commit. Other SoC specific hardware stuff (per-device flush/WB, GPIO pin wiring, Ethernet PLL setup, other things I've likely missed) will be introduced in subsequent commits. Reviewed by: imp@ Obtained from: (partially) Linux
2010-08-19 02:03:12 +00:00
default:
panic("ar71xx: unknown chip id:0x%08x\n", id);
}
sprintf(ar71xx_sys_type, "Atheros AR%s rev %u", chip, rev);
}
const char *
ar71xx_get_system_type(void)
{
return ar71xx_sys_type;
}
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