freebsd-skq/sys/dev/ic/i8237.h

/*
 * Intel 8237 DMA Controller
 *
 * $FreeBSD$
 */

#define	DMA37MD_SINGLE	0x40	/* single pass mode */
#define	DMA37MD_CASCADE	0xc0	/* cascade mode */
#define	DMA37MD_AUTO	0x50	/* autoinitialise single pass mode */
#define	DMA37MD_WRITE	0x04	/* read the device, write memory operation */
#define	DMA37MD_READ	0x08	/* write the device, read memory operation */

#ifndef PC98
/*
**  Register definitions for DMA controller 1 (channels 0..3):
*/
#define	DMA1_CHN(c)	(IO_DMA1 + 1*(2*(c)))	/* addr reg for channel c */
#define	DMA1_STATUS	(IO_DMA1 + 1*8)		/* status register */
#define	DMA1_SMSK	(IO_DMA1 + 1*10)	/* single mask register */
#define	DMA1_MODE	(IO_DMA1 + 1*11)	/* mode register */
#define	DMA1_FFC	(IO_DMA1 + 1*12)	/* clear first/last FF */
#define	DMA1_RESET	(IO_DMA1 + 1*13)	/* reset */

/*
**  Register definitions for DMA controller 2 (channels 4..7):
*/
#define	DMA2_CHN(c)	(IO_DMA2 + 2*(2*(c)))	/* addr reg for channel c */
#define	DMA2_STATUS	(IO_DMA2 + 2*8)		/* status register */
#define	DMA2_SMSK	(IO_DMA2 + 2*10)	/* single mask register */
#define	DMA2_MODE	(IO_DMA2 + 2*11)	/* mode register */
#define	DMA2_FFC	(IO_DMA2 + 2*12)	/* clear first/last FF */
#define	DMA2_RESET	(IO_DMA2 + 2*13)	/* reset */
#endif
Initial import, 0.1 + pk 0.2.4-B1 1993-06-12 14:58:17 +00:00			`/*`
			`* Intel 8237 DMA Controller`
Removed all patch kit headers, sccsid and rcsid strings, put $Id$ in, some minor cleanup. Added $Id$ to files that did not have any version info, etc 1993-10-16 13:48:52 +00:00			`*`
$Id$ -> $FreeBSD$ 1999-08-28 01:08:13 +00:00			`* $FreeBSD$`
Initial import, 0.1 + pk 0.2.4-B1 1993-06-12 14:58:17 +00:00			`*/`

			`#define DMA37MD_SINGLE 0x40 /* single pass mode */`
			`#define DMA37MD_CASCADE 0xc0 /* cascade mode */`
DMA automode patch, fix SB16 clicks Submitted by: tim@cs.city.ac.uk 1994-11-01 17:26:50 +00:00			`#define DMA37MD_AUTO 0x50 /* autoinitialise single pass mode */`
Initial import, 0.1 + pk 0.2.4-B1 1993-06-12 14:58:17 +00:00			`#define DMA37MD_WRITE 0x04 /* read the device, write memory operation */`
			`#define DMA37MD_READ 0x08 /* write the device, read memory operation */`
Remove trailing whitespace. 1995-05-30 08:16:23 +00:00
Since we are quite unlikely to ever face another platform which uses the i8237 without trying to emulate the PC architecture move the register definitions for the i8237 chip into the central include file for the chip, except for the PC98 case which is magic. Add new isa_dmatc() function which tells us as cheaply as possible if the terminal count has been reached for a given channel. 2005-02-06 13:46:39 +00:00			`#ifndef PC98`
			`/*`
			`** Register definitions for DMA controller 1 (channels 0..3):`
			`*/`
			`#define DMA1_CHN(c) (IO_DMA1 + 1(2(c))) /* addr reg for channel c */`
			`#define DMA1_STATUS (IO_DMA1 + 18) / status register */`
			`#define DMA1_SMSK (IO_DMA1 + 110) / single mask register */`
			`#define DMA1_MODE (IO_DMA1 + 111) / mode register */`
			`#define DMA1_FFC (IO_DMA1 + 112) / clear first/last FF */`
			`#define DMA1_RESET (IO_DMA1 + 113) / reset */`

			`/*`
			`** Register definitions for DMA controller 2 (channels 4..7):`
			`*/`
			`#define DMA2_CHN(c) (IO_DMA2 + 2(2(c))) /* addr reg for channel c */`
			`#define DMA2_STATUS (IO_DMA2 + 28) / status register */`
			`#define DMA2_SMSK (IO_DMA2 + 210) / single mask register */`
			`#define DMA2_MODE (IO_DMA2 + 211) / mode register */`
			`#define DMA2_FFC (IO_DMA2 + 212) / clear first/last FF */`
			`#define DMA2_RESET (IO_DMA2 + 213) / reset */`
			`#endif`