128 lines
5.1 KiB
C
128 lines
5.1 KiB
C
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/*-
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* Copyright (c) 2002-2006 Sam Leffler, Errno Consulting
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce at minimum a disclaimer
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* similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
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* redistribution must be conditioned upon including a substantially
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* similar Disclaimer requirement for further binary redistribution.
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* 3. Neither the names of the above-listed copyright holders nor the names
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* of any contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* Alternatively, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") version 2 as published by the Free
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* Software Foundation.
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*
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* NO WARRANTY
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
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* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
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* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
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* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGES.
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*
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* $FreeBSD$
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*/
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#ifndef _ATH_AH_OSDEP_H_
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#define _ATH_AH_OSDEP_H_
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/*
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* Atheros Hardware Access Layer (HAL) OS Dependent Definitions.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/endian.h>
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#include <machine/bus.h>
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/*
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* Delay n microseconds.
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*/
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extern void ath_hal_delay(int);
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#define OS_DELAY(_n) ath_hal_delay(_n)
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#define OS_INLINE __inline
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#define OS_MEMZERO(_a, _n) ath_hal_memzero((_a), (_n))
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extern void ath_hal_memzero(void *, size_t);
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#define OS_MEMCPY(_d, _s, _n) ath_hal_memcpy(_d,_s,_n)
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extern void *ath_hal_memcpy(void *, const void *, size_t);
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#define abs(_a) __builtin_abs(_a)
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struct ath_hal;
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extern u_int32_t ath_hal_getuptime(struct ath_hal *);
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#define OS_GETUPTIME(_ah) ath_hal_getuptime(_ah)
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/*
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* Register read/write operations are either handled through
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* platform-dependent routines (or when debugging is enabled
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* with AH_DEBUG); or they are inline expanded using the macros
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* defined below. For public builds we inline expand only for
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* platforms where it is certain what the requirements are to
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* read/write registers--typically they are memory-mapped and
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* no explicit synchronization or memory invalidation operations
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* are required (e.g. i386).
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*/
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#if defined(AH_DEBUG) || defined(AH_REGOPS_FUNC) || defined(AH_DEBUG_ALQ)
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#define OS_REG_WRITE(_ah, _reg, _val) ath_hal_reg_write(_ah, _reg, _val)
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#define OS_REG_READ(_ah, _reg) ath_hal_reg_read(_ah, _reg)
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extern void ath_hal_reg_write(struct ath_hal *ah, u_int reg, u_int32_t val);
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extern u_int32_t ath_hal_reg_read(struct ath_hal *ah, u_int reg);
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#else
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/*
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* The hardware registers are native little-endian byte order.
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* Big-endian hosts are handled by enabling hardware byte-swap
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* of register reads and writes at reset. But the PCI clock
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* domain registers are not byte swapped! Thus, on big-endian
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* platforms we have to explicitly byte-swap those registers.
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* Most of this code is collapsed at compile time because the
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* register values are constants.
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*/
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#define AH_LITTLE_ENDIAN 1234
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#define AH_BIG_ENDIAN 4321
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#if _BYTE_ORDER == _BIG_ENDIAN
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#define OS_REG_WRITE(_ah, _reg, _val) do { \
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if ( (_reg) >= 0x4000 && (_reg) < 0x5000) \
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bus_space_write_4((bus_space_tag_t)(_ah)->ah_st, \
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(bus_space_handle_t)(_ah)->ah_sh, (_reg), (_val)); \
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else \
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bus_space_write_stream_4((bus_space_tag_t)(_ah)->ah_st, \
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(bus_space_handle_t)(_ah)->ah_sh, (_reg), (_val)); \
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} while (0)
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#define OS_REG_READ(_ah, _reg) \
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(((_reg) >= 0x4000 && (_reg) < 0x5000) ? \
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bus_space_read_4((bus_space_tag_t)(_ah)->ah_st, \
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(bus_space_handle_t)(_ah)->ah_sh, (_reg)) : \
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bus_space_read_stream_4((bus_space_tag_t)(_ah)->ah_st, \
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(bus_space_handle_t)(_ah)->ah_sh, (_reg)))
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#else /* _BYTE_ORDER == _LITTLE_ENDIAN */
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#define OS_REG_WRITE(_ah, _reg, _val) \
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bus_space_write_4((bus_space_tag_t)(_ah)->ah_st, \
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(bus_space_handle_t)(_ah)->ah_sh, (_reg), (_val))
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#define OS_REG_READ(_ah, _reg) \
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bus_space_read_4((bus_space_tag_t)(_ah)->ah_st, \
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(bus_space_handle_t)(_ah)->ah_sh, (_reg))
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#endif /* _BYTE_ORDER */
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#endif /* AH_DEBUG || AH_REGFUNC || AH_DEBUG_ALQ */
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#ifdef AH_DEBUG_ALQ
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extern void OS_MARK(struct ath_hal *, u_int id, u_int32_t value);
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#else
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#define OS_MARK(_ah, _id, _v)
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#endif
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#endif /* _ATH_AH_OSDEP_H_ */
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