1993-06-12 14:58:17 +00:00
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/*-
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* Copyright (c) 1990 William Jolitz.
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* Copyright (c) 1991 The Regents of the University of California.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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ALL:
Removed patch kit headers and rcsid strings, add $Id$.
isa.c:
Removed old #ifdef notyet isa_configure code, since it will never be
used, and I have done 90% of what it attempted to.
Add conflict checking code that searchs back through the devtab's looking
for any device that has already been found that may conflict with what
we are about to probe. Checks are mode for I/O address, memory address,
IRQ, and DRQ. This should stop the screwing up of any device that has
alread been found by other device probes.
Print out messages when we are not going to probe a device due to
a conflict so the user knows WHY something was not found. For example:
aha0 not probed due to irq conflict with ahb0 at 11
Now print out a message when a device is not found so the user knows
that it was probed for, but could not be found. For example:
ed1 not found at 0x320
For devices that have I/O address < 0x100 say that they are on the
motherboard, not on isa! The 0x100 magic number is per ISA spec. It
may seem funny that pc0 and sc0 report as being on the motherboard, but
this is due to the fact that the I/O address used is that of the keyboard
controller which IS on the motherboard. We really need to split the
keyboard probe from the display probe. It is completly legal to build
a pc with out one or the other, or even with out both!
npx.c:
Return -1 from the probe routine if we are using the Emulator so
that the i/o addresses are not printed, this is the same trick used
for 486's.
Do not print the ``Errors reported via Exception 16'', and
``Errors reported via IRQ 13'' messages any more, since these just lead
to more user confusion that anything. It still prints the message
``Error reporting broken, using 387 emulator'' so that the person is
aware that there mother board is ill.
1993-10-13 15:59:30 +00:00
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* from: @(#)npx.c 7.2 (Berkeley) 5/12/91
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1993-06-12 14:58:17 +00:00
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*/
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2003-06-02 16:32:55 +00:00
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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2001-07-12 06:32:51 +00:00
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#include "opt_cpu.h"
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2002-01-30 12:41:12 +00:00
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#include "opt_isa.h"
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2001-10-21 05:18:30 +00:00
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#include "opt_npx.h"
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1996-01-04 19:51:50 +00:00
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1994-08-13 03:50:34 +00:00
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#include <sys/param.h>
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#include <sys/systm.h>
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1999-04-16 21:22:55 +00:00
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#include <sys/bus.h>
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1995-10-28 13:07:28 +00:00
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#include <sys/kernel.h>
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2001-05-01 08:13:21 +00:00
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#include <sys/lock.h>
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1998-02-12 21:41:10 +00:00
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#include <sys/malloc.h>
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1999-04-16 21:22:55 +00:00
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#include <sys/module.h>
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2001-01-20 02:30:58 +00:00
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#include <sys/mutex.h>
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2001-05-01 08:13:21 +00:00
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#include <sys/mutex.h>
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#include <sys/proc.h>
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2003-11-03 21:53:38 +00:00
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#include <sys/smp.h>
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2001-05-01 08:13:21 +00:00
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#include <sys/sysctl.h>
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1999-04-16 21:22:55 +00:00
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#include <machine/bus.h>
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#include <sys/rman.h>
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1997-01-29 13:46:28 +00:00
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#ifdef NPX_DEBUG
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1994-11-14 14:59:06 +00:00
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#include <sys/syslog.h>
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1997-01-29 13:46:28 +00:00
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#endif
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1994-11-14 14:59:06 +00:00
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#include <sys/signalvar.h>
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1994-10-23 21:28:03 +00:00
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1997-04-22 06:55:47 +00:00
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#include <machine/asmacros.h>
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1997-10-28 11:43:57 +00:00
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#include <machine/cputypes.h>
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#include <machine/frame.h>
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1996-06-25 20:31:01 +00:00
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#include <machine/md_var.h>
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1997-05-31 09:27:31 +00:00
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#include <machine/pcb.h>
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1997-10-28 11:43:57 +00:00
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#include <machine/psl.h>
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1999-04-16 21:22:55 +00:00
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#include <machine/resource.h>
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1994-08-13 03:50:34 +00:00
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#include <machine/specialreg.h>
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1997-10-28 11:43:57 +00:00
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#include <machine/segments.h>
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2002-09-16 19:25:59 +00:00
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#include <machine/ucontext.h>
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1994-10-23 21:28:03 +00:00
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2003-11-03 21:53:38 +00:00
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#include <machine/intr_machdep.h>
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2002-01-30 12:41:12 +00:00
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#ifdef DEV_ISA
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2000-05-04 23:57:32 +00:00
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#include <isa/isavar.h>
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2002-01-30 12:41:12 +00:00
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#endif
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1993-06-12 14:58:17 +00:00
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2005-07-02 20:06:44 +00:00
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#if !defined(CPU_DISABLE_SSE) && defined(I686_CPU)
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2002-09-07 07:02:12 +00:00
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#define CPU_ENABLE_SSE
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#endif
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1993-06-12 14:58:17 +00:00
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/*
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* 387 and 287 Numeric Coprocessor Extension (NPX) Driver.
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*/
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1996-11-11 20:39:03 +00:00
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/* Configuration flags. */
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#define NPX_DISABLE_I586_OPTIMIZED_BCOPY (1 << 0)
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#define NPX_DISABLE_I586_OPTIMIZED_BZERO (1 << 1)
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#define NPX_DISABLE_I586_OPTIMIZED_COPYIO (1 << 2)
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2005-03-02 21:33:29 +00:00
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#if defined(__GNUCLIKE_ASM) && !defined(lint)
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1993-06-12 14:58:17 +00:00
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1995-01-03 04:00:06 +00:00
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#define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr)))
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1993-06-12 14:58:17 +00:00
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#define fnclex() __asm("fnclex")
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#define fninit() __asm("fninit")
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1998-04-15 18:58:09 +00:00
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#define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr)))
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#define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr)))
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#define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr)))
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1995-01-03 04:00:06 +00:00
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#define fp_divide_by_0() __asm("fldz; fld1; fdiv %st,%st(1); fnop")
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#define frstor(addr) __asm("frstor %0" : : "m" (*(addr)))
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2001-08-23 01:03:56 +00:00
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#ifdef CPU_ENABLE_SSE
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2001-07-12 06:32:51 +00:00
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#define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr)))
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#define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr)))
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2005-03-17 22:21:36 +00:00
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#define ldmxcsr(__csr) __asm __volatile("ldmxcsr %0" : : "m" (__csr))
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2001-08-23 01:03:56 +00:00
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#endif
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1993-06-12 14:58:17 +00:00
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#define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \
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: : "n" (CR0_TS) : "ax")
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#define stop_emulating() __asm("clts")
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2005-03-02 21:33:29 +00:00
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#else /* !(__GNUCLIKE_ASM && !lint) */
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1993-06-12 14:58:17 +00:00
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2002-03-23 16:01:49 +00:00
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void fldcw(caddr_t addr);
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void fnclex(void);
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void fninit(void);
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void fnsave(caddr_t addr);
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void fnstcw(caddr_t addr);
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void fnstsw(caddr_t addr);
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void fp_divide_by_0(void);
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void frstor(caddr_t addr);
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2001-08-23 01:03:56 +00:00
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#ifdef CPU_ENABLE_SSE
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2002-03-23 16:01:49 +00:00
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void fxsave(caddr_t addr);
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void fxrstor(caddr_t addr);
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2001-08-23 01:03:56 +00:00
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#endif
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2002-03-23 16:01:49 +00:00
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void start_emulating(void);
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void stop_emulating(void);
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1993-06-12 14:58:17 +00:00
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2005-03-02 21:33:29 +00:00
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#endif /* __GNUCLIKE_ASM && !lint */
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1993-06-12 14:58:17 +00:00
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2001-07-12 06:32:51 +00:00
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#ifdef CPU_ENABLE_SSE
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2001-09-12 08:38:13 +00:00
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#define GET_FPU_CW(thread) \
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2001-07-12 06:32:51 +00:00
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(cpu_fxsr ? \
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2001-09-12 08:38:13 +00:00
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(thread)->td_pcb->pcb_save.sv_xmm.sv_env.en_cw : \
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(thread)->td_pcb->pcb_save.sv_87.sv_env.en_cw)
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#define GET_FPU_SW(thread) \
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2001-07-12 06:32:51 +00:00
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(cpu_fxsr ? \
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2001-09-12 08:38:13 +00:00
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(thread)->td_pcb->pcb_save.sv_xmm.sv_env.en_sw : \
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(thread)->td_pcb->pcb_save.sv_87.sv_env.en_sw)
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2001-07-12 06:32:51 +00:00
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#else /* CPU_ENABLE_SSE */
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2001-09-12 08:38:13 +00:00
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#define GET_FPU_CW(thread) \
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(thread->td_pcb->pcb_save.sv_87.sv_env.en_cw)
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#define GET_FPU_SW(thread) \
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(thread->td_pcb->pcb_save.sv_87.sv_env.en_sw)
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2001-07-12 06:32:51 +00:00
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#endif /* CPU_ENABLE_SSE */
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1993-06-12 14:58:17 +00:00
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typedef u_char bool_t;
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2006-04-19 07:00:19 +00:00
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#ifdef CPU_ENABLE_SSE
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static void fpu_clean_state(void);
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#endif
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2002-11-16 06:35:53 +00:00
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static void fpusave(union savefpu *);
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static void fpurstor(union savefpu *);
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2002-03-23 16:01:49 +00:00
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static int npx_attach(device_t dev);
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static void npx_identify(driver_t *driver, device_t parent);
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static void npx_intr(void *);
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static int npx_probe(device_t dev);
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2001-06-15 07:53:20 +00:00
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#ifdef I586_CPU_XXX
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2002-03-23 16:01:49 +00:00
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static long timezero(const char *funcname,
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void (*func)(void *buf, size_t len));
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1999-03-28 23:28:18 +00:00
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#endif /* I586_CPU */
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1993-06-12 14:58:17 +00:00
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1995-01-03 04:00:06 +00:00
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int hw_float; /* XXX currently just alias for npx_exists */
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1995-10-28 13:07:28 +00:00
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SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint,
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CTLFLAG_RD, &hw_float, 0,
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"Floatingpoint instructions executed in hardware");
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1998-12-07 21:58:50 +00:00
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static volatile u_int npx_intrs_while_probing;
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static volatile u_int npx_traps_while_probing;
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1997-06-22 16:04:22 +00:00
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2002-09-16 19:25:59 +00:00
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static union savefpu npx_cleanstate;
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static bool_t npx_cleanstate_ready;
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1993-06-12 14:58:17 +00:00
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static bool_t npx_ex16;
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static bool_t npx_exists;
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static bool_t npx_irq13;
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2001-10-16 14:12:35 +00:00
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alias_for_inthand_t probetrap;
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1998-04-19 15:39:26 +00:00
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__asm(" \n\
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.text \n\
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.p2align 2,0x90 \n\
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1999-05-06 09:44:57 +00:00
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.type " __XSTRING(CNAME(probetrap)) ",@function \n\
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1998-04-19 15:39:26 +00:00
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" __XSTRING(CNAME(probetrap)) ": \n\
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ss \n\
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incl " __XSTRING(CNAME(npx_traps_while_probing)) " \n\
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fnclex \n\
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iret \n\
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1993-06-12 14:58:17 +00:00
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");
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1997-07-21 07:57:50 +00:00
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1999-08-22 19:52:51 +00:00
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/*
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* Identify routine. Create a connection point on our parent for probing.
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*/
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static void
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npx_identify(driver, parent)
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driver_t *driver;
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device_t parent;
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{
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device_t child;
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child = BUS_ADD_CHILD(parent, 0, "npx", 0);
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if (child == NULL)
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panic("npx_identify");
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}
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2001-05-22 21:20:49 +00:00
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/*
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* Do minimal handling of npx interrupts to convert them to traps.
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*/
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static void
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npx_intr(dummy)
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void *dummy;
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{
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2001-09-12 08:38:13 +00:00
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struct thread *td;
|
2001-05-22 21:20:49 +00:00
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2001-10-16 14:12:35 +00:00
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npx_intrs_while_probing++;
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2001-05-22 21:20:49 +00:00
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/*
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* The BUSY# latch must be cleared in all cases so that the next
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* unmasked npx exception causes an interrupt.
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*/
|
2005-03-16 20:46:16 +00:00
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outb(IO_NPX, 0);
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2001-05-22 21:20:49 +00:00
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/*
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2001-12-11 23:33:44 +00:00
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* fpcurthread is normally non-null here. In that case, schedule an
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2001-05-22 21:20:49 +00:00
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* AST to finish the exception handling in the correct context
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2001-09-12 08:38:13 +00:00
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* (this interrupt may occur after the thread has entered the
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2001-05-22 21:20:49 +00:00
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* kernel via a syscall or an interrupt). Otherwise, the npx
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2001-09-12 08:38:13 +00:00
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* state of the thread that caused this interrupt must have been
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2001-09-14 04:40:44 +00:00
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* pushed to the thread's pcb, and clearing of the busy latch
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2001-05-22 21:20:49 +00:00
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* above has finished the (essentially null) handling of this
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* interrupt. Control will eventually return to the instruction
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* that caused it and it will repeat. We will eventually (usually
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* soon) win the race to handle the interrupt properly.
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*/
|
2001-12-11 23:33:44 +00:00
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|
td = PCPU_GET(fpcurthread);
|
2001-09-12 08:38:13 +00:00
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|
if (td != NULL) {
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td->td_pcb->pcb_flags |= PCB_NPXTRAP;
|
2001-05-22 21:20:49 +00:00
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|
mtx_lock_spin(&sched_lock);
|
2003-02-17 09:55:10 +00:00
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|
td->td_flags |= TDF_ASTPENDING;
|
2001-05-22 21:20:49 +00:00
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mtx_unlock_spin(&sched_lock);
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|
}
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}
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|
1993-06-12 14:58:17 +00:00
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|
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/*
|
2006-04-06 17:17:45 +00:00
|
|
|
* Probe routine. Set flags to tell npxattach() what to do. Set up an
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* interrupt handler if npx needs to use interrupts.
|
1993-06-12 14:58:17 +00:00
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*/
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static int
|
1999-04-16 21:22:55 +00:00
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|
|
npx_probe(dev)
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|
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device_t dev;
|
1993-06-12 14:58:17 +00:00
|
|
|
{
|
2001-10-16 14:12:35 +00:00
|
|
|
struct gate_descriptor save_idt_npxtrap;
|
|
|
|
struct resource *ioport_res, *irq_res;
|
|
|
|
void *irq_cookie;
|
|
|
|
int ioport_rid, irq_num, irq_rid;
|
1995-01-03 04:00:06 +00:00
|
|
|
u_short control;
|
|
|
|
u_short status;
|
2001-10-16 14:12:35 +00:00
|
|
|
|
2006-04-06 17:17:45 +00:00
|
|
|
device_set_desc(dev, "math processor");
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Modern CPUs all have an FPU that uses the INT16 interface
|
|
|
|
* and provide a simple way to verify that, so handle the
|
|
|
|
* common case right away.
|
|
|
|
*/
|
|
|
|
if (cpu_feature & CPUID_FPU) {
|
|
|
|
hw_float = npx_exists = 1;
|
|
|
|
npx_ex16 = 1;
|
|
|
|
device_quiet(dev);
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
2003-09-10 01:07:04 +00:00
|
|
|
save_idt_npxtrap = idt[IDT_MF];
|
|
|
|
setidt(IDT_MF, probetrap, SDT_SYS386TGT, SEL_KPL,
|
|
|
|
GSEL(GCODE_SEL, SEL_KPL));
|
2001-10-16 14:12:35 +00:00
|
|
|
ioport_rid = 0;
|
|
|
|
ioport_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &ioport_rid,
|
2005-03-16 20:31:46 +00:00
|
|
|
IO_NPX, IO_NPX + IO_NPXSIZE - 1, IO_NPXSIZE, RF_ACTIVE);
|
2001-10-16 14:12:35 +00:00
|
|
|
if (ioport_res == NULL)
|
|
|
|
panic("npx: can't get ports");
|
|
|
|
if (resource_int_value("npx", 0, "irq", &irq_num) != 0)
|
2005-03-16 20:46:16 +00:00
|
|
|
irq_num = IRQ_NPX;
|
2001-10-16 14:12:35 +00:00
|
|
|
irq_rid = 0;
|
2002-11-05 04:03:42 +00:00
|
|
|
irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, &irq_rid, irq_num,
|
2001-10-16 14:12:35 +00:00
|
|
|
irq_num, 1, RF_ACTIVE);
|
2005-12-05 22:11:44 +00:00
|
|
|
if (irq_res != NULL) {
|
|
|
|
if (bus_setup_intr(dev, irq_res, INTR_TYPE_MISC | INTR_FAST,
|
|
|
|
npx_intr, NULL, &irq_cookie) != 0)
|
|
|
|
panic("npx: can't create intr");
|
|
|
|
}
|
1995-01-03 04:00:06 +00:00
|
|
|
|
1993-06-12 14:58:17 +00:00
|
|
|
/*
|
|
|
|
* Partially reset the coprocessor, if any. Some BIOS's don't reset
|
|
|
|
* it after a warm boot.
|
|
|
|
*/
|
2005-03-16 20:46:16 +00:00
|
|
|
npx_full_reset();
|
|
|
|
outb(IO_NPX, 0);
|
|
|
|
|
1993-06-12 14:58:17 +00:00
|
|
|
/*
|
2006-04-06 17:17:45 +00:00
|
|
|
* Don't trap while we're probing.
|
1993-06-12 14:58:17 +00:00
|
|
|
*/
|
|
|
|
stop_emulating();
|
2006-04-06 17:17:45 +00:00
|
|
|
|
1993-06-12 14:58:17 +00:00
|
|
|
/*
|
|
|
|
* Finish resetting the coprocessor, if any. If there is an error
|
2001-10-16 14:12:35 +00:00
|
|
|
* pending, then we may get a bogus IRQ13, but npx_intr() will handle
|
1993-06-12 14:58:17 +00:00
|
|
|
* it OK. Bogus halts have never been observed, but we enabled
|
|
|
|
* IRQ13 and cleared the BUSY# latch early to handle them anyway.
|
|
|
|
*/
|
|
|
|
fninit();
|
1997-07-21 07:57:50 +00:00
|
|
|
|
1995-02-23 17:32:38 +00:00
|
|
|
/*
|
|
|
|
* Don't use fwait here because it might hang.
|
|
|
|
* Don't use fnop here because it usually hangs if there is no FPU.
|
|
|
|
*/
|
1995-01-03 04:00:06 +00:00
|
|
|
DELAY(1000); /* wait for any IRQ13 */
|
1993-06-12 14:58:17 +00:00
|
|
|
#ifdef DIAGNOSTIC
|
|
|
|
if (npx_intrs_while_probing != 0)
|
|
|
|
printf("fninit caused %u bogus npx interrupt(s)\n",
|
|
|
|
npx_intrs_while_probing);
|
|
|
|
if (npx_traps_while_probing != 0)
|
|
|
|
printf("fninit caused %u bogus npx trap(s)\n",
|
|
|
|
npx_traps_while_probing);
|
|
|
|
#endif
|
|
|
|
/*
|
|
|
|
* Check for a status of mostly zero.
|
|
|
|
*/
|
|
|
|
status = 0x5a5a;
|
|
|
|
fnstsw(&status);
|
|
|
|
if ((status & 0xb8ff) == 0) {
|
|
|
|
/*
|
|
|
|
* Good, now check for a proper control word.
|
|
|
|
*/
|
1995-05-30 08:16:23 +00:00
|
|
|
control = 0x5a5a;
|
1993-06-12 14:58:17 +00:00
|
|
|
fnstcw(&control);
|
|
|
|
if ((control & 0x1f3f) == 0x033f) {
|
1994-09-09 23:13:03 +00:00
|
|
|
hw_float = npx_exists = 1;
|
1993-06-12 14:58:17 +00:00
|
|
|
/*
|
|
|
|
* We have an npx, now divide by 0 to see if exception
|
|
|
|
* 16 works.
|
|
|
|
*/
|
|
|
|
control &= ~(1 << 2); /* enable divide by 0 trap */
|
|
|
|
fldcw(&control);
|
2001-10-21 05:18:30 +00:00
|
|
|
#ifdef FPU_ERROR_BROKEN
|
|
|
|
/*
|
|
|
|
* FPU error signal doesn't work on some CPU
|
|
|
|
* accelerator board.
|
|
|
|
*/
|
|
|
|
npx_ex16 = 1;
|
|
|
|
return (0);
|
|
|
|
#endif
|
1993-06-12 14:58:17 +00:00
|
|
|
npx_traps_while_probing = npx_intrs_while_probing = 0;
|
|
|
|
fp_divide_by_0();
|
2004-06-06 15:17:44 +00:00
|
|
|
DELAY(1000); /* wait for any IRQ13 */
|
1993-06-12 14:58:17 +00:00
|
|
|
if (npx_traps_while_probing != 0) {
|
|
|
|
/*
|
|
|
|
* Good, exception 16 works.
|
|
|
|
*/
|
|
|
|
npx_ex16 = 1;
|
2001-10-16 14:12:35 +00:00
|
|
|
goto no_irq13;
|
1993-06-12 14:58:17 +00:00
|
|
|
}
|
|
|
|
if (npx_intrs_while_probing != 0) {
|
|
|
|
/*
|
|
|
|
* Bad, we are stuck with IRQ13.
|
|
|
|
*/
|
|
|
|
npx_irq13 = 1;
|
2003-09-10 01:07:04 +00:00
|
|
|
idt[IDT_MF] = save_idt_npxtrap;
|
2003-11-03 21:53:38 +00:00
|
|
|
#ifdef SMP
|
|
|
|
if (mp_ncpus > 1)
|
|
|
|
panic("npx0 cannot use IRQ 13 on an SMP system");
|
|
|
|
#endif
|
1999-04-16 21:22:55 +00:00
|
|
|
return (0);
|
1993-06-12 14:58:17 +00:00
|
|
|
}
|
|
|
|
/*
|
|
|
|
* Worse, even IRQ13 is broken. Use emulator.
|
|
|
|
*/
|
|
|
|
}
|
|
|
|
}
|
|
|
|
/*
|
|
|
|
* Probe failed, but we want to get to npxattach to initialize the
|
|
|
|
* emulator and say that it has been installed. XXX handle devices
|
|
|
|
* that aren't really devices better.
|
|
|
|
*/
|
2003-11-03 21:53:38 +00:00
|
|
|
#ifdef SMP
|
|
|
|
if (mp_ncpus > 1)
|
|
|
|
panic("npx0 cannot be emulated on an SMP system");
|
|
|
|
#endif
|
2001-10-16 14:12:35 +00:00
|
|
|
/* FALLTHROUGH */
|
|
|
|
no_irq13:
|
2003-09-10 01:07:04 +00:00
|
|
|
idt[IDT_MF] = save_idt_npxtrap;
|
2005-12-05 22:11:44 +00:00
|
|
|
if (irq_res != NULL) {
|
|
|
|
bus_teardown_intr(dev, irq_res, irq_cookie);
|
|
|
|
bus_release_resource(dev, SYS_RES_IRQ, irq_rid, irq_res);
|
|
|
|
}
|
2001-10-16 14:12:35 +00:00
|
|
|
bus_release_resource(dev, SYS_RES_IOPORT, ioport_rid, ioport_res);
|
1999-04-16 21:22:55 +00:00
|
|
|
return (0);
|
1993-06-12 14:58:17 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Attach routine - announce which it is, and wire into system
|
|
|
|
*/
|
2002-09-28 17:15:38 +00:00
|
|
|
static int
|
1999-04-16 21:22:55 +00:00
|
|
|
npx_attach(dev)
|
|
|
|
device_t dev;
|
1993-06-12 14:58:17 +00:00
|
|
|
{
|
1999-04-16 21:22:55 +00:00
|
|
|
int flags;
|
2002-09-16 19:25:59 +00:00
|
|
|
register_t s;
|
1999-07-25 13:16:09 +00:00
|
|
|
|
2004-10-14 22:21:59 +00:00
|
|
|
flags = device_get_flags(dev);
|
1998-10-22 05:58:45 +00:00
|
|
|
|
2004-10-14 22:37:51 +00:00
|
|
|
if (npx_irq13)
|
|
|
|
device_printf(dev, "IRQ 13 interface\n");
|
2006-04-06 17:17:45 +00:00
|
|
|
else if (!npx_ex16)
|
2004-10-14 22:37:51 +00:00
|
|
|
device_printf(dev, "WARNING: no FPU!\n");
|
2006-04-06 17:17:45 +00:00
|
|
|
else if (!device_is_quiet(dev) || bootverbose)
|
|
|
|
device_printf(dev, "INT 16 interface\n");
|
2004-10-14 22:37:51 +00:00
|
|
|
|
1993-06-12 14:58:17 +00:00
|
|
|
npxinit(__INITIAL_NPXCW__);
|
1996-11-11 20:39:03 +00:00
|
|
|
|
2002-09-16 19:25:59 +00:00
|
|
|
if (npx_cleanstate_ready == 0) {
|
|
|
|
s = intr_disable();
|
|
|
|
stop_emulating();
|
|
|
|
fpusave(&npx_cleanstate);
|
|
|
|
start_emulating();
|
2006-05-30 23:44:21 +00:00
|
|
|
#ifdef CPU_ENABLE_SSE
|
|
|
|
if (cpu_fxsr) {
|
|
|
|
if (npx_cleanstate.sv_xmm.sv_env.en_mxcsr_mask)
|
|
|
|
cpu_mxcsr_mask =
|
|
|
|
npx_cleanstate.sv_xmm.sv_env.en_mxcsr_mask;
|
|
|
|
else
|
|
|
|
cpu_mxcsr_mask = 0xFFBF;
|
|
|
|
}
|
|
|
|
#endif
|
2002-09-16 19:25:59 +00:00
|
|
|
npx_cleanstate_ready = 1;
|
|
|
|
intr_restore(s);
|
|
|
|
}
|
2001-04-13 17:14:53 +00:00
|
|
|
#ifdef I586_CPU_XXX
|
1999-07-25 13:16:09 +00:00
|
|
|
if (cpu_class == CPUCLASS_586 && npx_ex16 && npx_exists &&
|
1998-02-12 21:41:10 +00:00
|
|
|
timezero("i586_bzero()", i586_bzero) <
|
|
|
|
timezero("bzero()", bzero) * 4 / 5) {
|
2003-04-04 17:29:55 +00:00
|
|
|
if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY))
|
1996-11-11 20:39:03 +00:00
|
|
|
bcopy_vector = i586_bcopy;
|
1999-04-16 21:22:55 +00:00
|
|
|
if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BZERO))
|
2003-04-04 17:29:55 +00:00
|
|
|
bzero_vector = i586_bzero;
|
1999-04-16 21:22:55 +00:00
|
|
|
if (!(flags & NPX_DISABLE_I586_OPTIMIZED_COPYIO)) {
|
1996-11-11 20:39:03 +00:00
|
|
|
copyin_vector = i586_copyin;
|
|
|
|
copyout_vector = i586_copyout;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
1999-04-16 21:22:55 +00:00
|
|
|
return (0); /* XXX unused */
|
1993-06-12 14:58:17 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Initialize floating point unit.
|
|
|
|
*/
|
|
|
|
void
|
|
|
|
npxinit(control)
|
1995-01-03 04:00:06 +00:00
|
|
|
u_short control;
|
1993-06-12 14:58:17 +00:00
|
|
|
{
|
2001-07-17 13:06:47 +00:00
|
|
|
static union savefpu dummy;
|
2002-03-21 06:19:08 +00:00
|
|
|
register_t savecrit;
|
1993-06-12 14:58:17 +00:00
|
|
|
|
|
|
|
if (!npx_exists)
|
|
|
|
return;
|
|
|
|
/*
|
|
|
|
* fninit has the same h/w bugs as fnsave. Use the detoxified
|
1995-01-03 04:00:06 +00:00
|
|
|
* fnsave to throw away any junk in the fpu. npxsave() initializes
|
2001-12-11 23:33:44 +00:00
|
|
|
* the fpu and sets fpcurthread = NULL as important side effects.
|
1993-06-12 14:58:17 +00:00
|
|
|
*/
|
2002-03-21 06:19:08 +00:00
|
|
|
savecrit = intr_disable();
|
1993-06-12 14:58:17 +00:00
|
|
|
npxsave(&dummy);
|
|
|
|
stop_emulating();
|
2001-10-15 20:18:06 +00:00
|
|
|
#ifdef CPU_ENABLE_SSE
|
|
|
|
/* XXX npxsave() doesn't actually initialize the fpu in the SSE case. */
|
|
|
|
if (cpu_fxsr)
|
|
|
|
fninit();
|
|
|
|
#endif
|
1993-06-12 14:58:17 +00:00
|
|
|
fldcw(&control);
|
|
|
|
start_emulating();
|
2002-03-21 06:19:08 +00:00
|
|
|
intr_restore(savecrit);
|
1993-06-12 14:58:17 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Free coprocessor (if we have it).
|
|
|
|
*/
|
|
|
|
void
|
2001-09-12 08:38:13 +00:00
|
|
|
npxexit(td)
|
|
|
|
struct thread *td;
|
1993-06-12 14:58:17 +00:00
|
|
|
{
|
2002-03-21 06:19:08 +00:00
|
|
|
register_t savecrit;
|
1993-06-12 14:58:17 +00:00
|
|
|
|
2002-03-21 06:19:08 +00:00
|
|
|
savecrit = intr_disable();
|
2002-09-16 19:25:59 +00:00
|
|
|
if (curthread == PCPU_GET(fpcurthread))
|
2001-07-12 06:32:51 +00:00
|
|
|
npxsave(&PCPU_GET(curpcb)->pcb_save);
|
2002-03-21 06:19:08 +00:00
|
|
|
intr_restore(savecrit);
|
1997-01-29 13:46:28 +00:00
|
|
|
#ifdef NPX_DEBUG
|
1994-11-14 14:59:06 +00:00
|
|
|
if (npx_exists) {
|
|
|
|
u_int masked_exceptions;
|
|
|
|
|
2002-09-16 19:25:59 +00:00
|
|
|
masked_exceptions = GET_FPU_CW(td) & GET_FPU_SW(td) & 0x7f;
|
1994-11-14 14:59:06 +00:00
|
|
|
/*
|
1997-01-29 13:46:28 +00:00
|
|
|
* Log exceptions that would have trapped with the old
|
|
|
|
* control word (overflow, divide by 0, and invalid operand).
|
1994-11-14 14:59:06 +00:00
|
|
|
*/
|
|
|
|
if (masked_exceptions & 0x0d)
|
|
|
|
log(LOG_ERR,
|
2001-09-18 21:05:04 +00:00
|
|
|
"pid %d (%s) exited with masked floating point exceptions 0x%02x\n",
|
|
|
|
td->td_proc->p_pid, td->td_proc->p_comm,
|
|
|
|
masked_exceptions);
|
1993-06-12 14:58:17 +00:00
|
|
|
}
|
1997-01-29 13:46:28 +00:00
|
|
|
#endif
|
1993-06-12 14:58:17 +00:00
|
|
|
}
|
|
|
|
|
2002-09-16 19:25:59 +00:00
|
|
|
int
|
|
|
|
npxformat()
|
|
|
|
{
|
|
|
|
|
|
|
|
if (!npx_exists)
|
|
|
|
return (_MC_FPFMT_NODEV);
|
|
|
|
#ifdef CPU_ENABLE_SSE
|
|
|
|
if (cpu_fxsr)
|
|
|
|
return (_MC_FPFMT_XMM);
|
|
|
|
#endif
|
|
|
|
return (_MC_FPFMT_387);
|
|
|
|
}
|
|
|
|
|
1999-07-25 13:16:09 +00:00
|
|
|
/*
|
|
|
|
* The following mechanism is used to ensure that the FPE_... value
|
|
|
|
* that is passed as a trapcode to the signal handler of the user
|
|
|
|
* process does not have more than one bit set.
|
|
|
|
*
|
|
|
|
* Multiple bits may be set if the user process modifies the control
|
1999-07-26 05:47:31 +00:00
|
|
|
* word while a status word bit is already set. While this is a sign
|
1999-07-25 13:16:09 +00:00
|
|
|
* of bad coding, we have no choise than to narrow them down to one
|
|
|
|
* bit, since we must not send a trapcode that is not exactly one of
|
|
|
|
* the FPE_ macros.
|
|
|
|
*
|
1999-07-26 05:47:31 +00:00
|
|
|
* The mechanism has a static table with 127 entries. Each combination
|
1999-07-25 13:16:09 +00:00
|
|
|
* of the 7 FPU status word exception bits directly translates to a
|
|
|
|
* position in this table, where a single FPE_... value is stored.
|
|
|
|
* This FPE_... value stored there is considered the "most important"
|
1999-07-26 05:47:31 +00:00
|
|
|
* of the exception bits and will be sent as the signal code. The
|
1999-07-25 13:16:09 +00:00
|
|
|
* precedence of the bits is based upon Intel Document "Numerical
|
|
|
|
* Applications", Chapter "Special Computational Situations".
|
|
|
|
*
|
|
|
|
* The macro to choose one of these values does these steps: 1) Throw
|
1999-07-26 05:47:31 +00:00
|
|
|
* away status word bits that cannot be masked. 2) Throw away the bits
|
1999-07-25 13:16:09 +00:00
|
|
|
* currently masked in the control word, assuming the user isn't
|
1999-07-26 05:47:31 +00:00
|
|
|
* interested in them anymore. 3) Reinsert status word bit 7 (stack
|
1999-07-25 13:16:09 +00:00
|
|
|
* fault) if it is set, which cannot be masked but must be presered.
|
|
|
|
* 4) Use the remaining bits to point into the trapcode table.
|
|
|
|
*
|
|
|
|
* The 6 maskable bits in order of their preference, as stated in the
|
|
|
|
* above referenced Intel manual:
|
|
|
|
* 1 Invalid operation (FP_X_INV)
|
|
|
|
* 1a Stack underflow
|
|
|
|
* 1b Stack overflow
|
|
|
|
* 1c Operand of unsupported format
|
|
|
|
* 1d SNaN operand.
|
|
|
|
* 2 QNaN operand (not an exception, irrelavant here)
|
|
|
|
* 3 Any other invalid-operation not mentioned above or zero divide
|
|
|
|
* (FP_X_INV, FP_X_DZ)
|
|
|
|
* 4 Denormal operand (FP_X_DNML)
|
|
|
|
* 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL)
|
1999-07-26 05:47:31 +00:00
|
|
|
* 6 Inexact result (FP_X_IMP)
|
|
|
|
*/
|
1999-07-25 13:16:09 +00:00
|
|
|
static char fpetable[128] = {
|
|
|
|
0,
|
1999-07-26 05:47:31 +00:00
|
|
|
FPE_FLTINV, /* 1 - INV */
|
|
|
|
FPE_FLTUND, /* 2 - DNML */
|
|
|
|
FPE_FLTINV, /* 3 - INV | DNML */
|
|
|
|
FPE_FLTDIV, /* 4 - DZ */
|
|
|
|
FPE_FLTINV, /* 5 - INV | DZ */
|
|
|
|
FPE_FLTDIV, /* 6 - DNML | DZ */
|
|
|
|
FPE_FLTINV, /* 7 - INV | DNML | DZ */
|
|
|
|
FPE_FLTOVF, /* 8 - OFL */
|
|
|
|
FPE_FLTINV, /* 9 - INV | OFL */
|
|
|
|
FPE_FLTUND, /* A - DNML | OFL */
|
|
|
|
FPE_FLTINV, /* B - INV | DNML | OFL */
|
|
|
|
FPE_FLTDIV, /* C - DZ | OFL */
|
|
|
|
FPE_FLTINV, /* D - INV | DZ | OFL */
|
|
|
|
FPE_FLTDIV, /* E - DNML | DZ | OFL */
|
|
|
|
FPE_FLTINV, /* F - INV | DNML | DZ | OFL */
|
|
|
|
FPE_FLTUND, /* 10 - UFL */
|
|
|
|
FPE_FLTINV, /* 11 - INV | UFL */
|
|
|
|
FPE_FLTUND, /* 12 - DNML | UFL */
|
|
|
|
FPE_FLTINV, /* 13 - INV | DNML | UFL */
|
|
|
|
FPE_FLTDIV, /* 14 - DZ | UFL */
|
|
|
|
FPE_FLTINV, /* 15 - INV | DZ | UFL */
|
|
|
|
FPE_FLTDIV, /* 16 - DNML | DZ | UFL */
|
|
|
|
FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */
|
|
|
|
FPE_FLTOVF, /* 18 - OFL | UFL */
|
|
|
|
FPE_FLTINV, /* 19 - INV | OFL | UFL */
|
|
|
|
FPE_FLTUND, /* 1A - DNML | OFL | UFL */
|
|
|
|
FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */
|
|
|
|
FPE_FLTDIV, /* 1C - DZ | OFL | UFL */
|
|
|
|
FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */
|
|
|
|
FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */
|
|
|
|
FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */
|
|
|
|
FPE_FLTRES, /* 20 - IMP */
|
|
|
|
FPE_FLTINV, /* 21 - INV | IMP */
|
|
|
|
FPE_FLTUND, /* 22 - DNML | IMP */
|
|
|
|
FPE_FLTINV, /* 23 - INV | DNML | IMP */
|
|
|
|
FPE_FLTDIV, /* 24 - DZ | IMP */
|
|
|
|
FPE_FLTINV, /* 25 - INV | DZ | IMP */
|
|
|
|
FPE_FLTDIV, /* 26 - DNML | DZ | IMP */
|
|
|
|
FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */
|
|
|
|
FPE_FLTOVF, /* 28 - OFL | IMP */
|
|
|
|
FPE_FLTINV, /* 29 - INV | OFL | IMP */
|
|
|
|
FPE_FLTUND, /* 2A - DNML | OFL | IMP */
|
|
|
|
FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */
|
|
|
|
FPE_FLTDIV, /* 2C - DZ | OFL | IMP */
|
|
|
|
FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */
|
|
|
|
FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */
|
|
|
|
FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */
|
|
|
|
FPE_FLTUND, /* 30 - UFL | IMP */
|
|
|
|
FPE_FLTINV, /* 31 - INV | UFL | IMP */
|
|
|
|
FPE_FLTUND, /* 32 - DNML | UFL | IMP */
|
|
|
|
FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */
|
|
|
|
FPE_FLTDIV, /* 34 - DZ | UFL | IMP */
|
|
|
|
FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */
|
|
|
|
FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */
|
|
|
|
FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */
|
|
|
|
FPE_FLTOVF, /* 38 - OFL | UFL | IMP */
|
|
|
|
FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */
|
|
|
|
FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */
|
|
|
|
FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */
|
|
|
|
FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */
|
|
|
|
FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */
|
|
|
|
FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */
|
|
|
|
FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */
|
|
|
|
FPE_FLTSUB, /* 40 - STK */
|
|
|
|
FPE_FLTSUB, /* 41 - INV | STK */
|
|
|
|
FPE_FLTUND, /* 42 - DNML | STK */
|
|
|
|
FPE_FLTSUB, /* 43 - INV | DNML | STK */
|
|
|
|
FPE_FLTDIV, /* 44 - DZ | STK */
|
|
|
|
FPE_FLTSUB, /* 45 - INV | DZ | STK */
|
|
|
|
FPE_FLTDIV, /* 46 - DNML | DZ | STK */
|
|
|
|
FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */
|
|
|
|
FPE_FLTOVF, /* 48 - OFL | STK */
|
|
|
|
FPE_FLTSUB, /* 49 - INV | OFL | STK */
|
|
|
|
FPE_FLTUND, /* 4A - DNML | OFL | STK */
|
|
|
|
FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */
|
|
|
|
FPE_FLTDIV, /* 4C - DZ | OFL | STK */
|
|
|
|
FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */
|
|
|
|
FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */
|
|
|
|
FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */
|
|
|
|
FPE_FLTUND, /* 50 - UFL | STK */
|
|
|
|
FPE_FLTSUB, /* 51 - INV | UFL | STK */
|
|
|
|
FPE_FLTUND, /* 52 - DNML | UFL | STK */
|
|
|
|
FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */
|
|
|
|
FPE_FLTDIV, /* 54 - DZ | UFL | STK */
|
|
|
|
FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */
|
|
|
|
FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */
|
|
|
|
FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */
|
|
|
|
FPE_FLTOVF, /* 58 - OFL | UFL | STK */
|
|
|
|
FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */
|
|
|
|
FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */
|
|
|
|
FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */
|
|
|
|
FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */
|
|
|
|
FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */
|
|
|
|
FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */
|
|
|
|
FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */
|
|
|
|
FPE_FLTRES, /* 60 - IMP | STK */
|
|
|
|
FPE_FLTSUB, /* 61 - INV | IMP | STK */
|
|
|
|
FPE_FLTUND, /* 62 - DNML | IMP | STK */
|
|
|
|
FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */
|
|
|
|
FPE_FLTDIV, /* 64 - DZ | IMP | STK */
|
|
|
|
FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */
|
|
|
|
FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */
|
|
|
|
FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */
|
|
|
|
FPE_FLTOVF, /* 68 - OFL | IMP | STK */
|
|
|
|
FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */
|
|
|
|
FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */
|
|
|
|
FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */
|
|
|
|
FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */
|
|
|
|
FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */
|
|
|
|
FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */
|
|
|
|
FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */
|
|
|
|
FPE_FLTUND, /* 70 - UFL | IMP | STK */
|
|
|
|
FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */
|
|
|
|
FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */
|
|
|
|
FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */
|
|
|
|
FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */
|
|
|
|
FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */
|
|
|
|
FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */
|
|
|
|
FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */
|
|
|
|
FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */
|
|
|
|
FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */
|
|
|
|
FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */
|
|
|
|
FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */
|
|
|
|
FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */
|
|
|
|
FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */
|
|
|
|
FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */
|
|
|
|
FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */
|
1999-07-25 13:16:09 +00:00
|
|
|
};
|
|
|
|
|
1993-06-12 14:58:17 +00:00
|
|
|
/*
|
1995-01-03 04:00:06 +00:00
|
|
|
* Preserve the FP status word, clear FP exceptions, then generate a SIGFPE.
|
|
|
|
*
|
|
|
|
* Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now
|
|
|
|
* depend on longjmp() restoring a usable state. Restoring the state
|
|
|
|
* or examining it might fail if we didn't clear exceptions.
|
|
|
|
*
|
1999-07-25 13:16:09 +00:00
|
|
|
* The error code chosen will be one of the FPE_... macros. It will be
|
|
|
|
* sent as the second argument to old BSD-style signal handlers and as
|
|
|
|
* "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers.
|
1995-01-03 04:00:06 +00:00
|
|
|
*
|
|
|
|
* XXX the FP state is not preserved across signal handlers. So signal
|
|
|
|
* handlers cannot afford to do FP unless they preserve the state or
|
|
|
|
* longjmp() out. Both preserving the state and longjmp()ing may be
|
|
|
|
* destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable
|
|
|
|
* solution for signals other than SIGFPE.
|
1993-06-12 14:58:17 +00:00
|
|
|
*/
|
2001-05-22 21:20:49 +00:00
|
|
|
int
|
|
|
|
npxtrap()
|
1993-06-12 14:58:17 +00:00
|
|
|
{
|
2002-03-21 06:19:08 +00:00
|
|
|
register_t savecrit;
|
2001-05-22 21:20:49 +00:00
|
|
|
u_short control, status;
|
1993-06-12 14:58:17 +00:00
|
|
|
|
Fixed panics in npx exception handling. When using IRQ13 exception
handling, SMPng always switches the npx context away from curproc
before calling the handler, so the handler always paniced. When using
exception 16 exception handling, SMPng sometimes switches the npx
context away from curproc before calling the handler, so the handler
sometimes paniced. Also, we didn't lock the context while using it,
so we sometimes didn't detect the switch and then paniced in a less
controlled way.
Just lock the context while using it, and return without doing anything
except clearing the busy latch if the context is not for curproc. This
fixes the exception 16 case and makes the IRQ13 case harmless. In both
cases, the instruction that caused the exception is restarted and the
exception repeats. In the exception 16 case, we soon get an exception
that can be handled without doing anything special. In the IRQ13 case,
we get an easy to kill hung process.
2001-05-02 13:06:58 +00:00
|
|
|
if (!npx_exists) {
|
2001-12-11 23:33:44 +00:00
|
|
|
printf("npxtrap: fpcurthread = %p, curthread = %p, npx_exists = %d\n",
|
|
|
|
PCPU_GET(fpcurthread), curthread, npx_exists);
|
2001-05-22 21:20:49 +00:00
|
|
|
panic("npxtrap from nowhere");
|
1993-06-12 14:58:17 +00:00
|
|
|
}
|
2002-03-21 06:19:08 +00:00
|
|
|
savecrit = intr_disable();
|
1993-06-12 14:58:17 +00:00
|
|
|
|
|
|
|
/*
|
2001-05-22 21:20:49 +00:00
|
|
|
* Interrupt handling (for another interrupt) may have pushed the
|
|
|
|
* state to memory. Fetch the relevant parts of the state from
|
|
|
|
* wherever they are.
|
1993-06-12 14:58:17 +00:00
|
|
|
*/
|
2001-12-11 23:33:44 +00:00
|
|
|
if (PCPU_GET(fpcurthread) != curthread) {
|
2001-09-12 08:38:13 +00:00
|
|
|
control = GET_FPU_CW(curthread);
|
|
|
|
status = GET_FPU_SW(curthread);
|
1993-06-12 14:58:17 +00:00
|
|
|
} else {
|
2001-05-22 21:20:49 +00:00
|
|
|
fnstcw(&control);
|
|
|
|
fnstsw(&status);
|
1993-06-12 14:58:17 +00:00
|
|
|
}
|
2001-05-22 21:20:49 +00:00
|
|
|
|
2002-09-16 19:25:59 +00:00
|
|
|
if (PCPU_GET(fpcurthread) == curthread)
|
2001-05-22 21:20:49 +00:00
|
|
|
fnclex();
|
2002-03-21 06:19:08 +00:00
|
|
|
intr_restore(savecrit);
|
2001-05-22 21:20:49 +00:00
|
|
|
return (fpetable[status & ((~control & 0x3f) | 0x40)]);
|
1993-06-12 14:58:17 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Implement device not available (DNA) exception
|
|
|
|
*
|
2001-12-11 23:33:44 +00:00
|
|
|
* It would be better to switch FP context here (if curthread != fpcurthread)
|
1995-01-03 04:00:06 +00:00
|
|
|
* and not necessarily for every context switch, but it is too hard to
|
|
|
|
* access foreign pcb's.
|
1993-06-12 14:58:17 +00:00
|
|
|
*/
|
2002-09-16 19:25:59 +00:00
|
|
|
|
|
|
|
static int err_count = 0;
|
|
|
|
|
1993-06-12 14:58:17 +00:00
|
|
|
int
|
|
|
|
npxdna()
|
|
|
|
{
|
2002-09-16 19:25:59 +00:00
|
|
|
struct pcb *pcb;
|
2002-03-21 06:19:08 +00:00
|
|
|
register_t s;
|
2005-03-17 22:21:36 +00:00
|
|
|
#ifdef CPU_ENABLE_SSE
|
|
|
|
int mxcsr;
|
|
|
|
#endif
|
2002-09-16 19:25:59 +00:00
|
|
|
u_short control;
|
2001-02-01 03:34:20 +00:00
|
|
|
|
1993-06-12 14:58:17 +00:00
|
|
|
if (!npx_exists)
|
|
|
|
return (0);
|
2002-09-16 19:25:59 +00:00
|
|
|
if (PCPU_GET(fpcurthread) == curthread) {
|
|
|
|
printf("npxdna: fpcurthread == curthread %d times\n",
|
|
|
|
++err_count);
|
|
|
|
stop_emulating();
|
|
|
|
return (1);
|
|
|
|
}
|
2001-12-11 23:33:44 +00:00
|
|
|
if (PCPU_GET(fpcurthread) != NULL) {
|
2002-09-16 19:25:59 +00:00
|
|
|
printf("npxdna: fpcurthread = %p (%d), curthread = %p (%d)\n",
|
|
|
|
PCPU_GET(fpcurthread),
|
|
|
|
PCPU_GET(fpcurthread)->td_proc->p_pid,
|
|
|
|
curthread, curthread->td_proc->p_pid);
|
1993-06-12 14:58:17 +00:00
|
|
|
panic("npxdna");
|
|
|
|
}
|
2002-03-21 06:19:08 +00:00
|
|
|
s = intr_disable();
|
1993-06-12 14:58:17 +00:00
|
|
|
stop_emulating();
|
|
|
|
/*
|
|
|
|
* Record new context early in case frstor causes an IRQ13.
|
|
|
|
*/
|
2001-12-11 23:33:44 +00:00
|
|
|
PCPU_SET(fpcurthread, curthread);
|
2002-09-16 19:25:59 +00:00
|
|
|
pcb = PCPU_GET(curpcb);
|
2001-07-12 06:32:51 +00:00
|
|
|
|
2002-09-16 19:25:59 +00:00
|
|
|
if ((pcb->pcb_flags & PCB_NPXINITDONE) == 0) {
|
|
|
|
/*
|
|
|
|
* This is the first time this thread has used the FPU or
|
|
|
|
* the PCB doesn't contain a clean FPU state. Explicitly
|
|
|
|
* initialize the FPU and load the default control word.
|
|
|
|
*/
|
|
|
|
fninit();
|
|
|
|
control = __INITIAL_NPXCW__;
|
|
|
|
fldcw(&control);
|
2005-03-17 22:21:36 +00:00
|
|
|
#ifdef CPU_ENABLE_SSE
|
|
|
|
if (cpu_fxsr) {
|
|
|
|
mxcsr = __INITIAL_MXCSR__;
|
|
|
|
ldmxcsr(mxcsr);
|
|
|
|
}
|
|
|
|
#endif
|
2002-09-16 19:25:59 +00:00
|
|
|
pcb->pcb_flags |= PCB_NPXINITDONE;
|
|
|
|
} else {
|
|
|
|
/*
|
|
|
|
* The following frstor may cause an IRQ13 when the state
|
|
|
|
* being restored has a pending error. The error will
|
|
|
|
* appear to have been triggered by the current (npx) user
|
|
|
|
* instruction even when that instruction is a no-wait
|
|
|
|
* instruction that should not trigger an error (e.g.,
|
|
|
|
* fnclex). On at least one 486 system all of the no-wait
|
|
|
|
* instructions are broken the same as frstor, so our
|
|
|
|
* treatment does not amplify the breakage. On at least
|
|
|
|
* one 386/Cyrix 387 system, fnclex works correctly while
|
|
|
|
* frstor and fnsave are broken, so our treatment breaks
|
|
|
|
* fnclex if it is the first FPU instruction after a context
|
|
|
|
* switch.
|
|
|
|
*/
|
|
|
|
fpurstor(&pcb->pcb_save);
|
|
|
|
}
|
2002-03-21 06:19:08 +00:00
|
|
|
intr_restore(s);
|
1993-06-12 14:58:17 +00:00
|
|
|
|
|
|
|
return (1);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
2001-05-20 20:04:40 +00:00
|
|
|
* Wrapper for fnsave instruction, partly to handle hardware bugs. When npx
|
|
|
|
* exceptions are reported via IRQ13, spurious IRQ13's may be triggered by
|
|
|
|
* no-wait npx instructions. See the Intel application note AP-578 for
|
|
|
|
* details. This doesn't cause any additional complications here. IRQ13's
|
|
|
|
* are inherently asynchronous unless the CPU is frozen to deliver them --
|
|
|
|
* one that started in userland may be delivered many instructions later,
|
|
|
|
* after the process has entered the kernel. It may even be delivered after
|
|
|
|
* the fnsave here completes. A spurious IRQ13 for the fnsave is handled in
|
|
|
|
* the same way as a very-late-arriving non-spurious IRQ13 from user mode:
|
2001-12-11 23:33:44 +00:00
|
|
|
* it is normally ignored at first because we set fpcurthread to NULL; it is
|
2001-05-20 20:04:40 +00:00
|
|
|
* normally retriggered in npxdna() after return to user mode.
|
|
|
|
*
|
|
|
|
* npxsave() must be called with interrupts disabled, so that it clears
|
2001-12-11 23:33:44 +00:00
|
|
|
* fpcurthread atomically with saving the state. We require callers to do the
|
2001-05-20 20:04:40 +00:00
|
|
|
* disabling, since most callers need to disable interrupts anyway to call
|
2001-12-11 23:33:44 +00:00
|
|
|
* npxsave() atomically with checking fpcurthread.
|
2001-05-20 20:04:40 +00:00
|
|
|
*
|
|
|
|
* A previous version of npxsave() went to great lengths to excecute fnsave
|
|
|
|
* with interrupts enabled in case executing it froze the CPU. This case
|
|
|
|
* can't happen, at least for Intel CPU/NPX's. Spurious IRQ13's don't imply
|
|
|
|
* spurious freezes.
|
1993-06-12 14:58:17 +00:00
|
|
|
*/
|
|
|
|
void
|
|
|
|
npxsave(addr)
|
2001-07-12 06:32:51 +00:00
|
|
|
union savefpu *addr;
|
1993-06-12 14:58:17 +00:00
|
|
|
{
|
1997-07-21 07:57:50 +00:00
|
|
|
|
|
|
|
stop_emulating();
|
2001-07-16 06:00:23 +00:00
|
|
|
fpusave(addr);
|
2001-07-12 06:32:51 +00:00
|
|
|
|
1997-07-21 07:57:50 +00:00
|
|
|
start_emulating();
|
2001-12-11 23:33:44 +00:00
|
|
|
PCPU_SET(fpcurthread, NULL);
|
1993-06-12 14:58:17 +00:00
|
|
|
}
|
|
|
|
|
2002-09-16 19:25:59 +00:00
|
|
|
/*
|
|
|
|
* This should be called with interrupts disabled and only when the owning
|
|
|
|
* FPU thread is non-null.
|
|
|
|
*/
|
|
|
|
void
|
|
|
|
npxdrop()
|
|
|
|
{
|
|
|
|
struct thread *td;
|
|
|
|
|
2004-06-18 02:10:55 +00:00
|
|
|
/*
|
|
|
|
* Discard pending exceptions in the !cpu_fxsr case so that unmasked
|
|
|
|
* ones don't cause a panic on the next frstor.
|
|
|
|
*/
|
|
|
|
#ifdef CPU_ENABLE_SSE
|
|
|
|
if (!cpu_fxsr)
|
|
|
|
#endif
|
|
|
|
fnclex();
|
|
|
|
|
2002-09-16 19:25:59 +00:00
|
|
|
td = PCPU_GET(fpcurthread);
|
|
|
|
PCPU_SET(fpcurthread, NULL);
|
|
|
|
td->td_pcb->pcb_flags &= ~PCB_NPXINITDONE;
|
|
|
|
start_emulating();
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Get the state of the FPU without dropping ownership (if possible).
|
|
|
|
* It returns the FPU ownership status.
|
|
|
|
*/
|
|
|
|
int
|
|
|
|
npxgetregs(td, addr)
|
|
|
|
struct thread *td;
|
|
|
|
union savefpu *addr;
|
|
|
|
{
|
|
|
|
register_t s;
|
|
|
|
|
|
|
|
if (!npx_exists)
|
|
|
|
return (_MC_FPOWNED_NONE);
|
|
|
|
|
|
|
|
if ((td->td_pcb->pcb_flags & PCB_NPXINITDONE) == 0) {
|
|
|
|
if (npx_cleanstate_ready)
|
|
|
|
bcopy(&npx_cleanstate, addr, sizeof(npx_cleanstate));
|
|
|
|
else
|
|
|
|
bzero(addr, sizeof(*addr));
|
|
|
|
return (_MC_FPOWNED_NONE);
|
|
|
|
}
|
|
|
|
s = intr_disable();
|
2003-04-01 00:16:32 +00:00
|
|
|
if (td == PCPU_GET(fpcurthread)) {
|
2002-09-16 19:25:59 +00:00
|
|
|
fpusave(addr);
|
|
|
|
#ifdef CPU_ENABLE_SSE
|
|
|
|
if (!cpu_fxsr)
|
|
|
|
#endif
|
|
|
|
/*
|
|
|
|
* fnsave initializes the FPU and destroys whatever
|
|
|
|
* context it contains. Make sure the FPU owner
|
|
|
|
* starts with a clean state next time.
|
|
|
|
*/
|
|
|
|
npxdrop();
|
|
|
|
intr_restore(s);
|
|
|
|
return (_MC_FPOWNED_FPU);
|
|
|
|
} else {
|
|
|
|
intr_restore(s);
|
|
|
|
bcopy(&td->td_pcb->pcb_save, addr, sizeof(*addr));
|
|
|
|
return (_MC_FPOWNED_PCB);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Set the state of the FPU.
|
|
|
|
*/
|
|
|
|
void
|
|
|
|
npxsetregs(td, addr)
|
|
|
|
struct thread *td;
|
|
|
|
union savefpu *addr;
|
|
|
|
{
|
|
|
|
register_t s;
|
|
|
|
|
|
|
|
if (!npx_exists)
|
|
|
|
return;
|
|
|
|
|
|
|
|
s = intr_disable();
|
2003-03-31 00:32:43 +00:00
|
|
|
if (td == PCPU_GET(fpcurthread)) {
|
2004-06-19 22:24:16 +00:00
|
|
|
#ifdef CPU_ENABLE_SSE
|
|
|
|
if (!cpu_fxsr)
|
|
|
|
#endif
|
|
|
|
fnclex(); /* As in npxdrop(). */
|
2002-09-16 19:25:59 +00:00
|
|
|
fpurstor(addr);
|
|
|
|
intr_restore(s);
|
|
|
|
} else {
|
|
|
|
intr_restore(s);
|
|
|
|
bcopy(addr, &td->td_pcb->pcb_save, sizeof(*addr));
|
|
|
|
}
|
2002-10-25 19:12:16 +00:00
|
|
|
curthread->td_pcb->pcb_flags |= PCB_NPXINITDONE;
|
2002-09-16 19:25:59 +00:00
|
|
|
}
|
|
|
|
|
2001-07-12 06:32:51 +00:00
|
|
|
static void
|
2001-07-16 06:00:23 +00:00
|
|
|
fpusave(addr)
|
2001-07-12 06:32:51 +00:00
|
|
|
union savefpu *addr;
|
|
|
|
{
|
|
|
|
|
2001-08-23 01:03:56 +00:00
|
|
|
#ifdef CPU_ENABLE_SSE
|
|
|
|
if (cpu_fxsr)
|
2001-07-17 13:06:47 +00:00
|
|
|
fxsave(addr);
|
2001-08-23 01:03:56 +00:00
|
|
|
else
|
|
|
|
#endif
|
|
|
|
fnsave(addr);
|
2001-07-12 06:32:51 +00:00
|
|
|
}
|
|
|
|
|
2006-04-19 07:00:19 +00:00
|
|
|
#ifdef CPU_ENABLE_SSE
|
|
|
|
/*
|
|
|
|
* On AuthenticAMD processors, the fxrstor instruction does not restore
|
|
|
|
* the x87's stored last instruction pointer, last data pointer, and last
|
|
|
|
* opcode values, except in the rare case in which the exception summary
|
|
|
|
* (ES) bit in the x87 status word is set to 1.
|
|
|
|
*
|
|
|
|
* In order to avoid leaking this information across processes, we clean
|
|
|
|
* these values by performing a dummy load before executing fxrstor().
|
|
|
|
*/
|
|
|
|
static double dummy_variable = 0.0;
|
|
|
|
static void
|
|
|
|
fpu_clean_state(void)
|
|
|
|
{
|
|
|
|
u_short status;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Clear the ES bit in the x87 status word if it is currently
|
|
|
|
* set, in order to avoid causing a fault in the upcoming load.
|
|
|
|
*/
|
|
|
|
fnstsw(&status);
|
|
|
|
if (status & 0x80)
|
|
|
|
fnclex();
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Load the dummy variable into the x87 stack. This mangles
|
|
|
|
* the x87 stack, but we don't care since we're about to call
|
|
|
|
* fxrstor() anyway.
|
|
|
|
*/
|
|
|
|
__asm __volatile("ffree %%st(7); fld %0" : : "m" (dummy_variable));
|
|
|
|
}
|
|
|
|
#endif /* CPU_ENABLE_SSE */
|
|
|
|
|
2001-07-12 06:32:51 +00:00
|
|
|
static void
|
2001-07-16 06:00:23 +00:00
|
|
|
fpurstor(addr)
|
2001-07-12 06:32:51 +00:00
|
|
|
union savefpu *addr;
|
|
|
|
{
|
2001-08-23 01:03:56 +00:00
|
|
|
|
|
|
|
#ifdef CPU_ENABLE_SSE
|
2006-04-19 07:00:19 +00:00
|
|
|
if (cpu_fxsr) {
|
|
|
|
fpu_clean_state();
|
2001-07-17 13:06:47 +00:00
|
|
|
fxrstor(addr);
|
2006-04-19 07:00:19 +00:00
|
|
|
} else
|
2001-08-23 01:03:56 +00:00
|
|
|
#endif
|
|
|
|
frstor(addr);
|
2001-07-12 06:32:51 +00:00
|
|
|
}
|
|
|
|
|
2001-06-15 07:53:20 +00:00
|
|
|
#ifdef I586_CPU_XXX
|
1998-02-12 21:41:10 +00:00
|
|
|
static long
|
|
|
|
timezero(funcname, func)
|
|
|
|
const char *funcname;
|
2002-03-20 07:51:46 +00:00
|
|
|
void (*func)(void *buf, size_t len);
|
1998-02-12 21:41:10 +00:00
|
|
|
|
|
|
|
{
|
|
|
|
void *buf;
|
2001-03-19 00:28:04 +00:00
|
|
|
#define BUFSIZE 1048576
|
1998-02-12 21:41:10 +00:00
|
|
|
long usec;
|
|
|
|
struct timeval finish, start;
|
|
|
|
|
|
|
|
buf = malloc(BUFSIZE, M_TEMP, M_NOWAIT);
|
|
|
|
if (buf == NULL)
|
|
|
|
return (BUFSIZE);
|
|
|
|
microtime(&start);
|
|
|
|
(*func)(buf, BUFSIZE);
|
|
|
|
microtime(&finish);
|
|
|
|
usec = 1000000 * (finish.tv_sec - start.tv_sec) +
|
|
|
|
finish.tv_usec - start.tv_usec;
|
|
|
|
if (usec <= 0)
|
|
|
|
usec = 1;
|
|
|
|
if (bootverbose)
|
2001-06-15 07:53:20 +00:00
|
|
|
printf("%s bandwidth = %u kBps\n", funcname,
|
2001-03-19 00:28:04 +00:00
|
|
|
(u_int32_t)(((BUFSIZE >> 10) * 1000000) / usec));
|
1998-02-12 21:41:10 +00:00
|
|
|
free(buf, M_TEMP);
|
|
|
|
return (usec);
|
|
|
|
}
|
|
|
|
#endif /* I586_CPU */
|
|
|
|
|
1999-04-16 21:22:55 +00:00
|
|
|
static device_method_t npx_methods[] = {
|
|
|
|
/* Device interface */
|
1999-08-22 19:52:51 +00:00
|
|
|
DEVMETHOD(device_identify, npx_identify),
|
1999-04-16 21:22:55 +00:00
|
|
|
DEVMETHOD(device_probe, npx_probe),
|
|
|
|
DEVMETHOD(device_attach, npx_attach),
|
|
|
|
DEVMETHOD(device_detach, bus_generic_detach),
|
|
|
|
DEVMETHOD(device_shutdown, bus_generic_shutdown),
|
|
|
|
DEVMETHOD(device_suspend, bus_generic_suspend),
|
|
|
|
DEVMETHOD(device_resume, bus_generic_resume),
|
|
|
|
|
|
|
|
{ 0, 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static driver_t npx_driver = {
|
|
|
|
"npx",
|
|
|
|
npx_methods,
|
|
|
|
1, /* no softc */
|
|
|
|
};
|
|
|
|
|
|
|
|
static devclass_t npx_devclass;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We prefer to attach to the root nexus so that the usual case (exception 16)
|
|
|
|
* doesn't describe the processor as being `on isa'.
|
|
|
|
*/
|
|
|
|
DRIVER_MODULE(npx, nexus, npx_driver, npx_devclass, 0, 0);
|
2000-05-04 23:57:32 +00:00
|
|
|
|
2004-02-13 18:04:51 +00:00
|
|
|
#ifdef DEV_ISA
|
2000-05-04 23:57:32 +00:00
|
|
|
/*
|
2001-08-30 09:17:03 +00:00
|
|
|
* This sucks up the legacy ISA support assignments from PNPBIOS/ACPI.
|
2000-05-04 23:57:32 +00:00
|
|
|
*/
|
|
|
|
static struct isa_pnp_id npxisa_ids[] = {
|
|
|
|
{ 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */
|
|
|
|
{ 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static int
|
|
|
|
npxisa_probe(device_t dev)
|
|
|
|
{
|
2000-06-23 08:19:50 +00:00
|
|
|
int result;
|
|
|
|
if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, npxisa_ids)) <= 0) {
|
|
|
|
device_quiet(dev);
|
|
|
|
}
|
|
|
|
return(result);
|
2000-05-04 23:57:32 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
npxisa_attach(device_t dev)
|
|
|
|
{
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static device_method_t npxisa_methods[] = {
|
|
|
|
/* Device interface */
|
|
|
|
DEVMETHOD(device_probe, npxisa_probe),
|
|
|
|
DEVMETHOD(device_attach, npxisa_attach),
|
|
|
|
DEVMETHOD(device_detach, bus_generic_detach),
|
|
|
|
DEVMETHOD(device_shutdown, bus_generic_shutdown),
|
|
|
|
DEVMETHOD(device_suspend, bus_generic_suspend),
|
|
|
|
DEVMETHOD(device_resume, bus_generic_resume),
|
|
|
|
|
|
|
|
{ 0, 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static driver_t npxisa_driver = {
|
|
|
|
"npxisa",
|
|
|
|
npxisa_methods,
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1, /* no softc */
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};
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static devclass_t npxisa_devclass;
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DRIVER_MODULE(npxisa, isa, npxisa_driver, npxisa_devclass, 0, 0);
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2001-10-21 06:05:08 +00:00
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#ifndef PC98
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2001-08-30 09:17:03 +00:00
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DRIVER_MODULE(npxisa, acpi, npxisa_driver, npxisa_devclass, 0, 0);
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2001-10-21 06:05:08 +00:00
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#endif
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2002-01-30 12:41:12 +00:00
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#endif /* DEV_ISA */
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