2012-08-15 05:37:10 +00:00
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/*-
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* Copyright (c) 1994-1998 Mark Brinicombe.
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* Copyright (c) 1994 Brini.
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* All rights reserved.
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*
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* This code is derived from software written for Brini by Mark Brinicombe
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Brini.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: FreeBSD: //depot/projects/arm/src/sys/arm/at91/kb920x_machdep.c, rev 45
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*/
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#include "opt_ddb.h"
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#include "opt_platform.h"
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#define _ARM32_BUS_DMA_PRIVATE
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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2012-11-03 22:39:07 +00:00
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2012-08-15 05:37:10 +00:00
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#include <machine/bus.h>
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2012-11-03 22:39:07 +00:00
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#include <machine/frame.h> /* For trapframe_t, used in <machine/machdep.h> */
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2012-08-15 05:37:10 +00:00
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#include <machine/machdep.h>
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2012-11-03 22:39:07 +00:00
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#include <machine/pmap.h>
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2012-08-15 05:37:10 +00:00
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2012-11-03 22:39:07 +00:00
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#include <arm/lpc/lpcreg.h>
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#include <arm/lpc/lpcvar.h>
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2012-09-22 22:41:38 +00:00
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2012-11-03 22:39:07 +00:00
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#include <dev/fdt/fdt_common.h>
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#include <dev/ic/ns16550.h>
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2012-08-15 05:37:10 +00:00
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2012-09-26 10:07:53 +00:00
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vm_offset_t
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initarm_lastaddr(void)
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{
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if (fdt_immr_addr(LPC_DEV_BASE) != 0)
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while (1);
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/* Platform-specific initialisation */
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return (fdt_immr_va - ARM_NOCACHE_KVA_SIZE);
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}
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void
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initarm_gpio_init(void)
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{
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2012-10-30 06:11:09 +00:00
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/*
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* Set initial values of GPIO output ports
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*/
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platform_gpio_init();
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2012-09-26 10:07:53 +00:00
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}
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void
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initarm_late_init(void)
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{
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}
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2012-08-15 05:37:10 +00:00
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#define FDT_DEVMAP_MAX (1 + 2 + 1 + 1)
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static struct pmap_devmap fdt_devmap[FDT_DEVMAP_MAX] = {
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{ 0, 0, 0, 0, 0, }
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};
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/*
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* Construct pmap_devmap[] with DT-derived config data.
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*/
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2012-11-03 22:39:07 +00:00
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int
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2012-08-15 05:37:10 +00:00
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platform_devmap_init(void)
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{
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/*
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* IMMR range.
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*/
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fdt_devmap[0].pd_va = fdt_immr_va;
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fdt_devmap[0].pd_pa = fdt_immr_pa;
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fdt_devmap[0].pd_size = fdt_immr_size;
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fdt_devmap[0].pd_prot = VM_PROT_READ | VM_PROT_WRITE;
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fdt_devmap[0].pd_cache = PTE_NOCACHE;
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pmap_devmap_bootstrap_table = &fdt_devmap[0];
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return (0);
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}
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struct arm32_dma_range *
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bus_dma_get_range(void)
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{
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return (NULL);
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}
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int
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bus_dma_get_range_nb(void)
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{
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return (0);
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}
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void
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cpu_reset(void)
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{
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/* Enable WDT */
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bus_space_write_4(fdtbus_bs_tag,
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LPC_CLKPWR_BASE, LPC_CLKPWR_TIMCLK_CTRL,
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LPC_CLKPWR_TIMCLK_CTRL_WATCHDOG);
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/* Instant assert of RESETOUT_N with pulse length 1ms */
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bus_space_write_4(fdtbus_bs_tag, LPC_WDTIM_BASE, LPC_WDTIM_PULSE, 13000);
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bus_space_write_4(fdtbus_bs_tag, LPC_WDTIM_BASE, LPC_WDTIM_MCTRL, 0x70);
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for (;;);
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}
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2012-11-03 22:39:07 +00:00
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