169 lines
3.6 KiB
C
169 lines
3.6 KiB
C
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/*
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* Copyright (C) 2003
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* Hidetoshi Shimokawa. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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*
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* This product includes software developed by Hidetoshi Shimokawa.
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*
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* 4. Neither the name of the author nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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struct phyreg_base {
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#if BYTE_ORDER == BIG_ENDIAN
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u_int8_t phy_id:6,
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r:1,
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cps:1;
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u_int8_t rhb:1,
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ibr:1,
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gap_count:6;
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u_int8_t extended:3,
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num_ports:5;
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u_int8_t phy_speed:3,
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:1,
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delay:4;
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u_int8_t lctrl:1,
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c:1,
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jitter:3,
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pwr_class:3;
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u_int8_t wdie:1,
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isbr:1,
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ctoi:1,
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cpsi:1,
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stoi:1,
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pei:1,
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eaa:1,
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emc:1;
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u_int8_t legacy_spd:3,
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blink:1,
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bridge:2,
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:2;
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u_int8_t page_select:3,
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:1,
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port_select:4;
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#else
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u_int8_t cps:1,
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r:1,
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phy_id:6;
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u_int8_t gap_count:6,
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ibr:1,
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rhb:1;
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u_int8_t num_ports:5,
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extended:3;
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u_int8_t delay:4,
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:1,
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phy_speed:3;
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u_int8_t pwr_class:3,
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jitter:3,
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c:1,
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lctrl:1;
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u_int8_t emc:1,
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eaa:1,
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pei:1,
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stoi:1,
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cpsi:1,
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ctoi:1,
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isbr:1,
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wdie:1;
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u_int8_t :2,
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bridge:2,
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blink:1,
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legacy_spd:3;
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u_int8_t port_select:4,
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:1,
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page_select:3;
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#endif
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};
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struct phyreg_page0 {
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#if BYTE_ORDER == BIG_ENDIAN
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u_int8_t astat:2,
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bstat:2,
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ch:1,
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con:1,
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rxok:1,
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dis:1;
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u_int8_t negotiated_speed:3,
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pie:1,
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fault:1,
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stanby_fault:1,
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disscrm:1,
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b_only:1;
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u_int8_t dc_connected:1,
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max_port_speed:3,
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lpp:1,
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cable_speed:3;
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u_int8_t connection_unreliable:1,
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:3,
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beta_mode:1,
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:3;
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u_int8_t port_error;
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u_int8_t :5,
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loop_disable:1,
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in_standby:1,
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hard_disable:1;
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u_int8_t :8;
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u_int8_t :8;
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#else
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u_int8_t dis:1,
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rxok:1,
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con:1,
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ch:1,
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bstat:2,
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astat:2;
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u_int8_t b_only:1,
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disscrm:1,
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stanby_fault:1,
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fault:1,
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pie:1,
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negotiated_speed:3;
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u_int8_t cable_speed:3,
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lpp:1,
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max_port_speed:3,
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dc_connected:1;
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u_int8_t :3,
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beta_mode:1,
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:3,
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connection_unreliable:1;
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u_int8_t port_error;
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u_int8_t hard_disable:1,
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in_standby:1,
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loop_disable:1,
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:5;
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u_int8_t :8;
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u_int8_t :8;
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#endif
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};
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struct phyreg_page1 {
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u_int8_t compliance;
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u_int8_t :8;
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u_int8_t vendor_id[3];
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u_int8_t product_id[3];
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};
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