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freebsd-skq/sys/mips/conf/AP96.hints

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Introduce configuration files for AP94 and AP96. This uses the new firmware(9) method for squirreling away the EEPROM contents from SPI flash so ath(4) can get to them later. It won't work out of the box just yet - you have to add this to if_ath_pci.c: #define ATH_EEPROM_FIRMWARE .. until I've added it as a configuration option and updated things.
2012-04-13 08:52:25 +00:00
# $FreeBSD$
Convert AP96 to use the mdioproxy and ARGE_MDIO option. arge1 still works (it's the standalone PHY) but arge0 and the other switch ports don't work. They're enumerated though, demonstrating that the mdiobus abstraction is correctly working.
2012-05-01 06:21:02 +00:00
# arge0 MDIO bus - there's no arge1 MDIO bus for AR71xx
hint.argemdio.0.at="nexus0"
hint.argemdio.0.maddr=0x19000000
hint.argemdio.0.msize=0x1000
hint.argemdio.0.order=0
Add switch support to AP96.
2012-05-11 21:13:43 +00:00
# This creates an automatic mdioproxy0!
Convert AP96 to use the mdioproxy and ARGE_MDIO option. arge1 still works (it's the standalone PHY) but arge0 and the other switch ports don't work. They're enumerated though, demonstrating that the mdiobus abstraction is correctly working.
2012-05-01 06:21:02 +00:00
Add switch support to AP96.
2012-05-11 21:13:43 +00:00
# The switch automatically probes off of mdio0, and will
# create an mdioproxy1.
Convert AP96 to use the mdioproxy and ARGE_MDIO option. arge1 still works (it's the standalone PHY) but arge0 and the other switch ports don't work. They're enumerated though, demonstrating that the mdiobus abstraction is correctly working.
2012-05-01 06:21:02 +00:00
Add in the AP96 phy configuration from openwrt. * arge0 doesn't (yet) work via the switch PHY ports; I'm not sure why. * arge1 maps to the WAN port. That works. TODO: * The PLL register needs a different (non-default) value for Gigabit Ethernet. The board setup code needs to be extended a bit to allow for non-default pll_1000 values - right now, those values come out of hard-coded values in the per-chip set_pll_ge() routines. Obtained from: Linux / OpenWRT
2012-04-15 22:59:56 +00:00
# TODO: RGMII
Add switch support to AP96.
2012-05-11 21:13:43 +00:00
hint.arge.0.phymask=0x0 # Nothing attached here (XXX?)
Add in the AP96 phy configuration from openwrt. * arge0 doesn't (yet) work via the switch PHY ports; I'm not sure why. * arge1 maps to the WAN port. That works. TODO: * The PLL register needs a different (non-default) value for Gigabit Ethernet. The board setup code needs to be extended a bit to allow for non-default pll_1000 values - right now, those values come out of hard-coded values in the per-chip set_pll_ge() routines. Obtained from: Linux / OpenWRT
2012-04-15 22:59:56 +00:00
hint.arge.0.media=1000
Introduce configuration files for AP94 and AP96. This uses the new firmware(9) method for squirreling away the EEPROM contents from SPI flash so ath(4) can get to them later. It won't work out of the box just yet - you have to add this to if_ath_pci.c: #define ATH_EEPROM_FIRMWARE .. until I've added it as a configuration option and updated things.
2012-04-13 08:52:25 +00:00
hint.arge.0.fduplex=1
* Force the ethernet MII configuration to be RGMII * Populate the "pll_1000" field, which will soon be used to override the PLL configuration from the default value. Obtained from: Linux OpenWRT
2012-05-02 06:19:26 +00:00
hint.arge.0.miimode=3 # RGMII
Introduce configuration files for AP94 and AP96. This uses the new firmware(9) method for squirreling away the EEPROM contents from SPI flash so ath(4) can get to them later. It won't work out of the box just yet - you have to add this to if_ath_pci.c: #define ATH_EEPROM_FIRMWARE .. until I've added it as a configuration option and updated things.
2012-04-13 08:52:25 +00:00
Add in the AP96 phy configuration from openwrt. * arge0 doesn't (yet) work via the switch PHY ports; I'm not sure why. * arge1 maps to the WAN port. That works. TODO: * The PLL register needs a different (non-default) value for Gigabit Ethernet. The board setup code needs to be extended a bit to allow for non-default pll_1000 values - right now, those values come out of hard-coded values in the per-chip set_pll_ge() routines. Obtained from: Linux / OpenWRT
2012-04-15 22:59:56 +00:00
# TODO: RGMII
hint.arge.1.phymask=0x10
Disable the pll_1000 hint for now, the upcoming work enables it and it breaks without the switch PHY code.
2012-05-02 07:41:26 +00:00
# hint.arge.1.pll_1000 = 0x1f000000
Convert AP96 to use the mdioproxy and ARGE_MDIO option. arge1 still works (it's the standalone PHY) but arge0 and the other switch ports don't work. They're enumerated though, demonstrating that the mdiobus abstraction is correctly working.
2012-05-01 06:21:02 +00:00
# For now, rendezouvs this on the arge0 mdiobus.
# Later, this will rendezvous via the AR8316 switch.
* Force the ethernet MII configuration to be RGMII * Populate the "pll_1000" field, which will soon be used to override the PLL configuration from the default value. Obtained from: Linux OpenWRT
2012-05-02 06:19:26 +00:00
hint.arge.1.miimode=3 # RGMII
Add switch support to AP96.
2012-05-11 21:13:43 +00:00
hint.arge.1.mdio=mdioproxy1 # off the switch mdiobus
Introduce configuration files for AP94 and AP96. This uses the new firmware(9) method for squirreling away the EEPROM contents from SPI flash so ath(4) can get to them later. It won't work out of the box just yet - you have to add this to if_ath_pci.c: #define ATH_EEPROM_FIRMWARE .. until I've added it as a configuration option and updated things.
2012-04-13 08:52:25 +00:00
Update AP96 to directly attach an arswitch.
2012-11-07 23:50:28 +00:00
# AR8316 switch on MDIO0
hint.arswitch.0.at="mdio0"
hint.arswitch.0.is_7240=0
hint.arswitch.0.numphys=4
hint.arswitch.0.phy4cpu=1
hint.arswitch.0.is_rgmii=1
hint.arswitch.0.is_gmii=0
Introduce configuration files for AP94 and AP96. This uses the new firmware(9) method for squirreling away the EEPROM contents from SPI flash so ath(4) can get to them later. It won't work out of the box just yet - you have to add this to if_ath_pci.c: #define ATH_EEPROM_FIRMWARE .. until I've added it as a configuration option and updated things.
2012-04-13 08:52:25 +00:00
# ath0 - slot 17
hint.pcib.0.bus.0.17.0.ath_fixup_addr=0x1fff1000
hint.pcib.0.bus.0.17.0.ath_fixup_size=4096
# ath1 - slot 18
hint.pcib.0.bus.0.18.0.ath_fixup_addr=0x1fff5000
hint.pcib.0.bus.0.18.0.ath_fixup_size=4096
# .. and now, telling each ath(4) NIC where to find the firmware
# image.
hint.ath.0.eeprom_firmware="pcib.0.bus.0.17.0.eeprom_firmware"
hint.ath.1.eeprom_firmware="pcib.0.bus.0.18.0.eeprom_firmware"
Flesh out the rest of the AP96 board/config.
2012-04-13 20:23:32 +00:00
# The default flash layout:
# uboot: 192k
# env: 64k
# rootfs: 6144k
# uimage (kernel): 1728k
# caldata: 64k
#
# bootargs=console=ttyS0,115200 root=31:02 rootfstype=jffs2 init=/sbin/init
# mtdparts=ar7100-nor0:192k(uboot),64k(env),6144k(rootfs),1728k(uImage),64k(caldata) mem=64M
#
# We steal 64k from the end of rootfs to store the local config.
hint.map.0.at="flash/spi0"
hint.map.0.start=0x00000000
hint.map.0.end=0x000030000
hint.map.0.name="uboot"
hint.map.0.readonly=1
hint.map.1.at="flash/spi0"
hint.map.1.start=0x00030000
hint.map.1.end=0x00040000
hint.map.1.name="uboot-env"
hint.map.1.readonly=1
hint.map.2.at="flash/spi0"
hint.map.2.start=0x00040000
hint.map.2.end=0x00630000
hint.map.2.name="rootfs"
hint.map.2.readonly=1
hint.map.3.at="flash/spi0"
hint.map.3.start=0x00630000
hint.map.3.end=0x00640000
hint.map.3.name="cfg"
hint.map.3.readonly=0
hint.map.4.at="flash/spi0"
hint.map.4.start=0x00640000
hint.map.4.end=0x007f0000
hint.map.4.name="kernel"
hint.map.4.readonly=1
hint.map.5.at="flash/spi0"
hint.map.5.start=0x007f0000
hint.map.5.end=0x00800000
hint.map.5.name="art"
hint.map.5.readonly=1
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