316 lines
16 KiB
C
316 lines
16 KiB
C
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/***********************license start***************
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* Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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*
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* * Neither the name of Cavium Networks nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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*
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
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* OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
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* RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
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* REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
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* DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
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* OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
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* PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
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* POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT
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* OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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*
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*
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* For any questions regarding licensing please contact marketing@caviumnetworks.com
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*
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***********************license end**************************************/
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/**
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* @file
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*
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* This header file defines the work queue entry (wqe) data structure.
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* Since this is a commonly used structure that depends on structures
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* from several hardware blocks, those definitions have been placed
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* in this file to create a single point of definition of the wqe
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* format.
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* Data structures are still named according to the block that they
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* relate to.
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*
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* This file must not depend on any other header files, except for cvmx.h!!!
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*
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*
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* <hr>$Revision: 41586 $<hr>
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*
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*
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*/
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#ifndef __CVMX_WQE_H__
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#define __CVMX_WQE_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define OCT_TAG_TYPE_STRING(x) (((x) == CVMX_POW_TAG_TYPE_ORDERED) ? "ORDERED" : \
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(((x) == CVMX_POW_TAG_TYPE_ATOMIC) ? "ATOMIC" : \
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(((x) == CVMX_POW_TAG_TYPE_NULL) ? "NULL" : \
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"NULL_NULL")))
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/**
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* HW decode / err_code in work queue entry
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*/
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typedef union
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{
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uint64_t u64;
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/** Use this struct if the hardware determines that the packet is IP */
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struct
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{
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uint64_t bufs : 8; /**< HW sets this to the number of buffers used by this packet */
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uint64_t ip_offset : 8; /**< HW sets to the number of L2 bytes prior to the IP */
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uint64_t vlan_valid : 1; /**< set to 1 if we found DSA/VLAN in the L2 */
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uint64_t vlan_stacked : 1; /**< Set to 1 if the DSA/VLAN tag is stacked */
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uint64_t unassigned : 1;
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uint64_t vlan_cfi : 1; /**< HW sets to the DSA/VLAN CFI flag (valid when vlan_valid) */
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uint64_t vlan_id :12; /**< HW sets to the DSA/VLAN_ID field (valid when vlan_valid) */
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uint64_t pr : 4; /**< Ring Identifier (if PCIe). Requires PIP_GBL_CTL[RING_EN]=1 */
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uint64_t unassigned2 : 8;
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uint64_t dec_ipcomp : 1; /**< the packet needs to be decompressed */
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uint64_t tcp_or_udp : 1; /**< the packet is either TCP or UDP */
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uint64_t dec_ipsec : 1; /**< the packet needs to be decrypted (ESP or AH) */
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uint64_t is_v6 : 1; /**< the packet is IPv6 */
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// (rcv_error, not_IP, IP_exc, is_frag, L4_error, software, etc.)
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uint64_t software : 1; /**< reserved for software use, hardware will clear on packet creation */
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// exceptional conditions below
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uint64_t L4_error : 1; /**< the receive interface hardware detected an L4 error (only applies if !is_frag)
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(only applies if !rcv_error && !not_IP && !IP_exc && !is_frag)
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failure indicated in err_code below, decode:
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- 1 = Malformed L4
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- 2 = L4 Checksum Error: the L4 checksum value is
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- 3 = UDP Length Error: The UDP length field would make the UDP data longer than what
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remains in the IP packet (as defined by the IP header length field).
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- 4 = Bad L4 Port: either the source or destination TCP/UDP port is 0.
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- 8 = TCP FIN Only: the packet is TCP and only the FIN flag set.
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- 9 = TCP No Flags: the packet is TCP and no flags are set.
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- 10 = TCP FIN RST: the packet is TCP and both FIN and RST are set.
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- 11 = TCP SYN URG: the packet is TCP and both SYN and URG are set.
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- 12 = TCP SYN RST: the packet is TCP and both SYN and RST are set.
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- 13 = TCP SYN FIN: the packet is TCP and both SYN and FIN are set. */
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uint64_t is_frag : 1; /**< set if the packet is a fragment */
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uint64_t IP_exc : 1; /**< the receive interface hardware detected an IP error / exception
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(only applies if !rcv_error && !not_IP) failure indicated in err_code below, decode:
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- 1 = Not IP: the IP version field is neither 4 nor 6.
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- 2 = IPv4 Header Checksum Error: the IPv4 header has a checksum violation.
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- 3 = IP Malformed Header: the packet is not long enough to contain the IP header.
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- 4 = IP Malformed: the packet is not long enough to contain the bytes indicated by the IP
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header. Pad is allowed.
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- 5 = IP TTL Hop: the IPv4 TTL field or the IPv6 Hop Count field are zero.
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- 6 = IP Options */
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uint64_t is_bcast : 1; /**< set if the hardware determined that the packet is a broadcast */
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uint64_t is_mcast : 1; /**< set if the hardware determined that the packet is a multi-cast */
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uint64_t not_IP : 1; /**< set if the packet may not be IP (must be zero in this case) */
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uint64_t rcv_error : 1; /**< the receive interface hardware detected a receive error (must be zero in this case) */
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/* lower err_code = first-level descriptor of the work */
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/* zero for packet submitted by hardware that isn't on the slow path */
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uint64_t err_code : 8; /**< type is cvmx_pip_err_t */
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} s;
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/**< use this to get at the 16 vlan bits */
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struct
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{
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uint64_t unused1 :16;
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uint64_t vlan :16;
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uint64_t unused2 :32;
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} svlan;
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/**< use this struct if the hardware could not determine that the packet is ip */
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struct
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{
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uint64_t bufs : 8; /**< HW sets this to the number of buffers used by this packet */
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uint64_t unused : 8;
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uint64_t vlan_valid : 1; /**< set to 1 if we found DSA/VLAN in the L2 */
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uint64_t vlan_stacked : 1; /**< Set to 1 if the DSA/VLAN tag is stacked */
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uint64_t unassigned : 1;
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uint64_t vlan_cfi : 1; /**< HW sets to the DSA/VLAN CFI flag (valid when vlan_valid) */
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uint64_t vlan_id :12; /**< HW sets to the DSA/VLAN_ID field (valid when vlan_valid) */
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uint64_t pr : 4; /**< Ring Identifier (if PCIe). Requires PIP_GBL_CTL[RING_EN]=1 */
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uint64_t unassigned2 :12;
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uint64_t software : 1; /**< reserved for software use, hardware will clear on packet creation */
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uint64_t unassigned3 : 1;
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uint64_t is_rarp : 1; /**< set if the hardware determined that the packet is rarp */
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uint64_t is_arp : 1; /**< set if the hardware determined that the packet is arp */
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uint64_t is_bcast : 1; /**< set if the hardware determined that the packet is a broadcast */
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uint64_t is_mcast : 1; /**< set if the hardware determined that the packet is a multi-cast */
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uint64_t not_IP : 1; /**< set if the packet may not be IP (must be one in this case) */
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uint64_t rcv_error : 1; /**< the receive interface hardware detected a receive error.
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Failure indicated in err_code below, decode:
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- 1 = partial error: a packet was partially received, but internal
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buffering / bandwidth was not adequate to receive the entire packet.
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- 2 = jabber error: the RGMII packet was too large and is truncated.
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- 3 = overrun error: the RGMII packet is longer than allowed and had
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an FCS error.
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- 4 = oversize error: the RGMII packet is longer than allowed.
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- 5 = alignment error: the RGMII packet is not an integer number of bytes
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and had an FCS error (100M and 10M only).
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- 6 = fragment error: the RGMII packet is shorter than allowed and had an
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FCS error.
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- 7 = GMX FCS error: the RGMII packet had an FCS error.
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- 8 = undersize error: the RGMII packet is shorter than allowed.
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- 9 = extend error: the RGMII packet had an extend error.
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- 10 = length mismatch error: the RGMII packet had a length that did not
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match the length field in the L2 HDR.
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- 11 = RGMII RX error/SPI4 DIP4 Error: the RGMII packet had one or more
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data reception errors (RXERR) or the SPI4 packet had one or more DIP4
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errors.
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- 12 = RGMII skip error/SPI4 Abort Error: the RGMII packet was not large
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enough to cover the skipped bytes or the SPI4 packet was terminated
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with an About EOPS.
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- 13 = RGMII nibble error/SPI4 Port NXA Error: the RGMII packet had a
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studder error (data not repeated - 10/100M only) or the SPI4 packet
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was sent to an NXA.
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- 16 = FCS error: a SPI4.2 packet had an FCS error.
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- 17 = Skip error: a packet was not large enough to cover the skipped bytes.
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- 18 = L2 header malformed: the packet is not long enough to contain the L2 */
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/* lower err_code = first-level descriptor of the work */
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/* zero for packet submitted by hardware that isn't on the slow path */
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uint64_t err_code : 8; // type is cvmx_pip_err_t (union, so can't use directly
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} snoip;
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} cvmx_pip_wqe_word2;
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/**
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* Work queue entry format
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*
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* must be 8-byte aligned
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*/
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typedef struct
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{
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/*****************************************************************
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* WORD 0
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* HW WRITE: the following 64 bits are filled by HW when a packet arrives
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*/
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/**
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* raw chksum result generated by the HW
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*/
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uint16_t hw_chksum;
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/**
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* Field unused by hardware - available for software
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*/
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uint8_t unused;
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/**
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* Next pointer used by hardware for list maintenance.
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* May be written/read by HW before the work queue
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* entry is scheduled to a PP
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* (Only 36 bits used in Octeon 1)
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*/
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uint64_t next_ptr : 40;
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/*****************************************************************
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* WORD 1
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* HW WRITE: the following 64 bits are filled by HW when a packet arrives
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*/
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/**
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* HW sets to the total number of bytes in the packet
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*/
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uint64_t len :16;
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/**
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* HW sets this to input physical port
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*/
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uint64_t ipprt : 6;
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/**
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* HW sets this to what it thought the priority of the input packet was
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*/
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uint64_t qos : 3;
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/**
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* the group that the work queue entry will be scheduled to
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*/
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uint64_t grp : 4;
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/**
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* the type of the tag (ORDERED, ATOMIC, NULL)
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*/
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cvmx_pow_tag_type_t tag_type : 3;
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/**
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* the synchronization/ordering tag
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*/
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uint64_t tag :32;
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/**
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* WORD 2
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* HW WRITE: the following 64-bits are filled in by hardware when a packet arrives
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* This indicates a variety of status and error conditions.
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*/
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cvmx_pip_wqe_word2 word2;
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/**
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* Pointer to the first segment of the packet.
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*/
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cvmx_buf_ptr_t packet_ptr;
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/**
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* HW WRITE: octeon will fill in a programmable amount from the
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* packet, up to (at most, but perhaps less) the amount
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* needed to fill the work queue entry to 128 bytes
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* If the packet is recognized to be IP, the hardware starts (except that
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* the IPv4 header is padded for appropriate alignment) writing here where
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* the IP header starts.
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* If the packet is not recognized to be IP, the hardware starts writing
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* the beginning of the packet here.
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*/
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uint8_t packet_data[96];
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/**
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* If desired, SW can make the work Q entry any length. For the
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* purposes of discussion here, Assume 128B always, as this is all that
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* the hardware deals with.
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*
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*/
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} CVMX_CACHE_LINE_ALIGNED cvmx_wqe_t;
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#ifdef __cplusplus
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}
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#endif
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#endif /* __CVMX_WQE_H__ */
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