FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64,
mips32r2 and mips64r2 (and close relatives) processors. There
presently is support for ADMtek ADM5120, A mips 4Kc in a malta board,
the RB533 routerboard (based on IDT RC32434) and some preliminary
support for sibtye/broadcom designs. Other hardware support will be
forthcomcing.
This port boots multiuser under gxemul emulating the malta board and
also bootstraps on the hardware whose support is forthcoming...
Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard,
Randall Stewert and others that have contributed to the mips2 and/or
mips2-jnpr perforce branches. Juniper contirbuted a generic mips port
late in the life cycle of the misp2 branch. Warner Losh merged the
mips2 and Juniper code bases, and others list above have worked for
the past several months to get to multiuser.
In addition, the mips2 work owe a debt to the trail blazing efforts of
the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
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/* $NetBSD: if_admswvar.h,v 1.1 2007/03/20 08:52:02 dyoung Exp $ */
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/*-
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* Copyright (c) 2007 Ruslan Ermilov and Vsevolod Lobko.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* 3. The names of the authors may not be used to endorse or promote
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* products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
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* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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* OF SUCH DAMAGE.
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*/
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#ifndef _IF_ADMSWVAR_H_
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#define _IF_ADMSWVAR_H_
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/mbuf.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <sys/socket.h>
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#include <sys/sockio.h>
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#include <sys/sysctl.h>
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#include <machine/bus.h>
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#include <net/ethernet.h>
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#include <net/if.h>
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#include <net/if_arp.h>
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#include <net/if_dl.h>
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#include <net/if_media.h>
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#include <net/if_mib.h>
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#include <net/if_types.h>
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#ifdef INET
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#include <netinet/in.h>
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#include <netinet/in_systm.h>
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#include <netinet/in_var.h>
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#include <netinet/ip.h>
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#endif
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#include <net/bpf.h>
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#include <net/bpfdesc.h>
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#include <dev/mii/mii.h>
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#include <dev/mii/miivar.h>
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2008-09-10 03:49:08 +00:00
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#include <mips/adm5120/adm5120reg.h>
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#include <mips/adm5120/if_admswreg.h>
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FreeBSD/mips port. The FreeBSD/mips port targets mips32, mips64,
mips32r2 and mips64r2 (and close relatives) processors. There
presently is support for ADMtek ADM5120, A mips 4Kc in a malta board,
the RB533 routerboard (based on IDT RC32434) and some preliminary
support for sibtye/broadcom designs. Other hardware support will be
forthcomcing.
This port boots multiuser under gxemul emulating the malta board and
also bootstraps on the hardware whose support is forthcoming...
Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard,
Randall Stewert and others that have contributed to the mips2 and/or
mips2-jnpr perforce branches. Juniper contirbuted a generic mips port
late in the life cycle of the misp2 branch. Warner Losh merged the
mips2 and Juniper code bases, and others list above have worked for
the past several months to get to multiuser.
In addition, the mips2 work owe a debt to the trail blazing efforts of
the original mips branch in perforce done by Juli Mallett.
2008-04-13 07:44:55 +00:00
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#define MAC_BUFLEN 0x07ff
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#define ADMSW_NTXHDESC 4
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#define ADMSW_NRXHDESC 32
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#define ADMSW_NTXLDESC 32
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#define ADMSW_NRXLDESC 32
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#define ADMSW_NTXHDESC_MASK (ADMSW_NTXHDESC - 1)
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#define ADMSW_NRXHDESC_MASK (ADMSW_NRXHDESC - 1)
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#define ADMSW_NTXLDESC_MASK (ADMSW_NTXLDESC - 1)
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#define ADMSW_NRXLDESC_MASK (ADMSW_NRXLDESC - 1)
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#define ADMSW_NEXTTXH(x) (((x) + 1) & ADMSW_NTXHDESC_MASK)
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#define ADMSW_NEXTRXH(x) (((x) + 1) & ADMSW_NRXHDESC_MASK)
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#define ADMSW_NEXTTXL(x) (((x) + 1) & ADMSW_NTXLDESC_MASK)
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#define ADMSW_NEXTRXL(x) (((x) + 1) & ADMSW_NRXLDESC_MASK)
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#define ADMSW_IRQ 9
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struct admsw_control_data {
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/* The transmit descriptors. */
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struct admsw_desc acd_txhdescs[ADMSW_NTXHDESC];
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/* The receive descriptors. */
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struct admsw_desc acd_rxhdescs[ADMSW_NRXHDESC];
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/* The transmit descriptors. */
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struct admsw_desc acd_txldescs[ADMSW_NTXLDESC];
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/* The receive descriptors. */
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struct admsw_desc acd_rxldescs[ADMSW_NRXLDESC];
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};
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#define ADMSW_CDOFF(x) offsetof(struct admsw_control_data, x)
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#define ADMSW_CDTXHOFF(x) ADMSW_CDOFF(acd_txhdescs[(x)])
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#define ADMSW_CDTXLOFF(x) ADMSW_CDOFF(acd_txldescs[(x)])
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#define ADMSW_CDRXHOFF(x) ADMSW_CDOFF(acd_rxhdescs[(x)])
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#define ADMSW_CDRXLOFF(x) ADMSW_CDOFF(acd_rxldescs[(x)])
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struct admsw_descsoft {
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struct mbuf *ds_mbuf;
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bus_dmamap_t ds_dmamap;
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/* Up to 2 segments */
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uint32_t ds_addr[2];
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uint32_t ds_len[2];
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uint32_t ds_nsegs;
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};
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/*
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* Software state per device.
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*/
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struct admsw_softc {
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device_t sc_dev; /* generic device information */
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uint8_t sc_enaddr[ETHER_ADDR_LEN];
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bus_dma_tag_t sc_control_dmat;
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/* bus DMA tag for control structs*/
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bus_dma_tag_t sc_bufs_dmat; /* bus DMA tag for buffers */
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struct ifmedia sc_ifmedia[SW_DEVS];
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int ndevs; /* number of IFF_RUNNING interfaces */
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struct ifnet *sc_ifnet[SW_DEVS];
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/* Ethernet common data */
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void *sc_ih; /* interrupt cookie */
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struct resource *irq_res;
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struct resource *mem_res;
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bus_dmamap_t sc_cddmamap; /* control data DMA map */
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uint32_t sc_cddma;
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struct admsw_control_data *sc_control_data;
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struct admsw_descsoft sc_txhsoft[ADMSW_NTXHDESC];
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struct admsw_descsoft sc_rxhsoft[ADMSW_NRXHDESC];
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struct admsw_descsoft sc_txlsoft[ADMSW_NTXLDESC];
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struct admsw_descsoft sc_rxlsoft[ADMSW_NRXLDESC];
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#define sc_txhdescs sc_control_data->acd_txhdescs
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#define sc_rxhdescs sc_control_data->acd_rxhdescs
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#define sc_txldescs sc_control_data->acd_txldescs
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#define sc_rxldescs sc_control_data->acd_rxldescs
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int sc_txfree; /* number of free Tx descriptors */
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int sc_txnext; /* next Tx descriptor to use */
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int sc_txdirty; /* first dirty Tx descriptor */
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int sc_rxptr; /* next ready Rx descriptor */
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};
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#define ADMSW_CDTXHADDR(sc, x) ((sc)->sc_cddma + ADMSW_CDTXHOFF((x)))
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#define ADMSW_CDTXLADDR(sc, x) ((sc)->sc_cddma + ADMSW_CDTXLOFF((x)))
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#define ADMSW_CDRXHADDR(sc, x) ((sc)->sc_cddma + ADMSW_CDRXHOFF((x)))
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#define ADMSW_CDRXLADDR(sc, x) ((sc)->sc_cddma + ADMSW_CDRXLOFF((x)))
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#define ADMSW_CDTXHSYNC(sc, x, ops) \
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bus_dmamap_sync((sc)->sc_control_dmat, (sc)->sc_cddmamap, (ops))
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#define ADMSW_CDTXLSYNC(sc, x, ops) \
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bus_dmamap_sync((sc)->sc_control_dmat, (sc)->sc_cddmamap, (ops))
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#define ADMSW_CDRXHSYNC(sc, x, ops) \
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bus_dmamap_sync((sc)->sc_control_dmat, (sc)->sc_cddmamap, (ops))
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#define ADMSW_CDRXLSYNC(sc, x, ops) \
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bus_dmamap_sync((sc)->sc_control_dmat, (sc)->sc_cddmamap, (ops))
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#define ADMSW_INIT_RXHDESC(sc, x) \
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do { \
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struct admsw_descsoft *__ds = &(sc)->sc_rxhsoft[(x)]; \
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struct admsw_desc *__desc = &(sc)->sc_rxhdescs[(x)]; \
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struct mbuf *__m = __ds->ds_mbuf; \
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\
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__m->m_data = __m->m_ext.ext_buf + 2; \
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__desc->data = __ds->ds_addr[0] + 2; \
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__desc->cntl = 0; \
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__desc->len = min(MCLBYTES - 2, MAC_BUFLEN - 2); \
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__desc->status = 0; \
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if ((x) == ADMSW_NRXHDESC - 1) \
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__desc->data |= ADM5120_DMA_RINGEND; \
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__desc->data |= ADM5120_DMA_OWN; \
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ADMSW_CDRXHSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \
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} while (0)
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#define ADMSW_INIT_RXLDESC(sc, x) \
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do { \
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struct admsw_descsoft *__ds = &(sc)->sc_rxlsoft[(x)]; \
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struct admsw_desc *__desc = &(sc)->sc_rxldescs[(x)]; \
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struct mbuf *__m = __ds->ds_mbuf; \
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\
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__m->m_data = __m->m_ext.ext_buf + 2; \
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__desc->data = __ds->ds_addr[0] + 2; \
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__desc->cntl = 0; \
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__desc->len = min(MCLBYTES - 2, MAC_BUFLEN - 2); \
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__desc->status = 0; \
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if ((x) == ADMSW_NRXLDESC - 1) \
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__desc->data |= ADM5120_DMA_RINGEND; \
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__desc->data |= ADM5120_DMA_OWN; \
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ADMSW_CDRXLSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \
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} while (0)
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void admwdog_attach(struct admsw_softc *);
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#endif /* _IF_ADMSWVAR_H_ */
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